Applications of ATPG
- 1. Applications of ATPG By Ushaswini Chowdary.M
- 2. Introduction • Here we show that ATPG technology, in addition to generating high- quality tests for various fault models, also offers efficient techniques for analyzing designs during design verification and optimization. • Already, ATPG has been used to generate tests not only to screen out chips with manufacturing defects but also to identify design errors and timing problems during design verification. • It has also been used as a powerful logic-analysis engine for applications such as logic optimization, timing analysis, and design-property checking.
- 3. ATPG for Delay Faults and Noise Faults • The move toward nanometer technology is introducing new failure modes and a new set of design and test problems. • Device features continue to shrink as the number of interconnect layers and gate density increases. • The result is increased current density and a higher voltage drop along the power nets as well as increased signal interference from coupling capacitance. All this gives rise to noise-induced failures, such as power supply noise or crosstalk. • These faults may cause logic errors or excessive propagation delays which degrade circuit performance
- 4. • Demands for higher circuit operating frequencies, lower cost, and higher quality mean that testing must ascertain that the circuit’s timing is correct • Timing defects can stay undetected after logic-fault testing such as testing of stuck-at faults, but they can be detected using delay tests. • Unlike ATPG for stuck-at faults, ATPG for delay faults is closely tied to the test application strategy. • Before tests for delay faults are derived, the test application strategy has to be decided. The strategy depends on the circuit type as well as on the test equipment’s speed.
- 5. • However, because high-speed testers require huge investments, most testers could be slower than the designs being tested. • Testing high-speed designs on slower testers requires special test application and test-generation strategies. • Noise faults must be detected during both design verification and manufacturing testing. • An efficient ATPG method must be able to generate validation vectors that can exercise worst-case design corners. To do this, it must integrate accurate timing information when the test vectors are derived.
- 6. • Tests for conventional fault models, such as stuck-at and transition faults, obviously cannot detect these conditions. • To check worst-case design corners, test vectors must sensitize the faults and propagate their effects to the primary outputs, as well as activate the conditions of worst-case noise effects. Power supply noise • For a highly integrated system-on-a-chip, more devices are switching simultaneously, which increases power supply noise. • One component of this noise, inductive noise, results from sudden current changes on either the package lead or wire/substrate inductance.
- 7. • The other component, net IR voltage drop, is caused by current flowing through the resistive power and ground lines. • The noise can cause a voltage glitch on these lines, resulting in timing or logic errors. • Large voltage drops through the power supply lines can cause electromigration, which in turn can cause short or open circuits. • To activate these defects and propagate them to the primary outputs, ATPG must carefully select test vectors. • Power supply noise can affect both reliability and performance. It reduces the actual voltage level that reaches a device, which in turn can increase cell and interconnection propagation delays.
- 8. • One way to detect these effects is to apply delay tests. • Unfortunately, most existing delay techniques are based on simplified, logic-level models that cannot be directly used to model, and test timing defects in high-speed designs that use deep sub-micron technologies. • The tests must produce the worst-case power supply noise along the sensitized paths, and thus cause the worst-case propagation delays on these paths.
- 9. Crosstalk effects • The increased design density in deep-submicron designs leads to more significant interference between the signals because of capacitive coupling, or crosstalk. • Crosstalk can induce both Boolean errors and delay faults. Therefore, ATPG for worst-case crosstalk effects must produce vectors that can create and propagate crosstalk pulses as well as crosstalk-induced delays. • Crosstalk-induced pulses are likely to cause errors on hazard-sensitive lines such as inputs to dynamic gates, clock, set/reset, and data inputs to flip- flops. • Crosstalk pulses can result in logicerrors or degraded voltage levels,which increase propagation delays.
- 10. • ATPG for worst-case crosstalk pulse aims to generate a pulse of maximum amplitude and width at the fault site and propagate its effects to primary outputs with minimal attenuation. • Increased coupling effects between signals can cause signal delay to increase (slowdown) or decrease (speedup) significantly. Both conditions can cause errors. • Signal speedup can cause race conditions if transitions are propagated along short paths. • To guarantee design performance, ATPG techniques must consider how worst-case crosstalk affects propagation delays
- 11. Design Applications • ATPG technology has been applied successfully in several areas of IC design automation, including logic optimization, logic equivalence checking, design property checking, and timing analysis. Logic Optimization • To optimize logic, design aids can either remove redundancy or restructure the logic by adding and removing redundancy. Redundancy Removal • Redundancy is the main link between test and logic optimization. If there are untestable stuck-at faults, there is likely to be redundant logic.
- 12. • The reasoning is that, if a stuck-at fault does not have any test the output responses of the faulty circuit will be identical to the responses of the fault- free circuit for all possible input patterns applied to these two circuits. • Thus, the faulty circuit is indeed a valid implementation of the fault-free circuit. • Therefore, when ATPG identifies a stuckat- 1 (stuck-at-0) fault as untestable, one can simplify the circuit by setting the faulty net to logic. 1(0) and thus effectively removing the faulty net from the circuit. • This operation, called redundancy removal, also removes all the logic driving the faulty net.
- 13. Logic Restructuring • Removing a redundant fault can change the status of other faults. Those that were redundant might no longer be redundant, and vice versa. • Although these changes complicate redundancy removal, they also pave the way for more rigorous optimization methods. • Even for a circuit with no redundancies, designers can add redundancies to create new redundancies elsewhere in the circuit. • By removing the created new redundancies, they may obtain an optimized circuit. This technique is called logic restructuring.
- 14. • Efficient algorithms for finding effective logic restructuring have been proposed in the past few years. • By properly orienting the search for redundancy, these techniques can be adapted to target several optimizing goals. Design Verification • Techniques used to verify designs include checking logic equivalence and determining that a circuit does or does not violate certain properties. • Logic Equivalence Checking • It is important to check the equivalence of two designs described at the same or different levels of abstraction.
- 15. • Checking the functional equivalence of the optimized implementation against the RTL specification, for example, guarantees that no error is introduced during logic synthesis and optimization, especially if part of the process is manual. • Checking the equivalence of the gate-level implementation and the gate- level model extracted from the layout assures that no error is made during physical design. • Two circuits are equivalent if and only if their canonical representations are isomorphic. • Commercial equivalence checking tools can now handle circuit modules of more than a million gates within tens of CPU minutes
- 16. Property Checking • An ATPG engine can find an example for proving that the circuit violates certain properties or, after exhausting the search space, can prove that no such example exists and thus that the circuit meets certain properties • ATPG can also identify races, which occur when data travels through two levels of latches in one clock cycle. Finally, an ATPG engine can check for effects (memory effect or an oscillation) from asynchronous feedback loops that might be in a pure synchronous circuit Timing Verification and Analysis • Test vectors that sensitize selected long paths are often used in simulations to verify circuit timing.