![“ MUL r0,r1,r2 // r0=r1*r2
CONDITIONS:
NO IMMEDIATE VALUE
2 SOURCE OPERANDS
MUST BE INDIFFERENT
MUL r0,r1,r2 // r0=r1*r2 [31:0]
32X32 =64bits 9
MUL{<cond>}{S} Rd,Rm,Rs](https://image.slidesharecdn.com/arminstsetpart2-200802171638/85/ARM-inst-set-part-2-9-320.jpg)
![“ MLA r1,r2,r3,r4
// r1=(r2*r3+r4) [31:0]
For eg: 1x2x3x4x5
1x2=2 ;2x3=6; 6x4=24;
24x5=100
10
MLA{<cond>}{S} Rd,Rm,Rs,Rn](https://image.slidesharecdn.com/arminstsetpart2-200802171638/85/ARM-inst-set-part-2-10-320.jpg)
![LDR r0, [r1] //r1 contains address 0x100, the
content of 0x100 is loaded into r0
r0= mem[r1]
26
STORE
STR r0, [r1] //store the content of r0 in memory
location whose address is given in r1 mem[r1] = r0
WITH OFFSET ADDRESS
LOAD
LDR r0, [r1, #4] // r0= mem[r1+4]
STR r0, [r1, #12] // mem[r1+12] =r0](https://image.slidesharecdn.com/arminstsetpart2-200802171638/85/ARM-inst-set-part-2-26-320.jpg)
![2 WAY OF ADDRESSING
AUTO INDEXING
LDR r0, [r1, #4] ! // r0=mem [r1+4] , then r1=r1+4 always
STR r0, [r1, #12] ! // mem [r1+12] = r0 , r1=r1+12
27
POST INDEXING
LDR r0 ,[r1], #4
1. LOAD THE VALUE r0=mem [r1]
2. Increase the r1 by offset value =r1+4 always
STR r0 [r1], #12 // mem [r1] = r0 , r1=r1+12](https://image.slidesharecdn.com/arminstsetpart2-200802171638/85/ARM-inst-set-part-2-27-320.jpg)
ARM inst set part 2
- 1. ARM INSTRUCTION SET PART 2 1 mr.C.KARTHIKEYAN AP/ECE/RMKCET
- 3. ASSEMBLY CODE ARM FEATURES 2 ENDIANS VARIOUS INSTRUCTIONS: DATA TRANSFER LOGICAL MOV, SHIFT,CMP, L/S , 3 EXAMPLES 3 REVIEW
- 4. TYPES OF INSTRUCTIONS PNEMONICS INSTRUCTION FORMAT 4 AGENDA
- 6. ARM DATA PROCESSING INSTRUCTION FORMAT 6
- 8. “ ADD r0,r1,r2 // r0=r1+r2 ADC r0,r1,r2 // r0=r1+r2+C SUB r0,r1,r2 // r0=r1-r2 SUBC r0,r1,r2 // r0=r1-r2+C-1 RSB r0,r1,r2 // r0=r2-r1 RSBC r0,r1,r2 // r0=r2-r1+C-1 NOTE: CAN PERFORM OP. IN SAME REG ADD r1,r1,r2 // r1=r1+r2 ADD r0,r2,r2 // r0=r2+r2 8
- 9. “ MUL r0,r1,r2 // r0=r1*r2 CONDITIONS: NO IMMEDIATE VALUE 2 SOURCE OPERANDS MUST BE INDIFFERENT MUL r0,r1,r2 // r0=r1*r2 [31:0] 32X32 =64bits 9 MUL{<cond>}{S} Rd,Rm,Rs
- 10. “ MLA r1,r2,r3,r4 // r1=(r2*r3+r4) [31:0] For eg: 1x2x3x4x5 1x2=2 ;2x3=6; 6x4=24; 24x5=100 10 MLA{<cond>}{S} Rd,Rm,Rs,Rn
- 11. “ MULL multiply long UMULL Unsigned multiply long UMLAL Unsigned multiply- accumulate long SMULL Signed multiply long SMLAL Signed multiply- accumulate long 11
- 13. “ CONSTANT / LITERALS (#) ADD r0,r1,#7 // r0=r1+7 ADDC r0,r1,#6 // r0=r1+6 SUB r0,r1,#5 // r0=r1-5 13
- 15. “ MOV r0,r2 // r0=r2 MOVN r0,r1 // r0=NOT r2 NOTE: REG TO REG 2 OPERANDS 1 S , 1D 15
- 17. “ AND r0,r1,r2 //r0=r1 AND r2 ORR r0,r1,r2 //r0=r1 OR r2 EOR r0,r1,r2 //r0=r1 XOR r2 BIC r0,r1,r2 //r0= r1 AND (NOT r2) 17
- 18. “ AND + MVN=NAND OR+MVN=NOR EOR+MVN=ENOR STEPS: PERFORM LOGICAL OPERATION STORE IN A REG NEGATE THE VALUE INSIDE THE REG STORE THE RESULT IN ANOTHER REG 18
- 19. SHIFT INSTRUCTION *FLEXIBILITY IN 2nd OPERAND, BARREL SHIFTER IS USED 5
- 20. “ Logical shift: fills with zeroes. LSL : fill LSB with 0 LSR : fill MSB with 0 ADD r1,r2,r3, LSL #3 // r1=r2+(r3<<3) ADD r1,r2,r3, LSR #3 // r1=r2+(r3>>3) ADD r1,r2,r3, LSR r4 // r1=r2+(r3>>r4) Arithmetic shift: fills with ones. ASL : fill LSB with 1 ASR : fill MSB with 1 20
- 21. COMPARE INSTRUCTION *THE RESULT IS NOT STORED IN SOME REG LIKE OTHER INST 6
- 22. “ 22 When ALU solves as per the inst , the flag reg always keep track , whether the result is NZCV . JUST COMPARE THE ALU RESULT WITH THE FLAG REG FOR FUTURE USE CMP r1,r2 // r1-r2 CMN r1,r2 // r1+r2 TST r1,r2 // r1 AND r2 TEQ r1,r2 // r1 EOR r2
- 24. LOAD / STORE INSTRUCTION 7
- 25. INITIALIZE SOME REGISTER FOR THE ADDRESS LOCATION 25
- 26. LDR r0, [r1] //r1 contains address 0x100, the content of 0x100 is loaded into r0 r0= mem[r1] 26 STORE STR r0, [r1] //store the content of r0 in memory location whose address is given in r1 mem[r1] = r0 WITH OFFSET ADDRESS LOAD LDR r0, [r1, #4] // r0= mem[r1+4] STR r0, [r1, #12] // mem[r1+12] =r0
- 27. 2 WAY OF ADDRESSING AUTO INDEXING LDR r0, [r1, #4] ! // r0=mem [r1+4] , then r1=r1+4 always STR r0, [r1, #12] ! // mem [r1+12] = r0 , r1=r1+12 27 POST INDEXING LDR r0 ,[r1], #4 1. LOAD THE VALUE r0=mem [r1] 2. Increase the r1 by offset value =r1+4 always STR r0 [r1], #12 // mem [r1] = r0 , r1=r1+12
- 31. INSTRUCTION FORMAT OF B & BL 31
- 32. CONTROL FLOW INSTRUCTIONS UNCONDITIONAL BRANCH: B TARGET ---------- ----------- ---------- --------- TARGET CONDITIONAL BRANCH: (LOOP) TRANSFER OF CONTROL DEPENDS UPON CERTAIN CONDITIONS 32
- 33. SYNTAX MUL{<cond>} {S} Rd,Rm,Rs MLA{<cond>} {S} Rd,Rm,Rs,Rn <Operation>{<cond>} {S} Rd, Rn, Operand2 LDR{<size>} {<cond>} Rd, <address> STR{<size>} {<cond>} Rd, <address> 33
- 34. CALL TO call a subroutine: PC points the location Element is pushed in stack Jump to subroutine Subroutine gets executed The last inst of subroutine will be the RETURN value SUBROUTINE CALL IN CONVENTIONAL PROCESSOR RETURN POP retrieve the last element from stack It will loaded into PC Which meants return back to prog from where the call inst was executed (next inst) 34
- 35. CALL There is NO call instruction BRANCH AND LINK (BL) R14 Link reg Return address –current value of PC Saved in LR IN ARM PROCESSOR (BL) After subroutine executed it has to jump back to the address stored in r14 35
- 36. 36 SUMMARIZE 1. INTERNAL MECH BET CPU AND MEMORY 2. COMMON INT FORMAT 3. DATA PROCESSING INST 4. ARITMETIC 5. IMMEDIATE 6. MOV 7. LOGICAL 8. SHIFT 9. COMPARE 10. DATA TRANSFER 11. LOAD / STORE 12. 2 MODES 13. CONTROL INST WITH UNCOD & COND 14. SYNTAX 15. SUBROUTINE