![11/70
ARM7 - Block Diagram
Address Register
Address
Incrementer
P
C
B
u
s
Register Bank
(31 x 32 bit registers)
(6 status registers)
Booth's
Multiplier
Barrel Shifter
32 bit ALU
Write Data Register Instruction Pipeline & Read
Data Register
Instruction
Decoder &
Control Logic
B
b
u
s
I
n
c
r
e
m
e
n
t
e
r
B
u
s
A
L
U
B
u
s
A
b
u
s
DOUT[31:0] DATA[31:0]
nEXEC
DATA32
BIGEND
PROG32
MCLK
nWAIT
nRW
nBW
nIRQ
nFIQ
nRESET
ABORT
nOPC
nTRANS
nMREQ
SEQ
LOCK
nCPI
CPA
CPB
nM[4:0]
ALE
A[31:0]](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-11-320.jpg)
![12/70
ARM7 - Functional Diagram
nEXEC
DATA32
BIGEND
PROG32
MCLK
nWAIT
nRW
nBW
nIRQ
nFIQ
nRESET
ABORT
nOPC
nTRANS
nMREQ
SEQ
LOCK
nCPI
CPA
CPB
nM[4:0]
ALE
DBE
VDD
VSS
A[31:0]
DATA[31:0]
DOUT[31:0]
nENOUT
ARM7
Processor
Mode
Memory
Interface
Memory
Management
Interface
Coprocessor
Interface
Power
Bus Controls
Interrupts
Configuration
Clocks](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-12-320.jpg)
![13/70
ARM7 - Signal Description
Clocks
– MCLK Memory Clock Input
– nWAIT Not wait
Configuration
– PROG32 32 bit program
configuration
– DATA32 32 bit data configuration
– BIGEND Big Endian configuration
Interrupts
– nIRQ Not interrupt request
– nFIQ Not fast interrupt request
Bus Controls
– ALE Address latch enable
– DBE Data bus enable
Power
– VDD Power supply
– VSS Ground
Processor Mode
– nM[4:0] Not processor mode](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-13-320.jpg)
![14/70
ARM7 - Signal Description
Memory Interface
– A[31:0] Addresses
– DATA[31:0] Data bus in
– DOUT[31:0] Data bus out
– nENOUT Not enable data
outputs
– nMREQ Not memory request
– SEQ Sequential address
– nRW Not read/write
– nBW Not byte/word
– LOCK Locked operation
Memory Management Interface
– nTRANS Not memory translate
– ABORT Memory abort
Coprocessor Interface
– nOPC Not op-code fetch
– nCPI Not coprocessor
instruction
– CPA Coprocessor absent
– CPB Coprocessor busy
Other
– nEXEC ******************
– nRESET Not reset](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-14-320.jpg)
![26/70
ARM7 - Registers
M[4:0] Mode Accessible register set
10000 User PC R14..R0 CPSR
10001 FIQ PC R14_fiq..R8_fiq, R7..R0 CPSR, SPSR_fiq
10010 IRQ PC R14_irq..R13_irq, R12..R0 CPSR, SPSR_irq
10011 Supervisor PC R14_svc..R13_svc, R12..R0 CPSR, SPSR_svc
10111 Abort PC R14_abt..R13_abt, R12..R0 SPSR_abt
11011 Undefined PC R14_und..R13_und, R12..R0 SPSR_und
The Mode Bits](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-26-320.jpg)
![45/70
ARM7 - Memory Interface
32 bit bidirectional data bus D[31:0]
32 bit address bus
The nRW signal gives the direction of transfer
Control signals give additional information about the transfer
cycle
DRAM page mode](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-45-320.jpg)
![48/70
ARM7 - Memory Interface
When an S-cycle follows
an N-cycle, the address
will always be one word
greater than the address
used in the N-cycle
This address should be
checked to ensure that it
is not the last in the
DRAM page before the
memory system commits
to the S-cycle
ARM Memory Cycle Timing
N-cycle S-cycle I-cycle C-cycle
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
MCLK
a a+4 a+8](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-48-320.jpg)
![49/70
ARM7 - Memory Interface
When an S-cycle follows an I-
or C-cycle, the address will
be the same as that used in
the I- or C-cycle
This be used to start the
DRAM access during the
preceding cycle, which
enables the S-cycle to run at
page mode speed whilst
performing a full DRAM
access
Memory Cycle Optimization
I-cycle S-cycle
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
MCLK](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-49-320.jpg)
![50/70
ARM7 - Memory Interface
The processor address bus gives byte addresses,
Instructions are always words (4 bytes)
The nBW control line is used to request a byte from the memory
system
– normally it is HIGH, signifying a request for a word quantity
– it goes LOW during phase 2 of the preceding cycle to request a byte
transfer
When the processor is fetching an instruction from memory, the
state of the bottom two address lines A[1:0] is undefined
ARM7 will perform the byte extraction internally. Alternatively, the
memory system may activate only the addressed byte of the
memory
Byte Addressing](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-50-320.jpg)
![51/70
ARM7 - Memory Interface
One way of implementing the byte decode in a DRAM system is to
separate the 32 bit wide block of DRAM into four byte wide banks,
and generate the column address strobes independently
Decoding Byte Access to Memory
NCAS0
NCAS1
NCAS2
NCAS3
A[0] A[1] nBW MCLK CAS
D Q
Quad
Latch](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-51-320.jpg)
![52/70
ARM7 - Memory Interface
Little Endian
– operation byte 0 of the memory system should be connected to data
lines 7 through 0 (D[7:0]) and strobed by nCAS0
– nCAS1 drives the bank connected to data lines 15 though 8
Big Endian
– byte 0 of the memory system should be connected to data lines 31
through 24](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-52-320.jpg)
![54/70
ARM7 - Memory Interface
The ARM7 address bus may be processed by an address
translation unit before being presented to the memory
ARM7 is capable of running a virtual memory system
Various signals enable different page protection levels to be
supported:
– nRW can be used by the memory manager to protect pages from being
written to
– nTRANS indicates whether the processor is in user or a privileged
mode, and may be used to protect system pages from the user, or to
support completely separate mappings for the system and the user
– nM[4:0] can give the memory manager full information on the
processor mode.
Memory Management](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-54-320.jpg)
![69/70
ARM7 - AC Parameters
Output
Signal
Test Load
(pF)
Output Derating
(ns/pF)
D[31:0] 5 0.5
A[31:0] 5 0.5
LOCK 2 0.5
nCPI 2 0.5
nMREQ 2 0.5
SEQ 2 0.5
nRW 2 0.5
nBW 2 0.5
nOPC 2 0.5
nTRANS 2 0.5
AC Test Loads](https://image.slidesharecdn.com/arm3-230111135527-35271cee/85/arm_3-ppt-69-320.jpg)
arm_3.ppt
- 1. ARM Authors: Goran Timotic [email protected] Gvozden Marinkovic [email protected] Prof. Dr. Veljko Milutinovic [email protected] University of Belgrade School of Electrical Engineering Department of Computer Science
- 2. 2/70 ARM - Introduction Advances RISC Machines (now known as ARM) was established as a joint venture between Acorn, Apple and VLSI between Acorn, Apple and VLSI in November 1990 ARM is the industry's leading provider of 16/32-bit embedded RISC microprocessor solutions The company licenses its high-performance, low-cost, power- efficient RISC processors, peripherals, and system-chip designs to leading international electronics companies ARM provides comprehensive support required in developing a complete system
- 3. 3/70 ARM - Introduction Arm 1 – This was the very first ARM processor and was superseded by the ARM2 fairly quickly Arm 2 – The ARM2 chip, and processor cell, features 27 registers of which 16 are accessible at any one time. Four processor modes are available: • USR : user mode • IRQ : interrupt mode (with a private copy of R13 and R14) • FIQ : fast interrupt mode (private copies of R8 to R14) • SVC : supervisor mode. (private copies of R13 and R14) Currently available processors:
- 4. 4/70 ARM - Introduction Arm 3 – This is an upgraded ARM2 cell, with a cache and dedicated coprocessor interface added Arm 6 – This processor cell is the first of the commercially available ARMs to have a full 32bit addressing capability – Additionally the processor now has 31 registers in it along with six new processor modes: • User32 - 32 bit USR mode • Supervisor32 - 32 bit SVC mode (private SPSR register) • IRQ32 - 32 bit IRQ mode (private SPSR register) • FIQ32 - 32 bit FIQ mode. (private SPSR register) • Abort32 - Memory fetch abort mode (private SPSR register) • Undefined32 Undefined instruction mode (private SPSR register)
- 5. 5/70 ARM - Introduction Thumb – This isn't a processor per se, but more a 16 bit compressed instruction set that is decoded by the Thumb core into full 32 bit instructions that are then fed to an ARM core for execution – This offers two important advantages for the embedded processor market: • Increased code density • Simplified system design The trade-off includes that the Thumb instruction set loses the conditional instruction execution and can only address the first eight registers of the processor
- 6. 6/70 ARM - Introduction Arm 7 – The ARM7 cell is functionally identical to the ARM6 cell in capabilities but may be clocked faster than the ARM6 – A variant of the ARM7 cell offers an improved hardware multiply, suitable for DSP work Arm 8 – Includes a five stage pipeline, a speculative instruction fetcher and internal tweaks to the processor to allow a higher clock speed StrongARM – This is the high speed variant of the ARM chip family – Architecturally it is similar to the ARM8 core, sharing the five stage pipeline with that processor – A further difference is change from a unified data and instruction cache to a split, Harvard architecture, instruction and data cache
- 7. 7/70 ARM - Introduction ARM9 – An incremental improvement over the ARM8 this chip features the same five stage pipeline but is now a Harvard Architecture chip, like the StrongARM ARM 10 – 300 MHz – 400 MIPS – 600 mWatts
- 9. 9/70 ARM7 - Features 32-bit RISC processor (32-bit data & address bus) Big and Little Endian operating modes High performance RISC (17 MIPS sustained @ 25 MHz (25 MIPS peak) @ 3V) Low power consumption (0.6mA/MHz @ 3V fabricated in .8µm CMOS) Fully static operation (ideal for power-sensitive applications) Fast interrupt response (for real-time applications) Virtual Memory System Support Excellent high-level language support Simple but powerful instruction set
- 10. 10/70 ARM7 - Applications The ARM7 is ideally suited to those applications requiring RISC performance from a compact, power-efficient processor – Telecomms - GSM terminal controller – Datacomms - Protocol conversion – Portable Computing - Palmtop computer – Portable Instrument - Hendheld data acquisition unit – Automotive - Engine management unit – Information systems - Smart cards – Imaging - JPEG controller
- 11. 11/70 ARM7 - Block Diagram Address Register Address Incrementer P C B u s Register Bank (31 x 32 bit registers) (6 status registers) Booth's Multiplier Barrel Shifter 32 bit ALU Write Data Register Instruction Pipeline & Read Data Register Instruction Decoder & Control Logic B b u s I n c r e m e n t e r B u s A L U B u s A b u s DOUT[31:0] DATA[31:0] nEXEC DATA32 BIGEND PROG32 MCLK nWAIT nRW nBW nIRQ nFIQ nRESET ABORT nOPC nTRANS nMREQ SEQ LOCK nCPI CPA CPB nM[4:0] ALE A[31:0]
- 12. 12/70 ARM7 - Functional Diagram nEXEC DATA32 BIGEND PROG32 MCLK nWAIT nRW nBW nIRQ nFIQ nRESET ABORT nOPC nTRANS nMREQ SEQ LOCK nCPI CPA CPB nM[4:0] ALE DBE VDD VSS A[31:0] DATA[31:0] DOUT[31:0] nENOUT ARM7 Processor Mode Memory Interface Memory Management Interface Coprocessor Interface Power Bus Controls Interrupts Configuration Clocks
- 13. 13/70 ARM7 - Signal Description Clocks – MCLK Memory Clock Input – nWAIT Not wait Configuration – PROG32 32 bit program configuration – DATA32 32 bit data configuration – BIGEND Big Endian configuration Interrupts – nIRQ Not interrupt request – nFIQ Not fast interrupt request Bus Controls – ALE Address latch enable – DBE Data bus enable Power – VDD Power supply – VSS Ground Processor Mode – nM[4:0] Not processor mode
- 14. 14/70 ARM7 - Signal Description Memory Interface – A[31:0] Addresses – DATA[31:0] Data bus in – DOUT[31:0] Data bus out – nENOUT Not enable data outputs – nMREQ Not memory request – SEQ Sequential address – nRW Not read/write – nBW Not byte/word – LOCK Locked operation Memory Management Interface – nTRANS Not memory translate – ABORT Memory abort Coprocessor Interface – nOPC Not op-code fetch – nCPI Not coprocessor instruction – CPA Coprocessor absent – CPB Coprocessor busy Other – nEXEC ****************** – nRESET Not reset
- 15. 15/70 ARM7 - Programmer’s Model ARM7 supports a variety of operating configurations – hardware configurations (controlled by inputs) – operating modes (controlled by software)
- 16. 16/70 ARM7 - Hardware Configuration Signals 3 hardware configuration signals – Big Endian – Little Endian – Configuration Bits for Backward Compatibility Hardware configuration signals may be changed while the processor is running
- 17. 17/70 ARM7 - Hardware Configuration Signals Most significant byte is at lowest address Word is addressed by byte address of most significant byte Big Endian 31 24 23 16 15 8 7 0 Word Address 11 10 9 8 8 7 6 5 4 4 3 2 1 0 0 Lower Address Higher Address
- 18. 18/70 ARM7 - Hardware Configuration Signals Least significant byte is at lowest address Word is addressed by byte address of least significant byte Little Endian 31 24 23 16 15 8 7 0 Word Address 8 9 10 11 8 4 5 6 7 4 0 1 2 3 0 Higher Address Lower Address
- 19. 19/70 ARM7 - Hardware Configuration Signals PROG32 and DATA32 are used for backward compatibility with earlier ARM processors (default value is 1) Provides support for running existing 26 bit programs in the 32 bit environment This mode is recommended for compatibility with future ARM processors Configuration Bits for Backward Compatibility
- 20. 20/70 ARM7 - Operating Modes User mode (usr): the normal program execution state FIQ mode (fiq): designed to support a data transfer or channel process IRQ mode (irq): used for general purpose interrupt handling Supervisor mode (svc): a protected mode for the operating system Abort mode (abt): entered after a data or instruction prefetch abort Undefined mode (und): entered when an undefined instruction is executed
- 21. 21/70 ARM7 - Registers 37 registers – 31 general 32 bit registers – 6 status registers 16 general registers and one or two status registers are visible at any time The visible registers depend on the processor mode The other registers (the banked registers) are switched in to support IRQ, FIQ, Supervisor, Abort and Undefined mode processing
- 22. 22/70 ARM7 - Registers R0 to R15 are directly accessible – R0 to R14 are general purpose – R15 holds the Program Counter (PC) CPSR - Current Program Status Register contains condition code flags and the current mode bits 5 SPSRs (Saved Program Status Registers) which are loaded with CPSR when an exceptions occurs
- 23. 23/70 ARM7 - Registers General Registers and Program Counter Modes Program Status Registers User32 Fiq32 Supervisor32 Abort32 IRQ32 Undefined32 R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8_fiq R8 R8 R8 R8 R9 R9_fiq R9 R9 R9 R9 R10 R10_fiq R10 R10 R10 R10 R11 R11_fiq R11 R11 R11 R11 R12 R12_fiq R12 R12 R12 R12 R13 R13_fiq R13_svc R13_abt R13_irq R13_und R14 R14_fiq R14_svc R14_abt R14_irq R14_und R15(PC) R15(PC) R15(PC) R15(PC) R15(PC) R15(PC) CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
- 24. 24/70 ARM7 - Registers R14 is used as the subroutine link register and receives a copy of R15 when a Branch and Link instruction is executed R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are used to – hold the return values of R15 when interrupts and exceptions arise, – when Branch and Link instructions are executed within interrupt or exception routines FIQ mode has seven banked registers mapped to R8-14 (R8_fiq- R14_fiq) User mode, IRQ mode, Supervisor mode, Abort mode and Undefined mode each have two banked registers mapped to R13 and R14 The two banked registers allow these modes to each have a private stack pointer and link register
- 25. 25/70 ARM7 - Registers The N, Z, C and V are condition code flags – may be changed as a result of arithmetic and logical operations in the processor – may be tested by all instructions to determine if the instruction is to be executed The I and F bits are the interrupt disable bits The M0, M1, M2, M3 and M4 bits are the mode bits 0 1 2 4 3 5 6 7 8 27 28 31 30 29 M4 M3 M2 M1 M0 I F N Z C V Overflow Carry/Borrow/Extend Zero Negative/Less Than Mode Bits FIQ disable IRQ disable
- 26. 26/70 ARM7 - Registers M[4:0] Mode Accessible register set 10000 User PC R14..R0 CPSR 10001 FIQ PC R14_fiq..R8_fiq, R7..R0 CPSR, SPSR_fiq 10010 IRQ PC R14_irq..R13_irq, R12..R0 CPSR, SPSR_irq 10011 Supervisor PC R14_svc..R13_svc, R12..R0 CPSR, SPSR_svc 10111 Abort PC R14_abt..R13_abt, R12..R0 SPSR_abt 11011 Undefined PC R14_und..R13_und, R12..R0 SPSR_und The Mode Bits
- 27. 27/70 ARM7 - Exceptions Exceptions arise whenever there is a need for the normal flow of program execution to be broken, so that the processor can be diverted to handle an interrupt from a peripheral Many exceptions may arise at the same time When multiple exceptions arise simultaneously, a fixed priority determines the order in which they are handled ARM7 handles exceptions by making use of the banked registers to save state
- 28. 28/70 ARM7 - Exceptions FIQ (Fast Interrupt reQuest) – The FIQ exception is externally generated by taking the nFIQ input LOW. – This input can accept asynchronous transitions, and is delayed by one clock cycle for synchronisation before it can affect the processor execution flow IRQ (Interrupt ReQuest) – The IRQ exception is a normal interrupt caused by a LOW level on the nIRQ input ABORT – An ABORT can be signalled by the external ABORT input – ABORT indicates that the current memory access cannot be completed Types of Exceptions
- 29. 29/70 ARM7 - Exceptions Types of Exceptions Software interrupt – The software interrupt instruction (SWI) is used for getting into Supervisor mode, usually to request a particular supervisor function Undefined instruction trap – When the ARM7 comes across an instruction which it cannot handle it offers it to any coprocessors which may be present – If a coprocessor can perform this instruction but is busy at that time, ARM7 will wait until the coprocessor is ready or until an interrupt occurs – If no coprocessor can handle the instruction then ARM7 will take the undefined instruction trap
- 30. 30/70 ARM7 - Exceptions (1) Reset (highest priority) (2) Data abort (3) FIQ (4) IRQ (5) Prefetch abort (6) Undefined Instruction, Software interrupt (lowest priority) Exception Priorities
- 31. 31/70 ARM7 - Reset When the nRESET signal goes LOW, ARM7 abandons the executing instruction and then continues to fetch instructions from incrementing word addresses
- 32. 32/70 ARM7 - Instruction Set Cond 0 0 I Opcode S Rn Rd Operand 2 Cond 0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm Cond 0 0 0 1 0 B 0 0 Rn Rd 0 0 0 0 1 0 0 1 Rm Cond 0 1 I P U B W L Rn Rd Offset Cond 0 1 1 XXXXXXXXXXXXXXXXXXXX 1 xxxx Cond 1 0 0 P U S W L Rn Register list Cond 1 0 1 L offset Cond 1 1 0 P U N W L Rn CRd CP# offset Cond 1 1 1 0 CP Opc CRn CRd CP# CP 0 CRm Cond 1 1 1 0 CP Opc L CRn Rd CP# CP 1 CRm Cond 1 1 1 1 ignored by processor Data Processing PSR Transfer Multiply Single Data Swap Single Data Transfer Undefined Block Data Transfer Branch Coproc Data Transfer Coproc Data Operation Coproc Register Transfer Software Interrupt 31 28 19 15 11 7 3 0 Instruction Set Summary
- 33. 33/70 ARM7 - Instruction Set All ARM7 instructions are conditionally executed, which means that their execution may or may not take place depending on the values of the N, Z, C and V flags in the CPSR If the always (AL) condition is specified, the instruction will be executed irrespective of the flags The never (NV) class of condition codes shall not be used as they will be redefined in future variants of the ARM architecture 31 27 0 Cond The Condition Field
- 34. 34/70 ARM7 - Instruction Set Condition field – 0000 = EQ - Z set (equal) – 0001 = NE - Z clear (not equal) – 0010 = CS - C set (unsigned higher or same) – 0011 = CC - C clear (unsigned lower) – 0100 = MI - N set (negative) – 0101 = PL - N clear (positive or zero) – 0110 = VS - V set (overflow) – 0111 = VC - V clear (no overflow) – 1000 = HI - C set and Z clear (unsigned higher) – 1001 = LS - C clear or Z set (unsigned lower or same) – 1010 = GE - N set and V set, or N clear and V clear (greater or equal) – 1011 = LT - N set and V clear, or N clear and V set (less than) – 1100 = GT - Z clear, and either N set and V set, or N clear and V clear (greater than) – 1101 = LE - Z set, or N set and V clear, or N clear and V set (less than or equal) – 1110 = AL - always – 1111 = NV - never 31 27 0 Cond
- 35. 35/70 ARM7 - Instruction Set MUL - Multiply Only MLA - Multiply and Accumulate B - Branch BL - Branch with Link
- 36. 36/70 ARM7 - Instruction Set Logical Operations Data Processing Assembler Mnemonic OpCode Action AND 0000 operand1 AND operand2 EOR 0001 operand1 EOR operand2 TST 1000 as AND, but result is not written TEQ 1001 as EOR, but result is not written ORR 1100 operand1 OR operand2 MOV 1101 operand2 (operand1 is ignored) BIC 1110 operand1 AND NOT operand2 Bit clear) MVN 1111 NOT operand2 (operand1 is ignored)
- 37. 37/70 ARM7 - Instruction Set Arithmetic Operations Data Processing Assembler Mnemonic OpCode Action SUB 0010 operand1-operand2 RSB 0011 operand2-operand1 ADD 0100 operand1+operand2 ADC 0101 operand1+operand2+carry SBC 0110 operand1-operand2+carry-1 RSC 0111 operand2-operand1+carry-1 CMP 1010 as SUB, but result is not written CMN 1011 as ADD, but result is not written
- 38. 38/70 ARM7 - Instruction Set The MRS and MSR instructions are formed from a subset of the Data Processing operations They are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set These instructions allow access to the CPSR and SPSR registers: – The MRS instruction allows the contents of the CPSR or SPSR_<mode> to be moved to a general register – The MSR instruction allows the contents of a general register to be moved to the CPSR or SPSR_<mode> register PSR Transfer (MRS, MSR)
- 39. 39/70 ARM7 - Instruction Set The single data transfer instructions are used to load or store single bytes or words of data The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register Single data transfer (LDR, STR)
- 40. 40/70 ARM7 - Instruction Set Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers They support all possible stacking modes, maintaining full or empty stacks which can grow up or down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks of data around main memory Block data transfer (LDM, STM)
- 41. 41/70 ARM7 - Instruction Set The data swap instruction is used to swap a byte or word quantity between a register and external memory This instruction is implemented as a memory read followed by a memory write which are “locked” together (the processor cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as inseparable) Single data swap (SWP)
- 42. 42/70 ARM7 - Instruction Set The software interrupt instruction is used to enter Supervisor mode in a controlled manner The instruction causes the software interrupt trap to be taken, which effects the mode change Software interrupt (SWI)
- 43. 43/70 ARM7 - Instruction Set This class of instruction is used to tell a coprocessor to perform some internal operation No result is communicated back to ARM7, and it will not wait for the operation to complete Coprocessor data operations (CDP) Coprocessor data transfers (LDC, STC) This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessors’s registers directly to memory ARM7 is responsible for supplying the memory address, and the coprocessor supplies or accepts the data and controls the number of words transferred
- 44. 44/70 ARM7 - Instruction Set This class of instruction is used to communicate information directly between ARM7 and a coprocessor Coprocessor register transfers (MRC, MCR) Undefined instruction If the condition is true, the undefined instruction trap will be taken
- 45. 45/70 ARM7 - Memory Interface 32 bit bidirectional data bus D[31:0] 32 bit address bus The nRW signal gives the direction of transfer Control signals give additional information about the transfer cycle DRAM page mode
- 46. 46/70 ARM7 - Memory Interface Four categories of transfer cycles – Non-sequential cycle • ARM7 requests a transfer to or from an address which is unrelated to the address used in the preceding cycle – Sequential cycle • ARM7 requests a transfer to or from an address which is either the same as the address in the preceding cycle, or is one word after the preceding address – Internal cycle • ARM7 does not require a transfer, as it is performing an internal function and no useful prefetching can be performed at the same time – Coprocessor register transfer • ARM7 wishes to use the data bus to communicate with a coprocessor, but does not require any action by the memory system
- 47. 47/70 ARM7 - Memory Interface nMREQ and SEQ lines define cycle type These control lines are generated during phase 1 of the cycle before the cycle whose characteristics they forecast This pipelining of the control information gives the memory system sufficient time to decide whether or not it can use a page mode access nMREQ SEQ Cycle type 0 0 Non-sequential cycle (N-cycle) 0 1 Sequential cycle (S-cycle) 1 0 Internal cycle (I-cycle) 1 1 Coprocessor register transfer (C-cycle)
- 48. 48/70 ARM7 - Memory Interface When an S-cycle follows an N-cycle, the address will always be one word greater than the address used in the N-cycle This address should be checked to ensure that it is not the last in the DRAM page before the memory system commits to the S-cycle ARM Memory Cycle Timing N-cycle S-cycle I-cycle C-cycle A[31:0] nMREQ SEQ nRAS nCAS D[31:0] MCLK a a+4 a+8
- 49. 49/70 ARM7 - Memory Interface When an S-cycle follows an I- or C-cycle, the address will be the same as that used in the I- or C-cycle This be used to start the DRAM access during the preceding cycle, which enables the S-cycle to run at page mode speed whilst performing a full DRAM access Memory Cycle Optimization I-cycle S-cycle A[31:0] nMREQ SEQ nRAS nCAS D[31:0] MCLK
- 50. 50/70 ARM7 - Memory Interface The processor address bus gives byte addresses, Instructions are always words (4 bytes) The nBW control line is used to request a byte from the memory system – normally it is HIGH, signifying a request for a word quantity – it goes LOW during phase 2 of the preceding cycle to request a byte transfer When the processor is fetching an instruction from memory, the state of the bottom two address lines A[1:0] is undefined ARM7 will perform the byte extraction internally. Alternatively, the memory system may activate only the addressed byte of the memory Byte Addressing
- 51. 51/70 ARM7 - Memory Interface One way of implementing the byte decode in a DRAM system is to separate the 32 bit wide block of DRAM into four byte wide banks, and generate the column address strobes independently Decoding Byte Access to Memory NCAS0 NCAS1 NCAS2 NCAS3 A[0] A[1] nBW MCLK CAS D Q Quad Latch
- 52. 52/70 ARM7 - Memory Interface Little Endian – operation byte 0 of the memory system should be connected to data lines 7 through 0 (D[7:0]) and strobed by nCAS0 – nCAS1 drives the bank connected to data lines 15 though 8 Big Endian – byte 0 of the memory system should be connected to data lines 31 through 24
- 53. 53/70 ARM7 - Memory Interface Static RAMs and ROMs require the address to be stable until after the access has completed The address transition must be delayed until after the end of phase 2 An on-chip address latch, controlled by ALE, allows the address timing to be modified in this way Address Timing
- 54. 54/70 ARM7 - Memory Interface The ARM7 address bus may be processed by an address translation unit before being presented to the memory ARM7 is capable of running a virtual memory system Various signals enable different page protection levels to be supported: – nRW can be used by the memory manager to protect pages from being written to – nTRANS indicates whether the processor is in user or a privileged mode, and may be used to protect system pages from the user, or to support completely separate mappings for the system and the user – nM[4:0] can give the memory manager full information on the processor mode. Memory Management
- 55. 55/70 ARM7 - Memory Interface ARM7 includes a data swap (SWP) instruction that allows the contents of a memory location to be swapped with the contents of a processor register This instruction is implemented as an uninterruptable pair of accesses: – the first access reads the contents of the memory – the second writes the register data to the memory These accesses must be treated as a contiguous operation by the memory controller to prevent another device from changing the affected memory location before the swap is completed ARM7 drives the LOCK signal HIGH for the duration of the swap operation to warn the memory controller not to give the memory to another device Locked Operations
- 56. 56/70 ARM7 - Memory Interface Long access times can be accommodated by stretching MCLK It is usual to stretch the LOW period of MCLK Taking nWAIT LOW has the same effect as stretching the LOW period of MCLK nWAIT must only change when MCLK is LOW There is no limit upon the maximum period for which MCLK may be stretched, or nWAIT held LOW Streching Access Times
- 57. 57/70 ARM7 - Coprocessor Interface The ARM7 instruction set may be extended by the addition of up to 16 external coprocessors Adding the coprocessor will then increase the system performance in a software compatible way When the coprocessor is not present, instructions intended for it will trap, and suitable software may be installed to emulate its functions
- 58. 58/70 ARM7 - Coprocessor Interface Three dedicated signals control the coprocessor interface: – nCPI – nCPA – nCPB The CPA and CPB inputs should be driven high except when they are being used for handshaking Interface Signals
- 59. 59/70 ARM7 - Coprocessor Interface ARM7 takes nCPI LOW whenever it starts to execute a coprocessor (or undefined) instruction Each coprocessor will have a copy of the instruction Each coprocessor can inspect the CP# field to see which coprocessor it is for Every coprocessor in a system must have a unique number If that number matches the contents of the CP# field the coprocessor should drive the CPA (coprocessor absent) line LOW If no coprocessor has a number which matches the CP# field, CPA and CPB will remain HIGH, and ARM7 will take the undefined instruction trap Coprocessor present/absent
- 60. 60/70 ARM7 - Coprocessor Interface If CPA goes LOW, ARM7 will watch the CPB (coprocessor busy) line ARM7 will busy-wait while CPB is HIGH, unless an enabled interrupt occurs, in which case it will break off from the coprocessor handshake to process the interrupt When CPB goes LOW, the instruction continues to completion Busy-waiting
- 61. 61/70 ARM7 - Coprocessor Interface In order to respond correctly when a coprocessor instruction arises, each coprocessor must have a copy of the instruction All ARM7 instructions are fetched from memory via the main data bus, and coprocessors are connected to this bus The nOPC signal indicates when an instruction fetch is taking place MCLK gives the timing of the transfer Pipeline Following
- 62. 62/70 ARM7 - Coprocessor Interface Coprocessor must supply or accept data at ARM7 bus rate (defined by MCLK) The L bit in the instruction defines direction of transfer The coprocessor is responsible for determining the number of words to be transferred ARM7 will continue to increment the address by one word per transfer until the coprocessor tells it to stop The termination condition is indicated by the coprocessor driving CPA and CPB HIGH There is no limit to the number of words which one coprocessor data transfer can move, but no coprocessor should allow more than 16 words in one instruction Data Transfer Cycles
- 63. 63/70 ARM7 - Coprocessor Interface ARM7 requires the data bus without requiring the memory to be active The memory system is informed that the bus is required by ARM7 taking both nMREQ and SEQ HIGH When the bus is free, DBE should be taken HIGH to allow ARM7 or the coprocessor to drive the bus, and an MCLK cycle times the transfer Register Transfer Cycle
- 64. 64/70 ARM7 - Coprocessor Interface The coprocessor may restrict certain instructions for use in privileged modes only Privileged Instructions
- 65. 65/70 ARM7 - Coprocessor Interface All instructions may be interrupted at any point up to the time when the coprocessor goes not-busy The instruction will normally be restarted from the beginning after the interrupt has been processed Any action taken by the coprocessor before it goes not-busy must be idempotent, ie must be repeatable with identical results Idempotency
- 66. 66/70 ARM7 - Coprocessor Interface Undefined instructions are treated by ARM7 as coprocessor instructions All coprocessors must be absent (ie CPA and CPB must be HIGH) when an undefined instruction is presented The coprocessor need only look at bit 27 of the instruction to differentiate undefined instructions (which all have 0 in bit 27) from coprocessor instructions (which all have 1 in bit 27) Undefined Instructions
- 67. 67/70 ARM7 - DC Parameters Exceeding the absolute maximum ratings may permanently damage the device. Operating the device at absolute maximum ratings for extended periods may affect device reliability Absolute Maximum Ratings Symbol Parameter Min. Max. Units VDD Supply voltage VSS-0.3 VSS+0.7 V Vin Input voltage applied to any pin VSS-0.3 VSS+0.3 V Vts Storage temperature -40 125 deg C
- 68. 68/70 ARM7 - DC Parameters DC Operating Conditions Symbol Parameter Min. Typ. Max. Units VDD Supply voltage 4.5 5.0 5.5 V Vihc Input HIGH voltage 3.5 VDD V Vilc Input LOW voltage 0.0 1.5 V Ta Ambient operating temperature 0 70 Deg C
- 69. 69/70 ARM7 - AC Parameters Output Signal Test Load (pF) Output Derating (ns/pF) D[31:0] 5 0.5 A[31:0] 5 0.5 LOCK 2 0.5 nCPI 2 0.5 nMREQ 2 0.5 SEQ 2 0.5 nRW 2 0.5 nBW 2 0.5 nOPC 2 0.5 nTRANS 2 0.5 AC Test Loads
- 70. 70/70 ARM7 - Backward Compatibility Two inputs, PROG32 and DATA32, allow one of three processor configurations to be selected as follows: – 26 bit program and data space - (PROG32 LOW, DATA32 LOW) – 26 bit program space and 32 bit data space - (PROG32 LOW, DATA32 HIGH) – 32 bit program and data space - (PROG32 HIGH, DATA32 HIGH)