Atmel

Features
• Compatible with MCS-51™ Products
• 4K Bytes of In-System Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
•
•
Programmable Serial Channel
Low-power Idle and Power-down Modes
8-bit
Microcontroller
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
with 4K Bytes
bytes of Flash programmable and erasable read only memory (PEROM). The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
Flash
compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conven-
tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash AT89C51
on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides
a highly-flexible and cost-effective solution to many embedded control applications.

PDIP Not Recommended
Pin Configurations
P1.0 1 40 VCC
for New Designs.
P1.1 2 39 P0.0 (AD0)
P1.2
P1.3
3
4
38
37
P0.1 (AD1)
P0.2 (AD2)
Use AT89S51.
P1.4 5 36 P0.3 (AD3)
P1.5 6 35 P0.4 (AD4)
P1.6 7 34 P0.5 (AD5)
P1.7 8 33 P0.6 (AD6)
RST 9 32 P0.7 (AD7)
PQFP/TQFP (RXD) P3.0 10 31 EA/VPP
(TXD) P3.1 11 30 ALE/PROG
P1.1 (T2 EX)

(INT0) P3.2 12 29 PSEN
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)

(INT1) P3.3 13 28 P2.7 (A15)
P1.0 (T2)

(T0) P3.4 14 27 P2.6 (A14)
VCC
P1.4
P1.3
P1.2

(T1) P3.5 15 26 P2.5 (A13)
NC

(WR) P3.6 16 25 P2.4 (A12)
(RD) P3.7 17 24 P2.3 (A11)
44
43
42
41
40
39
38
37
36
35
34

XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)
P1.5 1 33 PO.4 (AD4) GND 20 21 P2.0 (A8)
P1.6 2 32 P0.5 (AD5)
P1.7 3 31 P0.6 (AD6)
RST 4 30 P0.7 (AD7) PLCC
(RXD) P3.0 5 29 EA/VPP
NC 6 28 NC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)

(INT0) P3.2 8 26 PSEN
VCC
P1.4
P1.3
P1.2
P1.1
P1.0
NC

(INT1) P3.3 9 25 P2.7 (A15)
(T0) P3.4 10 24 P2.6 (A14)
6
5
4
3
2
1
44
43
42
41
40

(T1) P3.5 11 23 P2.5 (A13)
P1.5 7 39 PO.4 (AD4)
P1.6 8 38 P0.5 (AD5)
12
13
14
15
16
17
18
19
20
21
22

P1.7 9 37 P0.6 (AD6)
(WR)P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4

RST 10 36 P0.7 (AD7)
(RXD) P3.0 11 35 EA/VPP
NC 12 34 NC
(INT0) P3.2 14 32 PSEN
(INT1) P3.3 15 31 P2.7 (A15)
(T0) P3.4 16 30 P2.6 (A14)
(T1) P3.5 17 29 P2.5 (A13)
18
19
20
21
22
23
24
25
26
27
28
(WR)P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4

Rev. 0265G–02/00

1

Block Diagram
P0.0 - P0.7 P2.0 - P2.7

VCC

PORT 0 DRIVERS PORT 2 DRIVERS
GND

RAM ADDR. PORT 0 PORT 2
REGISTER RAM LATCH LATCH FLASH

PROGRAM
B STACK ADDRESS
ACC POINTER
REGISTER REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS

PROGRAM
PSW COUNTER

PSEN
ALE/PROG TIMING
AND INSTRUCTION DPTR
EA / VPP CONTROL REGISTER

RST

PORT 1 PORT 3
LATCH LATCH

OSC
PORT 1 DRIVERS PORT 3 DRIVERS

P1.0 - P1.7 P3.0 - P3.7

2 AT89C51

AT89C51

The AT89C51 provides the following standard features: 4K Port 2 pins that are externally being pulled low will source
bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit current (IIL) because of the internal pullups.
timer/counters, a five vector two-level interrupt architecture, Port 2 emits the high-order address byte during fetches
a full duplex serial port, on-chip oscillator and clock cir- from external program memory and during accesses to
cuitry. In addition, the AT89C51 is designed with static logic external data memory that use 16-bit addresses (MOVX @
for operation down to zero frequency and supports two DPTR). In this application, it uses strong internal pullups
software selectable power saving modes. The Idle Mode when emitting 1s. During accesses to external data mem-
stops the CPU while allowing the RAM, timer/counters, ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
serial port and interrupt system to continue functioning. The contents of the P2 Special Function Register.
Power-down Mode saves the RAM contents but freezes
Port 2 also receives the high-order address bits and some
the oscillator disabling all other chip functions until the next
control signals during Flash programming and verification.
hardware reset.
Port 3
Pin Description Port 3 is an 8-bit bi-directional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
VCC When 1s are written to Port 3 pins they are pulled high by
Supply voltage. the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
GND current (IIL) because of the pullups.
Ground. Port 3 also serves the functions of various special features
of the AT89C51 as listed below:
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an Port Pin Alternate Functions
output port, each pin can sink eight TTL inputs. When 1s P3.0 RXD (serial input port)
are written to port 0 pins, the pins can be used as high-
P3.1 TXD (serial output port)
impedance inputs.
Port 0 may also be configured to be the multiplexed low- P3.2 INT0 (external interrupt 0)
order address/data bus during accesses to external pro- P3.3 INT1 (external interrupt 1)
gram and data memory. In this mode P0 has internal
P3.4 T0 (timer 0 external input)
pullups.
Port 0 also receives the code bytes during Flash program- P3.5 T1 (timer 1 external input)
ming, and outputs the code bytes during program P3.6 WR (external data memory write strobe)
verification. External pullups are required during program
P3.7 RD (external data memory read strobe)
verification.

Port 1 Port 3 also receives some control signals for Flash pro-
gramming and verification.
Port 1 is an 8-bit bi-directional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
RST
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs, Reset input. A high on this pin for two machine cycles while
Port 1 pins that are externally being pulled low will source the oscillator is running resets the device.
current (IIL) because of the internal pullups.
ALE/PROG
Port 1 also receives the low-order address bytes during
Flash programming and verification. Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
Port 2 pin is also the program pulse input (PROG) during Flash
programming.
Port 2 is an 8-bit bi-directional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs. In normal operation ALE is emitted at a constant rate of 1/6
When 1s are written to Port 2 pins they are pulled high by the oscillator frequency, and may be used for external tim-
the internal pullups and can be used as inputs. As inputs, ing or clocking purposes. Note, however, that one ALE

3

pulse is skipped during each access to external Data unconnected while XTAL1 is driven as shown in Figure 2.
Memory. There are no requirements on the duty cycle of the external
If desired, ALE operation can be disabled by setting bit 0 of clock signal, since the input to the internal clocking circuitry
SFR location 8EH. With the bit set, ALE is active only dur- is through a divide-by-two flip-flop, but minimum and maxi-
ing a MOVX or MOVC instruction. Otherwise, the pin is mum voltage high and low time specifications must be
weakly pulled high. Setting the ALE-disable bit has no observed.
effect if the microcontroller is in external execution mode.
Idle Mode
PSEN In idle mode, the CPU puts itself to sleep while all the on-
Program Store Enable is the read strobe to external pro- chip peripherals remain active. The mode is invoked by
gram memory. software. The content of the on-chip RAM and all the spe-
When the AT89C51 is executing code from external pro- cial functions registers remain unchanged during this
gram memory, PSEN is activated twice each machine mode. The idle mode can be terminated by any enabled
cycle, except that two PSEN activations are skipped during interrupt or by a hardware reset.
each access to external data memory. It should be noted that when idle is terminated by a hard
ware reset, the device normally resumes program execu-
EA/VPP tion, from where it left off, up to two machine cycles before
External Access Enable. EA must be strapped to GND in the internal reset algorithm takes control. On-chip hardware
order to enable the device to fetch code from external pro- inhibits access to internal RAM in this event, but access to
gram memory locations starting at 0000H up to FFFFH. the port pins is not inhibited. To eliminate the possibility of
Note, however, that if lock bit 1 is programmed, EA will be an unexpected write to a port pin when Idle is terminated by
internally latched on reset. reset, the instruction following the one that invokes Idle
EA should be strapped to V C C for internal program should not be one that writes to a port pin or to external
executions. memory.
This pin also receives the 12-volt programming enable volt- Figure 1. Oscillator Connections
age (VPP) during Flash programming, for parts that require
12-volt VPP. C2
XTAL2
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit. C1
XTAL1
XTAL2
Output from the inverting oscillator amplifier.

GND
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
Note: C1, C2 = 30 pF ± 10 pF for Crystals
crystal or ceramic resonator may be used. To drive the = 40 pF ± 10 pF for Ceramic Resonators
device from an external clock source, XTAL2 should be left

Status of External Pins During Idle and Power-down Modes
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data

4 AT89C51

AT89C51

Figure 2. External Clock Drive Configuration ters retain their values until the power-down mode is
terminated. The only exit from power-down is a hardware
reset. Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before VCC
is restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and
stabilize.

Program Memory Lock Bits
On the chip are three lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the
additional features listed in the table below.
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is nec-
Power-down Mode essary that the latched value of EA be in agreement with
In the power-down mode, the oscillator is stopped, and the the current logic level at that pin in order for the device to
instruction that invokes power-down is the last instruction function properly.
executed. The on-chip RAM and Special Function Regis-

Lock Bit Protection Modes
Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
2 P U U MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further programming of the Flash is disabled
3 P P U Same as mode 2, also verify is disabled
4 P P P Same as mode 3, also external execution is disabled

5

Programming the Flash and data for the entire array or until the end of the
object file is reached.
The AT89C51 is normally shipped with the on-chip Flash
Data Polling: The AT89C51 features Data Polling to indi-
memory array in the erased state (that is, contents = FFH)
cate the end of a write cycle. During a write cycle, an
and ready to be programmed. The programming interface
attempted read of the last byte written will result in the com-
accepts either a high-voltage (12-volt) or a low-voltage
plement of the written datum on PO.7. Once the write cycle
(V CC ) program enable signal. The low-voltage program-
has been completed, true data are valid on all outputs, and
ming mode provides a convenient way to program the
the next cycle may begin. Data Polling may begin any time
AT89C51 inside the user’s system, while the high-voltage
after a write cycle has been initiated.
programming mode is compatible with conventional third-
party Flash or EPROM programmers. Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.4 is pulled
The AT89C51 is shipped with either the high-voltage or
low after ALE goes high during programming to indicate
low-voltage programming mode enabled. The respective
BUSY. P3.4 is pulled high again when programming is
top-side marking and device signature codes are listed in
done to indicate READY.
the following table.
Program Verify: If lock bits LB1 and LB2 have not been
VPP = 12V VPP = 5V programmed, the programmed code data can be read back
Top-side Mark AT89C51 AT89C51 via the address and data lines for verification. The lock bits
xxxx xxxx-5 cannot be verified directly. Verification of the lock bits is
yyww yyww achieved by observing that their features are enabled.
Chip Erase: The entire Flash array is erased electrically
Signature (030H) = 1EH (030H) = 1EH
by using the proper combination of control signals and by
(031H) = 51H (031H) = 51H
holding ALE/PROG low for 10 ms. The code array is written
(032H) =F FH (032H) = 05H with all “1”s. The chip erase operation must be executed
before the code memory can be re-programmed.
The AT89C51 code memory array is programmed byte-by-
Reading the Signature Bytes: The signature bytes are
byte in either programming mode. To program any non-
read by the same procedure as a normal verification of
blank byte in the on-chip Flash Memory, the entire memory
locations 030H, 031H, and 032H, except that P3.6 and
must be erased using the Chip Erase Mode.
P3.7 must be pulled to a logic low. The values returned are
Programming Algorithm: Before programming the as follows.
AT89C51, the address, data and control signals should be
(030H) = 1EH indicates manufactured by Atmel
set up according to the Flash programming mode table and
(031H) = 51H indicates 89C51
Figure 3 and Figure 4. To program the AT89C51, take the
(032H) = FFH indicates 12V programming
following steps.
(032H) = 05H indicates 5V programming
1. Input the desired memory location on the address
lines.
2. Input the appropriate data byte on the data lines.
Programming Interface
3. Activate the correct combination of control signals. Every code byte in the Flash array can be written and the
entire array can be erased by using the appropriate combi-
4. Raise EA/VPP to 12V for the high-voltage program-
nation of control signals. The write operation cycle is self-
ming mode.
timed and once initiated, will automatically time itself to
5. Pulse ALE/PROG once to program a byte in the completion.
Flash array or the lock bits. The byte-write cycle is
All major programming vendors offer worldwide support for
self-timed and typically takes no more than 1.5 ms.
the Atmel microcontroller series. Please contact your local
Repeat steps 1 through 5, changing the address
programming vendor for the appropriate software revision.

6 AT89C51

AT89C51

Flash Programming Modes
Mode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7
Write Code Data H L H/12V L H H H

Read Code Data H L H H L L H H
Write Lock Bit - 1 H L H/12V H H H H

Bit - 2 H L H/12V H H L L

Bit - 3 H L H/12V H L H L

Chip Erase H L (1) H/12V H L L L

Read Signature Byte H L H H L L L L
Note: 1. Chip Erase requires a 10 ms PROG pulse.

Figure 3. Programming the Flash Figure 4. Verifying the Flash
+5V +5V
AT89C51 AT89C51
A0 - A7 VCC A0 - A7 VCC
ADDR. P1 ADDR. P1
OOOOH/OFFFH PGM OOOOH/0FFFH PGM DATA
P2.0 - P2.3 P0 P2.0 - P2.3 P0 (USE 10K
A8 - A11 DATA A8 - A11 PULLUPS)
P2.6 P2.6

SEE FLASH P2.7 ALE PROG SEE FLASH P2.7 ALE
PROGRAMMING PROGRAMMING
MODES TABLE P3.6 MODES TABLE P3.6
VIH
P3.7 P3.7

XTAL2 EA VIH/VPP XTAL2 EA

3-24 MHz 3-24 MHz

XTAL1 RST VIH XTAL1 RST VIH

GND PSEN GND PSEN

7

Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V)
PROGRAMMING VERIFICATION
P1.0 - P1.7
ADDRESS ADDRESS
P2.0 - P2.3
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tGHDX
tAVGL tGHAX
ALE/PROG
tSHGL tGHSL
tGLGH
VPP LOGIC 1
EA/VPP LOGIC 0

tEHSH tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY) BUSY READY
tWC

Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V)
PROGRAMMING VERIFICATION
P1.0 - P1.7
ADDRESS ADDRESS
P2.0 - P2.3
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tGHDX
tAVGL tGHAX
ALE/PROG
tSHGL
tGLGH
LOGIC 1
EA/VPP LOGIC 0

tEHSH tEHQZ
tELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY) BUSY READY
tWC

8 AT89C51

AT89C51

Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 ± 10%
Symbol Parameter Min Max Units
(1)
VPP Programming Enable Voltage 11.5 12.5 V
IPP(1) Programming Enable Current 1.0 mA
1/tCLCL Oscillator Frequency 3 24 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold after PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold after PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGHSL(1) VPP Hold after PROG 10 µs
tGLGH PROG Width 1 110 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float after ENABLE 0 48tCLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 2.0 ms
Note: 1. Only used in 12-volt programming mode.

9

Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage ............................................ 6.6V conditions for extended periods may affect device
reliability.
DC Output Current...................................................... 15.0 mA

DC Characteristics
TA = -40°C to 85°C, VCC = 5.0V ± 20% (unless otherwise noted)
Symbol Parameter Condition Min Max Units

VIL Input Low-voltage (Except EA) -0.5 0.2 VCC - 0.1 V

VIL1 Input Low-voltage (EA) -0.5 0.2 VCC - 0.3 V

VIH Input High-voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High-voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V
(1)
VOL Output Low-voltage (Ports 1,2,3) IOL = 1.6 mA 0.45 V
(1)
Output Low-voltage
VOL1 IOL = 3.2 mA 0.45 V
(Port 0, ALE, PSEN)

IOH = -60 µA, VCC = 5V ± 10% 2.4 V
Output High-voltage
VOH IOH = -25 µA 0.75 VCC V
(Ports 1,2,3, ALE, PSEN)
IOH = -10 µA 0.9 VCC V

IOH = -800 µA, VCC = 5V ± 10% 2.4 V
Output High-voltage
VOH1 IOH = -300 µA 0.75 VCC V
(Port 0 in External Bus Mode)
IOH = -80 µA 0.9 VCC V

IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

Logical 1 to 0 Transition Current
ITL VIN = 2V, VCC = 5V ± 10% -650 µA
(Ports 1,2,3)

ILI Input Leakage Current (Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pull-down Resistor 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF

Active Mode, 12 MHz 20 mA
Power Supply Current
Idle Mode, 12 MHz 5 mA
ICC
VCC = 6V 100 µA
Power-down Mode(2)
VCC = 3V 40 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port: Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
2. Minimum VCC for Power-down is 2V.

10 AT89C51

AT89C51

AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.

External Program and Data Memory Characteristics
12 MHz Oscillator 16 to 24 MHz Oscillator
Symbol Parameter Min Max Min Max Units
tLHLL ALE Pulse Width 127 2tCLCL-40 ns
tAVLL Address Valid to ALE Low 43 tCLCL-13 ns
tLLAX Address Hold after ALE Low 48 tCLCL-20 ns
tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns
tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns
tPLPH PSEN Pulse Width 205 3tCLCL-20 ns
tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns
tPXIX Input Instruction Hold after PSEN 0 0 ns
tPXIZ Input Instruction Float after PSEN 59 tCLCL-10 ns
tPXAV PSEN to Address Valid 75 tCLCL-8 ns
tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns
tPLAZ PSEN Low to Address Float 10 10 ns
tRLRH RD Pulse Width 400 6tCLCL-100 ns
tWLWH WR Pulse Width 400 6tCLCL-100 ns
tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns
tRHDX Data Hold after RD 0 0 ns
tRHDZ Data Float after RD 97 2tCLCL-28 ns
tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns
tAVDV Address to Valid Data In 585 9tCLCL-165 ns
tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns
tAVWL Address to RD or WR Low 203 4tCLCL-75 ns
tQVWX Data Valid to WR Transition 23 tCLCL-20 ns
tQVWH Data Valid to WR High 433 7tCLCL-120 ns
tWHQX Data Hold after WR 33 tCLCL-20 ns
tRLAZ RD Low to Address Float 0 0 ns
tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns

11

External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL tLLIV
tLLPL
PSEN tPLIV
tPXAV
tPLAZ
tPXIZ
tLLAX
tPXIX
PORT 0 A0 - A7 INSTR IN A0 - A7

tAVIV

PORT 2 A8 - A15 A8 - A15

External Data Memory Read Cycle
tLHLL
ALE
tWHLH

PSEN
tLLDV
tRLRH
tLLWL

RD tLLAX
tRLDV tRHDZ
tAVLL
tRLAZ
tRHDX

PORT 0 A0 - A7 FROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN

tAVWL
tAVDV
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

12 AT89C51

AT89C51

External Data Memory Write Cycle
tLHLL
ALE
tWHLH

PSEN
tLLWL tWLWH

WR tLLAX
tAVLL tQVWX tWHQX
tQVWH

PORT 0 A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN

tAVWL

PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

External Clock Drive Waveforms

tCHCX
tCHCX tCLCH tCHCL
VCC - 0.5V
0.7 VCC

0.2 VCC - 0.1V
0.45V
tCLCX
tCLCL

External Clock Drive
Symbol Parameter Min Max Units
tCLCL Clock Period 41.6 ns
tCHCX High Time 15 ns
tCLCX Low Time 15 ns
tCLCH Rise Time 20 ns
tCHCL Fall Time 20 ns

13

Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)
12 MHz Osc Variable Oscillator Units
Symbol Parameter Min Max Min Max
tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs
tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns
tXHQX Output Data Hold after Clock Rising Edge 50 2tCLCL-117 ns
tXHDX Input Data Hold after Clock Rising Edge 0 0 ns
tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

Shift Register Mode Timing Waveforms
INSTRUCTION 0 1 2 3 4 5 6 7 8
ALE
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF 0 1 2 3 4 5 6 7
tXHDX
OUTPUT DATA tXHDV SET TI
CLEAR RI VALID VALID VALID VALID VALID VALID VALID VALID

INPUT DATA SET RI

AC Testing Input/Output Waveforms(1) Float Waveforms(1)

VCC - 0.5V V OL -
0.2 VCC + 0.9V V LOAD+ 0.1V 0.1V

TEST POINTS V LOAD Timing Reference
Points
0.2 VCC - 0.1V V LOAD - 0.1V V OL + 0.1V
0.45V

Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a Note: 1. For timing purposes, a port pin is no longer floating
logic 1 and 0.45V for a logic 0. Timing measurements when a 100 mV change from load voltage occurs. A
are made at VIH min. for a logic 1 and VIL max. for a port pin begins to float when 100 mV change from
logic 0. the loaded VOH/VOL level occurs.

14 AT89C51

AT89C51

Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
12 5V ± 20% AT89C51-12AC 44A Commercial
AT89C51-12JC 44J (0° C to 70° C)
AT89C51-12PC 40P6
AT89C51-12QC 44Q
AT89C51-12AI 44A Industrial
AT89C51-12JI 44J (-40° C to 85° C)
AT89C51-12PI 40P6
AT89C51-12QI 44Q
AT89C51-16JC 44J (0° C to 70° C)
AT89C51-16PC 40P6
AT89C51-16QC 44Q
AT89C51-16JI 44J (-40° C to 85° C)
AT89C51-16PI 40P6
AT89C51-16QI 44Q
AT89C51-20JC 44J (0° C to 70° C)
AT89C51-20PC 40P6
AT89C51-20QC 44Q
AT89C51-20JI 44J (-40° C to 85° C)
AT89C51-20PI 40P6
AT89C51-20QI 44Q
AT89C51-24JC 44J (0° C to 70° C)
AT89C51-24PC 40P6
AT89C51-24QC 44Q
AT89C51-24JI 44J (-40° C to 85° C)
AT89C51-24PI 40P6
AT89C51-24QI 44Q

Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44Q 44-lead, Plastic Gull Wing Quad Flatpack (PQFP)

15

Packaging Information
44A, 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Flatpack (TQFP) Dimensions in Inches and (Millimeters)
Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-018 AC
JEDEC STANDARD MS-026 ACB

12.21(0.478) .045(1.14) X 45° PIN NO. 1 .045(1.14) X 30° - 45° .012(.305)
PIN 1 ID SQ
11.75(0.458) IDENTIFY .008(.203)

.656(16.7) .630(16.0)
0.45(0.018) SQ
.650(16.5) .590(15.0)
0.80(0.031) BSC 0.30(0.012)
.032(.813) .021(.533)
.026(.660) .695(17.7) .013(.330)
SQ
.685(17.4)

.050(1.27) TYP .043(1.09)
.500(12.7) REF SQ .020(.508)
.120(3.05)
.090(2.29)
10.10(0.394) .180(4.57)
SQ
9.90(0.386) .165(4.19)
1.20(0.047) MAX
0
0.20(.008) 7
0.09(.003)
.022(.559) X 45° MAX (3X)

0.75(0.030) 0.15(0.006)
0.45(0.018) 0.05(0.002)

Controlling dimension: millimeters

40P6, 40-lead, 0.600" Wide, Plastic Dual Inline 44Q, 44-lead, Plastic Quad Flat Package (PQFP)
Package (PDIP) Dimensions in Millimeters and (Inches)*
Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-022 AB

2.07(52.6) 13.45 (0.525)
2.04(51.8) PIN
SQ
12.95 (0.506)
1
PIN 1 ID

.566(14.4)
.530(13.5)
0.50 (0.020)
0.80 (0.031) BSC 0.35 (0.014)

.090(2.29)
1.900(48.26) REF MAX
.220(5.59) .005(.127)
MAX MIN

SEATING
PLANE
.065(1.65)
.161(4.09) .015(.381)
.125(3.18) 10.10 (0.394)
.022(.559) SQ
.065(1.65) .014(.356) 9.90 (0.386)
.110(2.79) .041(1.04)
.090(2.29)
.630(16.0) 2.45 (0.096) MAX
.590(15.0) 0
0 REF 0.17 (0.007) 7
15 0.13 (0.005)
.012(.305)
.008(.203)
.690(17.5)
1.03 (0.041)
.610(15.5) 0.25 (0.010) MAX
0.78 (0.030)

Controlling dimension: millimeters

16 AT89C51

Atmel Headquarters Atmel Operations
Corporate Headquarters Atmel Colorado Springs
2325 Orchard Parkway 1150 E. Cheyenne Mtn. Blvd.
San Jose, CA 95131 Colorado Springs, CO 80906
TEL (408) 441-0311 TEL (719) 576-3300
FAX (408) 487-2600 FAX (719) 540-1759
Europe Atmel Rousset
Atmel U.K., Ltd. Zone Industrielle
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Riverside Way France
Camberley, Surrey GU15 3YL TEL (33) 4-4253-6000
England FAX (33) 4-4253-6001
TEL (44) 1276-686-677
FAX (44) 1276-686-697
Asia
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Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Fax-on-Demand
North America:
1-(800) 292-8635
International:
1-(408) 441-0732

e-mail
literature@atmel.com

Web Site
http://www.atmel.com

BBS
1-(408) 436-4309

© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop-
erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life suppor t devices or systems.
® ™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Printed on recycled paper.
Terms and product names in this document may be trademarks of others.
0265G–02/00/xM

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