Attachment_ VHDL datasheet
- 1. Design Sheet 1. Team Members Team member: Name Team member: Name 2. Design Overview The design and instructionset is fora16-register 16-bit computer. Likein MIPSarchitecture,register 0 will always contain the value 0. The machine code instruction is 6 bits meaning it can handle up to 64 different instructions, but the design will be limited to only 25 different instructions. Each instruction and operation is triggered by the rise of the computer clock. 2.1. Instructionformat R-Format: Opcode rs rt 0 rd 5 bits 3 bits 3 bits 2 bits 3 bits I–Format: Opcode rs rt Immediate 5 bits 3 bits 3 bits 5 bits 2.2. Instructions Name Mnem onic Operation Opcode Func For mat Add immediate addi addi $s1, $s2, I; $s1 = $s2 + I 00000 000000 I Subtract immediate subi sub $s1, $s2, I; $s1 = $s2 – I 00001 000000 I OR immediate ori ori $s1, $s2, I; $s1= $s2 v I 00010 000000 I AND immediate andi andi $s1, $s2, I; $s1= $s2 ^ I 00011 000000 I XORimmediate xori xori $s1, $s2, I; $s1= $s2 ⊕I 00100 000000 I NOR immediate nori nori $s1, $s2, I;$s1= ~($s2| I) 00101 000000 I NAND immediate nandi andi $s1, $s2, I; $s1= ~($s2& I) 00110 000000 I XNORimmediate xnori xori $s1, $s2, I; $s1= ~($s2⊕I) 00111 000000 I Add add add $s1, $s2, $s3; $s1 = $s2 + $s3 01000 000000 R Subtract sub sub $s1, $s2, $s3; $s1 = $s2 - $s3 01001 000000 R OR or or $s1, $s2, $s3; $s1= $s2 v $s3 01010 000000 R AND and and $s1, $s2, $s3; $s1= $s2 ^ $s3 01011 000000 R XOR xor xor $s1, $s2, $s3; $s1= $s2 ⊕$s3 01100 000000 R NOR nor nor $s1, $s2, $s3; $s1= ~($s2| $s3) 01101 000000 R
- 2. NAND nand and $s1, $s2, $s3; $s1= ~($s2& $s3) 01110 000000 R XNOR xnor xor $s1, $s2, $s3; $s1= ~($s2⊕ $s3) 01111 000000 R Branch if equal beq beq $s1, $s2, $s3; if $s1=$s2, j to $s3 10000 000000 R Branch if not equal bne bne $s1, $s2, $s3; if $s1=/=$s2, j to $s3 10001 000000 R Shift bits to the left sl Sl $s1, $s2, I; $s1 = $s2 << I 10010 000000 I Shift bits to the right sr Sl $s1, $s2, I; $s1 = $s2 >> I 10011 000000 I Jump j J I 10100 000000 J No operation nop nop 10101 000000 J Move immediate movi movi $s1, I; $s1 = I 10110 000000 I Move mov mov $s1, $s2; $s1 = $s2 10111 000000 I The instructions supported are ● Arithmetic-logical instructions ● Control flow instructions Individual functional units:
- 3. R-Type Instructions R typeinstructions take2 registers and performALU operation on these two.The result of whichwill be written to another register. I-TypeInstructions I type instructions is almost the same as R type instructions with the exception that the second operand forI type instruction is an immediate value given by the user. Both instructions willfollow the same data path shown below Considering the data path given, the main differencebetween the R and I typeinstruction is that the ALUSrc for the R type instructions will be set to 1 so that the multiplexer connected to the input of the main ALU will be the second read data. Consequently, I typeinstructions will have its ALUSrc set to 0, so the multiplexer connected to the main ALU will be the first 16 bits.
- 4. JUMP
- 5. The data path followedby the jump instruction resembles the complete data path for the computer. The only thing missing is the controlunit. Thecontrolunit is responsible for setting whichvalues will pass through each of the multiplexors available.
- 6. The figure above shows the complete data path with the control unit. The simple control unit produces a certain array of bits depending on the type of instruction given. Instruction RegDst ALUSr c MemToReg MemWrite MemRea d Branch Jump RegWrit e R-format 1 0 0 0 0 0 0 1 I-format 0 0 0 0 0 0 0 1 J-format x 0 x 0 0 1 1 0