BASIC COMPUTER ORGANIZATION AND DESIGN

MATERIAL PREPARED BY ANIL REDDY [2/4 CSE]
BASIC COMPUTER ORGANIZATION AND DESIGN
Instruction Codes
A computer instruction is a binary code that specifies a sequence of micro operations for the
computer. Instruction codes together with data are stored in memory. The computer reads each
instruction from memory and places it in a control register. The control then interprets the binary
code of the instruction and proceeds to execute it by issuing a sequence of micro operations.
Every computer has its own unique instruction set. The ability to store and execute instructions,
the stored program concept, is the most important property of a general-purpose computer.
Instruction Code
An instruction code is a group of bits that instruct the computer to perform a specific operation.
Operation Code
The operation code of an instruction is a group of bits that define such operations as add, subtract,
multiply, shift, and complement. The number of bits required for the operation code of an
instruction depends on the total number of operations available in the computer. The operation
code must consist of at least n bits for a given 2 n (or less) distinct operations.
Accumulator (AC)
Computers that have a single-processor register usually assign to it the name accumulator (AC)
accumulator and label it AC. The operation is performed with the memory operand and the content
of AC.
Stored Program Organization
· The simplest way to organize a computer is to have one processor register and an
instruction code format with two parts.
· The first part specifies the operation to be performed and the second specifies an address.
· The memory address tells the control where to find an operand in memory.
· This operand is read from memory and used as the data to be operated on together with
the data stored in the processor register.
· The following figure shows this type of organization.
Figure: Stored Program Organization

· Instructions are stored in one section of memory and data in another.
· For a memory unit with 4096 words, we need 12 bits to specify an address since 212
=
4096.
· If we store each instruction code in one 16-bit memory word, we have available four bits for
operation code (abbreviated opcode) to specify one out of 16 possible operations, and 12
bits to specify the address of an operand.
· The control reads a 16-bit instruction from the program portion of memory.
· It uses the 12-bit address part of the instruction to read a 16-bit operand from the data
portion of memory.
· It then executes the operation specified by the operation code.
· Computers that have a single-processor register usually assign to it the name accumulator
and label it AC.
· If an operation in an instruction code does not need an operand from memory, the rest of
the bits in the instruction can be used for other purposes.
· For example, operations such as clear AC, complement AC, and increment AC operate on
data stored in the AC register. They do not need an operand from memory. For these types
of operations, the second part of the instruction code (bits 0 through 11) is not needed for
specifying a memory address and can be used to specify other operations for the computer.
Direct and indirect addressing of basic computer
Fig:- Demonstration of direct and indirect address.
3 – Address Format:
1. Immediate address: If the data or information in the instruction code.

In the second part of the instruction code specifies an operand, the instruction is said have
immediate operand.
2. Direct Address: The second part of an instruction format specifies the address of an
operand, the instruction is said to have a direct address.
3. Indirect Address: In Indirect address, the bits in the second part of the instruction
designate an address of a memory word in which the address of the operand is found.
4. Effective Address: The address of an operand is said to be the effective address
5. 12–Bit Address: It can be designated as direct or indirect based on the mode bit. The
mode bit is zero for the direct address of 1 for indirect address
· A direct address instruction is shown in Figure. It is placed in address 22 in memory.
· The I bit is 0, so the instruction is recognized as a direct address instruction.
· The I bit is 0, so the instruction is recognized as a direct address instruction.
· The opcode specifies an ADD instruction, and the address part is the binary equivalent of
457.
· The control finds the operand in memory at address 457 and adds it to the content of AC.
· The instruction in address 35 shown in Figure 2.3 has a mode bit I = 1, recognized as an
indirect address instruction.
· The address part is the binary equivalent of 300.
· The control goes to address 300 to find the address of the operand.
· The address of the operand in this case is 1350. The operand found in address 1350 is
then added to the content of AC.
· The indirect address instruction needs two references to memory to fetch an operand.
1. The first reference is needed to read the address of the operand
2. Second reference is for the operand itself.
· The memory word that holds the address of the operand in an indirect address instruction is
used as a pointer to an array of data.
Direct Address Indirect Address
When the second part of an instruction
code specifies the address of an operand,
the instruction is said to have a direct
address.
When the second part of an instruction
code specifies the address of a memory
word in which the address of the operand,
the instruction is said to have a direct
address.
For instance the instruction MOV R0 00H.
R0, when converted to machine language
is the physical address of register R0. The
instruction moves 0 to R0.
For instance the instruction MOV @R0
00H, when converted to machine language,
@R0 becomes whatever is stored in R0,
and that is the address used to move 0 to.
It can be whatever is stored in R0.

Computer Registers:
Registers of basic computer
· It is necessary to provide a register in the control unit for storing the instruction code after it
is read from memory.
· The computer needs processor registers for manipulating data and a register for holding a
memory address.
· These requirements dictate the register configuration
Fig: - Basic computer registers and memory
Fig: - List of Registers for the Basic Computer
The explanation for each of the registers specified in figure: Basic computer registers and memory
as follows
1. The data register holds the operand read from the memory
2. The accumulator is a general purpose register used for processing
3. The instruction register holds the read memory
4. The temporary data used while processing is stored in the temporary register
5. The address register holds the address of the instruction that is to be executed next from
the memory

6. The program counter [ pc ] controls the sequence of instructions to be read. In case a
branch instruction is encountered, the sequential execution does not happen. A branch
execution calls for a transfer to an instruction that is not in sequence with the instructions in
the PC. The address of this non – consecutive instruction is passed on to the PC to replace
the existing instruction address. to read an instruction, the memory cycle is initiated again
with the PC content taken as address for memory. Next, the PC incremented by one and
the previous order continues.
7. The input register INPR and output register OUTPR are the registers used for the I/O
operations. The INPR receives an 8-bit character from the input device, same with the
OUTPR.
Common Bus System
The basic computer has eight registers, a memory unit, and a control unit. Paths must be provided
to transfer information from one register to another and between memory and registers.
The outputs of seven registers and memory are connected to the common bus. S0 , S1 , S2 are the
selection values that are connected to the bus.
The selection values determine the output that is selected for the bus lines at any given time. Each
of the output has a number along with it, which indicates the decimal equivalent of the required
binary selection.
· The input register INPR and the output register OUTR have 8 bits each and communicate with the
eight least significant bits in the bus. INPR is connected to provide information to the bus but OUTR
can only receive information from the bus.

· The 16 lines of the common bus receive information from six registers and the memory unit.
· Five registers have three control inputs: LD (load), INR (increment), and CLR (clear).
· Two registers have only a LD (Load) are IR and OUTR.
· The input data and output data of the memory are connected to the common bus, but the memory
address is connected to AR.
· The 16 inputs of AC come from an adder and logic circuit. This circuit has three sets of inputs. One
set of 16-bit inputs come from the outputs of AC.
· They are used to implement register Micro operations such as complement AC and shift AC.
· Another set of 16-bit inputs come from the data register DR.
· Moreover, The result of an addition transferred to AC and the end carry-out of the addition
transferred to flip-flop E (extended AC bit).
· A third set of 8-bit inputs come from the input register INPR. The content of any register can be
applied onto the bus and an operation can be performed in the adder and logic circuit during the
same clock cycle. The clock transition at the end of the cycle transfers the content of the bus into
the designated destination register.
Computer Instructions:
Instruction Format
· An instruction format or instruction code is a group of bits used to perform a particular
operation on the data stored in computer.
· Processor fetches an instruction from memory and decodes the bits to execute the
instruction.
· Different computers may have their own instruction set.
· Instruction code is divided into two parts namely operation code and address of data.
· Operation code consisting group of bits to define an operation such as add, subtract,
multiply etc.
· In an instruction format:
· First 12 bits (0-11) specify an address.
· Next 3 bits specify operation code (opcode).
· Left most bit specify the addressing mode I
· I = 0 for direct address
· I = 1 for indirect address

Types of Instructions
The basic computer has three 16-bit instruction code formats:
The basic computer has 3 instruction code formats
1. Memory reference instructions
2. Register – reference instructions
3. I/P – O/P instructions
Memory reference instructions
In Memory reference instruction:
· First 12 bits(0-11) specify an address.
· Next 3 bits specify operation code (opcode).
· Left most bit specify the addressing mode I
· I = 0 for direct address
· I = 1 for indirect address
· The address field is denoted by three x’s (in hexadecimal notation) and is equivalent to 12-
bit address.
· The last mode bit of the instruction represents by symbol I.
· When I = 0, the last four bits of an instruction have a hexadecimal digit equivalent from 0 to
6 since the last bit is zero (0).
· When I = 1 the last four bits of an instruction have a hexadecimal digit equivalent from 8 to
E since the last bit is one (1).

Register – reference instructions
In Register Reference Instruction:
· First 12 bits (0-11) specify the register operation.
· The next three bits equals to 111 specify opcode.
· The last mode bit of the instruction is 0.
· Therefore, left most 4 bits are always 0111 which is equal to hexadecimal 7.
I/O Reference Instructions
· First 12 bits (0-11) specify the I/O operation.
· The next three bits equals to 111 specify opcode.
· The last mode bit of the instruction is 1.
· Therefore, left most 4 bits are always 1111 which is equal to hexadecimal F.

Instruction Set Completeness
A computer should have a set of instructions so that the user can construct machine language
programs to evaluate any function that is known to be computable.
Instruction Types:-
Functional Instructions
- Arithmetic, logic, and shift instructions
- ADD, CMA, INC, CIR, CIL, AND, CLA
Transfer Instructions
- Data transfers between the main memory and the processor registers
- LDA, STA
Control Instructions
- Program sequencing and control
- BUN, BSA, ISZ
Input/output Instructions
- Input and output
- INP, OUT
Timing and Control Unit
The timing for all register in basic computer is controlled by a master clock generator.
Clock pulses – The clock pulses are applied to all flip-flops and registers in the system, including
the flip-flops in the control unit. The clock pulses do not change the state of a register unless the
register is unable by a control signal.
Design of Control Unit
Control unit generates control signals using one of the two organizations:
· Hardwired Control Unit
· Micro-programmed Control Unit
Hardwired Control Unit
· It is implemented as logic circuits (gates, flip-flops, decoders etc.) in the hardware.
· This organization is very complicated if we have a large control unit.
· In this organization, if the design has to be modified or changed, requires changes in the
wiring among the various components. Thus the modification of all the combinational
circuits may be very difficult.

Advantages
· Hardwired Control Unit is fast because control signals are generated by combinational
circuits.
· The delay in generation of control signals depends upon the number of gates.
Disadvantages
· More is the control signals required by CPU; more complex will be the design of control
unit.
· Modifications in control signal are very difficult. That means it requires rearranging of wires
in the hardware circuit.
· It is difficult to correct mistake in original design or adding new feature in existing design of
control unit.
Fig:- control unit of basic computer
· Control unit consist of a Instruction Register, Number of Control Logic Gates, Two
Decoders, 4-bit Sequence Counter
· An instruction read from memory is placed in the instruction register (IR).
· The instruction register is divided into three parts: the I bit, operation code, and address
part.
· First 12-bits (0-11) to specify an address, next 3-bits specify the operation code (opcode)
field of the instruction and last left most bit specify the addressing mode I.
I = 0 for direct address
I = 1 for indirect address
· First 12-bits (0-11) are applied to the control logic gates.
· The operation code bits (12 – 14) are decoded with a 3 x 8 decoder.

· The eight outputs ( D0 through D7) from a decoder goes to the control logic gates to perform
specific operation.
· Last bit 15 is transferred to a I flip-flop designated by symbol I.
· The 4-bit sequence counter SC can count in binary from 0 through 15.
· The counter output is decoded into 16 timing pulses T0 through T15.
· The sequence counter can be incremented by INR input or clear by CLR input
synchronously.
· For example: Consider the case where SC is incremented to provide timing signalsT0, T1,
T2 , T3, and T4 in sequence. At time T4 , SC is cleared to 0 if decoder output D3 is active.
This is expressed symbolically by the statement: D3 T4 : SC ←0
· The timing diagram shows the time relationship of the control signals.
Fig: - Example of control timing signals.
Micro-Programmed Control Unit
· A micro-programmed control unit is implemented using programming approach. A
sequence of micro operations are carried out by executing a program consisting of micro-
instructions.
· Micro-program, consisting of micro-instructions is stored in the control memory of the
control unit.
· Execution of a micro-instruction is responsible for generation of a set of control signals.
A micro-instruction consists of:
· One or more micro-operations to be executed.
· Address of next microinstruction to be executed.
Micro-Operations: The operations performed on the data stored inside the registers are called
micro operations.
Micro-Programs: Microprogramming is the concept for generating control signals using
programs. These programs are called micro-programs.
Micro-Instructions: The instructions that make micro-program are called micro-instructions.

Micro-Code: Micro-program is a group of microinstructions. The micro-program can also be
termed as micro-code.
Control Memory: Micro-programs are stored in the read only memory (ROM). That memory is
called control memory.
Advantages
· The design of micro-program control unit is less complex because micro-programs are
implemented using software routines.
· The micro-programmed control unit is more flexible because design modifications,
correction and enhancement is easily possible.
· The new or modified instruction set of CPU can be easily implemented by simply rewriting
or modifying the contents of control memory.
· The fault can be easily diagnosed in the micro-program control unit using diagnostics tools
by maintaining the contents of flags, registers and counters.
Disadvantages
· The micro-program control unit is slower than hardwired control unit. That means to
execute an instruction in micro-program control unit requires more time.
· The micro-program control unit is expensive than hardwired control unit in case of limited
hardware resources.
· The design duration of micro-program control unit is more than hardwired control unit for
smaller CPU.
Instruction Cycle
The program is executed in the computer by going through a cycle for each instruction. Each
instruction cycle in turn is subdivided into a sequence of sub cycles or phases. In the basic
computer each instruction cycle consists of the following phases:
1. Fetch an instruction from the memory.
2. Decode the instruction.
3. Read the effective address from the memory if the instruction has an indirect address.
4. Execute the instruction.
Upon the completion of step 4, the control goes back to step 1 to fetch, decode, and execute the
next instruction. This process continues indefinitely unless a HALT instruction is encountered.
Fetch and Decode Phase
Initially, the program counter PC is loaded with the address of the first instruction in the program.
The sequence counter SC is cleared to 0, providing a decoded timing signal To. After each clock
pulse, SC is incremented by one, so that the timing signals go through a sequence T0, T1, T2, and
so on.
The rnicro operations for the fetch and decode phases can be specified by the following register
transfer statements.

Register transfers for the fetch phase
Fig: - Register transfers for the fetch phase
To provide the data path for the transfer of PC to AR we must apply timing signal T0 to achieve the
following connection:
1. Place the content of PC onto the bus by making the bus selection inputs S2S1S0 equal to 010.
2. Transfer the content of the bus to AR by enabling the LD input of AR.
The next clock transition initiates the transfer from PC to AR. In order to implement
T1: IR <-M[AR], PC <- PC + 1
It is necessary to use timing signal T1 to provide the following connections in the bus system
1. Enable the read input of memory.
2. Place the content of memory onto the bus by making S2S1S0 = 111.
3. Transfer the content of the bus to IR by enabling the LD input of IR.
4. Increment PC by enabling the INR input of PC.
The next clock transition initiates the read and increment operations since T1 = 1.
During the timing signals the control unit determines the type of the instructions, that was read
from the memory

Flow Chart
Decoder output D, is equal to 1 if the operation code is equal to binary 111 then the instruction
must be register reference.
If D7 = 0, the operation code must be one of the other seven values 000 through 110, specifying a
memory-reference instruction. Control then inspects the value of the first bit of the instruction,
Which is now available in flip-flop I. If D7 = 0 and I = 1, we have a memory reference instruction
with an indirect address.
The three instruction types are subdivided into four separate paths. The selected operation is
activated with the clock transition associated with timing signal T3. This can be symbolized as
follows:
When a memory-reference instruction with I = 0 is encountered, it is not necessary to do anything
since the effective address is already in address register but when D7 = 0 & I = 1, then it is
necessary to read the effective address from the memory shown by the register transfer
statement.

Register Reference Instructions
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 I¢T3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
Memory Reference Instructions
¾ The effective address of the instruction is in AR and was placed there during timing signal
T2 when I = 0, or during timing signal T3 when I = 1
¾ Memory cycle is assumed to be short enough to complete in a CPU cycle
¾ The execution of MR Instruction starts with T4
Fig: - Memory - Reference Instructions

AND to AC
This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory
word specified by the effective address. The result of the operation is transferred to AC.
ADD to AC
This instruction adds the content of the memory word specified by the effective address to the
value of AC .The sum is transferred into AC and the output carry Cout is transferred to the E
(extended accumulator) flip-flop.
LDA: Load to AC
This instruction transfers the memory word specified by the effective address to AC.
STA: Store AC
This instruction stores the content of AC into the memory word specified by the effective address.
Since the output of AC is applied to the bus and the data input of memory is connected to the bus,
we can execute this instruction with one micro operation:
BUN: Branch Unconditionally
This instruction transfers the program to the instruction specified by the effective address.
Remember that PC holds the address of the instruction to be read from memory in the next
instruction cycle. PC is incremented at time T1 to prepare it for the address of the next instruction
in the program sequence. The BUN instruction allows the programmer to specify an instruction out
of sequence and we say that the program branches (or jumps) unconditionally.
BSA: Branch and Save Return Address
This instruction is useful for branching to a portion of the program called a subroutine or
procedure. When executed, the BSA instruction stores the address of the next instruction in
sequence (which is available in PC) into a memory location specified by the effective address. The
effective address plus one is then transferred to PC to serve as the address of the first instruction
in the subroutine. This operation was specified in with the following register transfer:

Example of BSA instruction execution: -
ISZ: Increment and Skip if Zero
This instruction increments the word specified by the effective address, and if the incremented
value is equal to 0, PC is incremented by 1.
Control Flowchart
Fig: - Flowchart For Memory Reference Instructions

Input – Output and Interrupt
Input/output:
A computer can serve no useful purpose unless it communicates with the external environment.
Instructions and data stored in memory must come from some input device. Computational results
must be transmitted to the user through some output device. Commercial computers include many
types of input and output devices.
Input-Output Configuration:
That illustrates the Input/output configuration. The terminals here are the keyboard and printer.
They send and receive the information serially. The information is alphanumeric and 8 bits in size.
The input provided through the keyboard is sent to the input register INPR. The data is stored in
the OUTPR (output register) in the serial order for the printer. The OUTR stores the serial
information for the printer
Fig: - input output configuration
Fig refers to 1 bit input flag which is a flip-flop. When the input device receives any new data, the
flip-flop is set to 1. It is cleared to 0 when data is accepted by output device. The difference
between the timing rates of input devices and computer is synchronized by the flag. The case is
similar with the output device, the difference being the change in direction of the data flow. The
output device sets the FGO to 1 after accepting, decoding and printing the data. FGO in the 0
mode indicates that the device is printing data.
Input-Output Instructions
Input and output instructions are needed for transferring information to and from AC register, for
checking the flag bits, and for controlling the interrupt facility. Input-output instructions have an
operation code 1111 and are recognized by the control when D7 = 1 and I = 1. The remaining bits
of the instruction specify the particular operation.
The control function is distinguished by one of the bits in IR(6-11).

Program Interrupt:
¾ The process of communication just described is referred to as programmed control transfer.
The computer keeps checking the flag bit, and when it finds it set, it initiates an information
transfer.
¾ The computer is wasting time while checking the flag instead of doing some other useful
processing task
¾ IEN & IOF, These two instructions provide the programmer with the capability of making a
decision as to whether or not to use the interrupt facility.
FIG: - Flowchart for interrupt cycle.

¾ The interrupt cycle is a hardware implementation of a branch and save return address
operation.
¾ Control then inserts address 1 into PC and clears lEN and R so that no more interruptions
can occur until the interrupt request from the flag has been serviced.
¾ The content of PC (256) is stored in memory location 0, PC is set to 1, and R is cleared to
0. At the beginning of the next instruction cycle, the instruction that is read from memory is
in address 1 since this is the content of PC .
¾ The effective address is in location 0 and is the return address that was stored there during
the previous interrupt cycle. The execution of the indirect BUN instruction results in placing
into PC the return address from location 0.

Complete Computer Description
Micro Operations

Design of Basic Computer
The basic computer consists of the following hardware components:
1. A memory unit with 4096 words of 16 bits each
2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
3. Seven flip-flops: I, S , E, R, lEN, FGI, and FGO
4. Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder
5. A 16-bit common bus
6. Control logic gates
7. Adder and logic circuit connected to the input of AC
Control Logic Gates
The inputs to this circuit come from the two decoders, the I flip-flop, and bits 0 through 11 of IR.
The other inputs to the control logic are: AC bits 0 through 15 to check if AC = 0 and to detect the
sign bit in AC(15); DR bits 0 through 15 to check if DR = 0; and the values of the seven flip-flops.
The outputs of the control logic circuit are:
1. Signals to control the inputs of the nine registers
2. Signals to control the read and write inputs of memory
3, Signals to set, clear, or complement the flip-flops
4. Signals for S2, S1, and S0 to select a register for the bus
5. Signals to control the AC adder and logic circuit
Control of Registers and Memory
The control inputs of the registers are LD (load), INR (increment), and CLR (clear). Suppose that
we want to derive the gate structure associated with the control inputs of AR.
The first three statements specify transfer of information from a register or memory to AR. The
content of the source register or memory is placed on the bus and the content of the bus is
transferred into A R b y enabling its LD control input. The fourth statement clears AR to 0. The last
statement increments AR by 1. The control functions can be combined into three Boolean
Expressions as follows:

Control of Single Flip-flops
Control of Common Bus
· The 16-bit common bus is controlled by the selection inputs S2, S1, and S0• The decimal
number shown with each bus input specifies the equivalent binary number that must be
applied to the selection inputs in order to select the corresponding register. Table specifies
the binary numbers for S2S1S0 that select each register. Each binary number is associated
with a Boolean Variable x1 through x7, corresponding to the gate structure that must be
active in order to select the register or memory for the bus.
· Table 5-7 is recognized as the truth table of a binary encoder. The placement of the
encoder at the inputs of the bus selection logic is shown in Fig.5-18.
· The Boolean functions for the encoder are

In a similar manner we can determine the gate logic for the other registers.
Design of Accumulator Logic
The circuits associated with the AC register. The adder and logic circuit has three sets of inputs.
One set of 16 inputs comes from the outputs of AC. Another set of 16 inputs comes from the data
register DR. A third set of eight inputs comes from the input register INPR. The outputs of the
adder and logic circuit provide the data inputs for the register. In addition, it is necessary to include
logic gates for controlling the LD, INR, and CLR in the register and for controlling the operation of
the adder and logic circuit.

All the statements that change the content of AC.
From this list we can derive the control logic gates and the adder and logic circuit.
Fig: - Circuits associated with AC.
Control of AC Register
The gate structure that controls the LD, INR, and CLR inputs of AC. The gate configuration is
derived from the control functions in the list above. The control function for the clear micro
operation is rB11, where r = D7l ' T3 and B11 = IR (11). The output of the AND gate that generates
this control function is connected to the CLR input of the register. Similarly, the output of the gate
that implements the increment micro operation is connected to the INR input of the register. The
other seven micro operations are generated in the adder and logic circuit and are loaded into AC
at the proper time. The outputs of the gates for each control function is marked with a symbolic
name. These outputs are used in the design of the adder and logic circuit.

Adder and Logic Circuit
· The adder and logic circuit can be subdivided into 16 stages, with each stage
corresponding to one bit of AC.
· Figure shows one such AC register stage (with the OR gates removed). The input is
labelled Ii; and the output AC(i). When the LD input is enabled, the 16 inputs Ii, for i = 0, 1,
2, . . . , 15 are transferred to AC (0-15).
· One stage of the adder and logic circuit consists of seven AND gates, one OR gate and a
full-adder (FA), as shown in Fig

Fig: - One stage of adder and logic circuit.

BASIC COMPUTER ORGANIZATION AND DESIGN

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