Encoding Schemes for Multipliers
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The document discusses various encoding schemes for hardware multiplication, focusing on methods such as traditional multiplication and Booth's algorithm. It highlights the steps involved in partial product generation, reduction, and addition, along with the advantages and disadvantages of each method. The modified Booth algorithm is emphasized for its efficiency in reducing partial products and improving speed, particularly in implementing large multipliers.
Encoding Schemes for Multipliers
- 1. Encoding Schemes for Multipliers Hardware multiplication is performed in the same way multiplication done by hand, first step is to partialized the products are computed then shifted appropriately and summed. Normal multiplication Process: The simplest multiplication operation is to directly calculate the product of two numbers by hand. This procedure can be divided into three steps: 1. Partial product generation 2. Partial product reduction 3. Addition. Let us calculate the product of 2’s complement of two numbers 1101(-3) and 5 (0101), when computing the two binary numbers product we get the result 1 1 0 1 Multiplicand x 0 1 0 1 Multiplier ------------------------ 1 1 1 1 1 1 0 1 PP1 0 0 0 0 0 0 0 PP2 1 1 1 1 0 1 PP3 + 0 0 0 0 0 PP4 ------------------------------------ 1 1 1 1 1 0 0 0 1 = −15 Product Discard this bit From the above we say that 1101 is multiplicand and 0101 is multiplier. The intermediate products are partial products. The final result is product (-15). When this method is processed in hardware, the operation is to take one of the multiplier bits at a time from right to left, multiplying the multiplicand by the single bit of the multiplier and shifting the intermediate product one position to the left of the earlier intermediate products. All the bits of the partial products in each column are added to obtain two bits: sum and carry. Finally, the sum and carry bits in each column have to be summed. The two rows before the product are called sum and carry bits.
- 2. 1 1 0 1 Multiplicand x 0 1 0 1 Multiplier ------------------------ 1 1 1 1 1 1 0 1 PP1 0 0 0 0 0 0 0 PP2 1 1 1 1 0 1 PP3 + 0 0 0 0 0 PP4 ------------------------------------ 0 0 0 0 1 0 0 1 Sum bit 1 1 1 1 0 1 0 0 0 Carry bit ______________________________ 1 1 1 1 1 0 0 0 1 = −15 Product Advantage: In this method the partial product circuit is simple and easy to implement. Therefore, is is suitable for the implementation of small multipliers. Disadvantage: This method is not able to efficiently handle the sign extension and it generates a number of partial products as many as the number of bits of the multiplier, which results in many adders needed so that the area and power consumption increase. This method is not applicable for large multipliers. Booths algorithm:- This algorithm will be slow if there are many partial products because the output must wait until each sum is calculated and performed. As speed is main important aspect while calculating the multiplication. By using the Booths algorithm, we can maximize the speed. In Booths algorithm, speed can be maximized by reducing the partial products to half. The adder circuits in Booth algorithm provide the advantage in maximizing the speed. ALU implements Booth algorithm to multiply binary number. ALU cannot simply multiply binary number as it can do only addition, subtraction and shifting. Working Principle:- Accumulator Multiplier Q Q-1 Multiplicand Action 0000 Step1 0000 0010 0001 0 0 0110 2’s complement of 0110 Shifting
- 3. 1010 0000 Step 2 +1010 1010 1101 Step 3 0001 0000 0 1 0110 2’s complement of 0110 1010 Subtraction shifting 1101 Step 4 +0110 0011 0001 Step 5 0000 1000 1 0 0110 Addition Shifting 0000 Step 6 1100 0 Shifting The operation of Booth encoding consists of two major steps: the first one is to take one bit of the multiplier, and then to decide whether to add the multiplicand according to the current and previous bits of the multiplier. Initially accumulator start with 0000 and we will perform shift that is arthimetic shift then we get first bit of A and the copy of first bit A and for the remaining positions we get from the second position of A. The left bit in A is shifted to Q and bits of Q is placed after it. The bit in Q is shifted to Q-1. Initially Q-1 will be 0. Then we will compare LSB Multiplier, based on this comparision we will perform the addition, subtraction and shifting. Based on this comparision we will perform the action on Accumulator and multiplicand. In the above table we multiplied 0010 and 0110 as an example and the result will be combination of both Accumulator and multiplier i.e 0000 1100(12). Q0 Q-1 Action on A and multiplicand 0 0 Shifting 0 1 Adding 1 0 Subtracting 1 1 Shifting
- 4. Modified Booth Algorithm: The encoding method is widely used to generate the partial products for the implementation of large multipliers. It adopts parallel encoding scheme. Modified Booth Algorithm can be realized by using circuits consists of Booth Encoder and multiplier array of partial product generator (Multiplexer) and adders. Booth Encoder: It implements Booth Algorithm encoding. Basic Principle:- The basic principle in modified Booth Algorithm is, consider X and Y are two fixed-point two’s complement numbers, where X is multiplier and Y is multiplicand both having same n bits. X can be represented as X = −𝑋 𝑛−12 𝑛−1 + ∑ 𝑋𝑖2𝑖𝑛−2 𝑖=0 = ∑ (−𝑋2𝑖−1 + 𝑋2𝑖 + 𝑋2𝑖−1). 22𝑖𝑛/2−1 𝑖=0 = ∑ (−2𝑋2𝑖+1 + 𝑋2𝑖 + 𝑋2𝑖−1). 4𝑖𝑛/2−1 𝑖=0 By multiplying the X with Y, results XY = ∑ (−2𝑋2𝑖+1 + 𝑋2𝑖 + 𝑋2𝑖−1). 4𝑖𝑛/2−1 𝑖=0 . 𝑌 From the above equation we portioned the bits of multipliers into substrings of 3 adjacent bits and each substring consists of(𝑋2𝑖+1, 𝑋2𝑖 , 𝑋2𝑖−1), each corresponds to the value {−2, −1, 0, +1, +2} The grouping of bits of multiplies can be done as 1 1 0 1 1 0 1 0 1 1
- 5. 𝑋2𝑖+1 𝑋2𝑖 𝑋2𝑖−1 Possible values 0 0 0 0 0 0 1 +1 0 1 0 +1 0 1 1 +2 1 0 0 -2 1 0 1 -1 1 1 0 -1 1 1 1 0 Each three adjacent bits of the multiplier can generate a single encoding digit having the possible values {−2, −1, 0, +1, +2}. For the n × n multiplication, the number of bits for the multiplier X is n, using the modified Booth encoding n/2 partial products are produced. Multiplication: The partial product should be shifted two positions to the left of the partial product due to the is multiplied by Add a Zero to get 3 bit as a group 1 1 0 1 0 +1 -1 0 1 0 1 +1Y 1 0 1 1 -1Y ------------------------------------------- 1 1 0 0 0 1 (-15) The operation is summerized as Possible values Operation on Y 0 0*Y: Y => 0 => Product is zero +1 +1*Y: Y => Product (Y is the product) +2 +2*Y: One Shift Y to the left => Product
- 6. Architecture: Booth Multiplier Multiplier cell -1 -1*Y: Invert Y and add 1 to the LSB of Y => Product -2 -2*Y: One Shift to the left for Y, then inverted Y & added 1 to the LSB
- 7. Modified Booth Algorithm can be realized by using circuits consists of Booth Encoder and multiplier array of partial product generator (Multiplexer) and adders. Booth Encoder: On the left-hand side are the Booth encoders, one for each partial product. They each have three bits of as input (with “0” to the right of the LSB).They are also responsible for decoding and propagating the sign extension logic to the next encoder. The array cells then generate the appropriate bit and add it to the accumulated sum with their internal adders. In two’s complement format inverting a number consists of flipping all bits and adding one. The “ADD” cell generates the 1 if required. Multiplier cell: The cell consists of two components, a multiplexer to generate the partial product bit (PP-MUX) and a full adder (FA) or half adder (HA) to add this bit with the previous sum. The multiplier cell represents one bit in a partial product and is responsible for: 1) Generating a bit of the correct partial product in response to the signals from the Booth encoder; 2) Adding this bit to the cumulative sum propagated from the row above. Adders: In Booth Algorithm we use Half Adder and Full Adders along with the Multiplexer. The FA is the most critical circuit in the multiplier as it ultimately determines the speed and power dissipation of the array. The Boolean Expression for Half Adder is 𝑆0 = A XOR B 𝐶0 = AB The Boolean Expression for Full Adder is 𝑆0 = A XOR B XOR 𝐶𝑖𝑛 𝐶0 = A (~B) 𝐶𝑖𝑛+ ÃB𝐶𝑖𝑛+AB. Ramavathu Sakru Naik, NIT ROURKELA, SILICON MENTOR.