Cache memory
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Cache memory is a type of fast memory located between the CPU and main memory that stores recently accessed data. It was developed in the 1970s by Maurice Wilkes to address the issue of main memory access times increasing as memory sizes grew. Modern CPUs typically have three levels of cache - an instruction cache to speed up fetching of executable instructions, a data cache to speed up data fetching and storing, and a translation lookaside buffer to speed up virtual-to-physical address translation for both instructions and data. Cache is organized hierarchically and transfers data between memory and cache in fixed-size blocks called cache lines.
Cache memory
- 3. WHAT WE NEED? ļ® What we would prefer in our Computer Memory: ļ Fast ļ Large ļ Cheap However, Very Fast memory = Very expensive memory Since we need large capacity ( today multi- gigabyte memories) we need to build a system that is the best compromise to keep the total $$ reasonable.
- 4. WHY WE NEED CACHE MEMORY? Due to increasing the size of main memory day by day the systemās speed make reduce . So, Mr. Maurice Wilkes developed a memory (which is communicating between processor and main memory) in 1970ās. A cache used by (CPU) of a computer to reduce the average time to access data from the main memory.
- 6. TYPES OF CACHE MEMORY Most modern desktop and server CPUs have at least three independent caches: An instruction cache: To speed up executable instruction fetch. A data cache: To speed up data fetch and store data. A translation look side buffer (TLB): To speed up virtual-to-physical address translation for both executable instructions and data.
- 7. ORGANIZATION OF CACHE The data cache is usually organized as a hierarchy of more cache levels (L1, L2, etc.; see also multi- level caches below)
- 8. TRANSFORMATION OF CACHE Data is transferred between memory and cache in blocks of fixed size, called cache lines. When a cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location (now called a tag). Note: Cache memory width is equal to the data bus width.