Can overview
- 1. 1 ¥ Overview of CAN ÐWhat is CAN? ÐWhy CAN? ¥ CAN Protocol: ÐCAN 2.0A & CAN 2.0B ÐBasics Concepts & Definitions ÐIdentifiers & Arbitration ÐRobustness & Flexibility ÐMessage Formats ÐErrors at Message and Bit Level ÐError Handling and Confinement ¥ CAN Implementations ÐThe Requirements of a CAN Controller ÐFull CAN vs. Basic CAN Controllers ÐMessage Buffering & Filtering ÐEffective, Low Cost CAN Receive Structures ¥ Motorola CAN Modules ¥ Summary CAN Technical OverviewCAN Technical Overview AgendaAgenda
- 2. 2 Overview of CANOverview of CAN
- 3. 3 ÒWhat is CAN?!ÓÒWhat is CAN?!Ó ¥ CAN (Controller Area Network) is a multiplexed serial communication channel which data is transferred among distributed electronic module; very similar to SPI or SCI, although more complex. -MultiMaster, MultiCast Protocol without Routing.
- 4. 4 Engine 683xx Transmission HC08AZx / HC12 Throttle HC08AZx ABS HC12 Central Module HC12 / 683xx Door HC08AZx Door HC08AZx Sunroof HC08AZx Airbag HC08AZx Driver Seat HC08AZx Radio HC08AZx Steering HC08AZx Dashboard HC08AZx Climate HC08AZx Rear Lights HC08AZx Power Train: >250k bit/sec CAN Car Body >125k bit/sec CAN Typical CAN NetworkTypical CAN Network
- 5. 5 Application Layer Logic Link Control Data Transfer Remote Data Request Message Filtering Recovery Management & Overload Notification Medium Access Control Framing & Arbitration Error Checking & Error Flags Fault Confinement Bit Timing Layer 2: Data Link Layer Physical Layer CAN 2.0CAN 2.0 Structure of a CAN NodeStructure of a CAN Node • ISO 7498 defines the communication’s standard Open Systems Interconnection (OSI). - This standard defines seven independent layers of a protocol stack. • CAN Specification, ISO 11898, deals with only the Physical & Data Link Layers for a CAN network. Layer 7: Layer 1: Presentation LayerLayer 6: Session LayerLayer 5: Transport LayerLayer 4: Network LayerLayer 3:
- 6. 6 CAN 2.0A: 11 Bit Identifier M68HC05X Family • Used by vast majority of current applications. • Greater message throughput and improved latency times • Less silicon overhead ! CAN 2.0B 29 Bit Identifier HC08 / HC11 + MSCAN • Originally defined for USA Passenger Cars but now their Taskforce decree that it is not necessary. • Allows more information in message but requires more bus bandwidth • More silicon cost and less efficient use of bus ! CAN 2.0A vs CAN 2.0BCAN 2.0A vs CAN 2.0B
- 7. 7 CAN 2.0A/B SAE J1850 BEAN Bit Encoding NRZ PWM or VPW NRZ Bus Wire Medium Single Single (10.4Kbps) Single or Dual or Dual (41.0Kbps) Data Rate 1Mbps 10.4 Kbps VPW or 10kbps 41.7 Kbps PWM # of SOF Bits 1bit unique symbol 1 bit # of Identifier Bits 11/29 bits 8 to 24 bits 12 bits Data Length Code 4 bits none 4 bits Message Length Field 0 to 24 bits 0 to 24 bits 1 to 88 CRC Field 15 bits 8 bits 8 bits ACK Field 2 bits none 2 bits End of Frame 7 bits unique symbol 6 bits IFR ACK a) 1 byte from 1 receiver or- b) Multiple bytes from multiple receivers. c) Data bytes, with or without CRC, from a single receiver. EOF 1 bit 1 bit 1 bit CAN vs Other ProtocolsCAN vs Other Protocols
- 8. 8 ¥ Widely Accepted Standard Ð ÒTHE STANDARDÓ in the automotive industry in Europe. Ð Gaining acceptance in the US. ¥ Robust Ð Handles extreme conditions well. Ð Simple to configure. Ð Good error detection capabilities. Ð Excellent two-wire fault tolerance capabilities: È Either of the two wires in the bus is broken. È Either of the two wires are shorted to power, to ground, or together. ¥ ÔLots of software and hardware support available Ð Application layer and driver software available. Ð CAN Bus Analyzer/development tools. Ð CAN USER group conferences. ÒWhy CAN?!ÓÒWhy CAN?!Ó
- 9. 9 Technical OverviewTechnical Overview IdentifiersIdentifiers ArbitrationArbitration CAN 2.0A & 2.0B Message FramesCAN 2.0A & 2.0B Message Frames Network Flexibility & ExpanisionNetwork Flexibility & Expanision ResynchronizationResynchronization
- 10. 10 ¥ Labels the content (type) of a message. ¥ Performs acceptance test of messages. ¥ Arbitrates & determines the priority of the message. IdentifiersIdentifiers
- 11. 11 ¥ Carrier Sense, Multiple Access with Collision Detect (CSMA/CD) Ð Method used to arbitrate and determine the priority of messages. Ð Uses enhanced capability of non-destructive bitwise arbitration to provide collision resolution. ArbitrationArbitration
- 12. 12 BitwiseBitwise ArbitrationArbitration Node 0 Node 1 Node 2 Time Logic Level ¥ Any potential bus conflicts are resolved by bitwise arbitration Ð Dominant state (logic 0) has precedence over a recessive state (logic 1). È Competition for the bus is won by node 2 . È Nodes 0 and 1 automatically become receivers of the message È Nodes 0 and 1 will re-transmit their messages when the bus becomes available again.
- 13. 13 Local Priority ConceptLocal Priority Concept ¥ Each transmit buffer hold an 8-bit priority register. ¥ Allows flexible priority schemes. Ð Fixed Priority for each buffer. Ð Map a CAN ID to a priority. Ð First in, first out. Ð Back - to - Back transmission of same ID. Ð Situation priority.
- 14. 14 • CAN 2.0A (Standard Format) - 11 bit message identifier - Transmits and receives only standard format messages. CAN 2.0A Message FrameCAN 2.0A Message Frame SOF 11 bit Identifier DLC 15 BITSData 0 - 8 Bytes CRC ACK EOF INT Bus Idle RTR r1 r0 Delimiter Slot Delimiter Data Field Control Field Arbitration Field Bus Idle Message Frame
- 15. 15 • CAN 2.0B (Extended Format) - Capable of receiving CAN 2.0A messages. - 29 bit message identifier. 11 bits for a CAN 2.0A message + 18 bits for a CAN 2.0B message. CAN 2.0B Message FrameCAN 2.0B Message Frame SOF 11 bit Identifier DLC 15 Bits Data 0 - 8 Bytes CRC ACK EOF INT Bus Idle SRR r1 Delimiter Slot Delimiter Data FieldControl FieldArbitration Field Bus Idle Message Frame IDE 18 bit Identifier r0
- 16. 16 ¥ High degree of flexibility for system configuration. Ð Easy to add new (purely) receiving nodes. Ð Measurements needed by several controllers can be transmitted via the bus. Network Flexibility and ExpansionNetwork Flexibility and Expansion
- 17. 17 SYNC Propagation Phase Seg 1 Phase Seg 2 Bit time segments (BT) SYNC TSEG1 TSEG 2 SJWSJW Sample Point CAN Definition Implementation CAN ResynchronizationCAN Resynchronization ¥Sync-Seg : Used to synchronize the nodes on the bus and the start of bit transition. ¥Prop-Seg : A period of time that is used to compensate for physical delay times within the network. ¥Phase-Seg1: A buffer segment that may be lengthened during resynchronization to compensate for oscillator drift and positive phase differences between the oscillators of the transmitting and receiving node(s). ¥Phase-Seg2: A buffer segment that may be shortened during resynchronization to compensate for negative phase errors and oscillator drift. ¥SJW : 1bit time, synchronization jump width (SJW) is not to be exceeded.
- 18. 18 Technical OverviewTechnical Overview • Five Error Detection Mechanisms• Five Error Detection Mechanisms Error Flags, Confinement, & CountsError Flags, Confinement, & Counts Error Active ModeError Active Mode Bus-Off ModeBus-Off Mode Error LevelsError Levels Overload FrameOverload Frame
- 19. 19 ¥ CAN implements five error detection mechanisms. Ð Three at the message level È Cyclic Redundancy Checks (CRC) È Frame Checks È Acknowledgment Error Checks Ð Two at the bit level È Bit Monitoring È Bit Stuffing Error DetectionError Detection
- 20. 20 ¥CRC Errors (Message Level) ÐThe 15 bit CRC is computed by the transmitter and based on the message content. Ð All receivers that accept the message, recalculates the CRC and compares against received CRC. Ð If the two values do not match a CRC error is flagged. Cyclic Redundancy Checks (CRC)Cyclic Redundancy Checks (CRC)
- 21. 21 ¥ If a receiver detects an invalid bit in one of these positions, a Form Error (or Format Error) will be flagged: Ð CRC Delimiter Ð ACK Delimiter Ð End of Frame Bit Field Ð Interframe Space (the 3 bit INTermission field and a possible Bus Idle time). Frame CheckFrame Check Message LevelMessage Level
- 22. 22 ¥ Each receiving node writes a dominant bit into the ACK slot ¥ If a transmitter determines that a message has not been ACKnowledged then an ACK Error is flagged. ¥ ACK errors may occur because of transmission errors because the ACK field has been corrupted or there is no operational receivers. ACK Error CheckACK Error Check Message LevelMessage Level
- 23. 23 ¥ Each bit level (dominant or recessive) on the bus is monitored by the transmitting node. Ð Bit monitoring is not performed during arbitration or on the ACK Slot. Bit MonitoringBit Monitoring Bit LevelBit Level
- 24. 24 ¥ Bit stuffing is used to guarantee enough edges in the NRZ bit stream to maintain synchronization. Ð After five identical and consecutive bit levels have been transmitted, the transmitter will automatically inject (stuff) a bit of the opposite polarity into the bit stream. Ð Receivers of the message will automatically delete (de- stuff) such bits. Ð If any node detects six consecutive bits of the same level, a stuff error is flagged. Bit StuffingBit Stuffing Bit LevelBit Level
- 25. 25 ¥ If an error is detected by at least one node Ð The node that detects the error will immediately abort the transmission by sending an Error Flag. ¥ An Error Flag consists of six dominant bits. Ð This violates the bit stuffing rule and all other nodes respond by also transmitting Error Flags. Error FlagError Flag
- 26. 26 ¥ A method for discriminating between temporary errors and permanent failures . Ð Temporary errors may be caused by external conditions, voltage spikes, etc. Ð Permanent failures may be caused by bad connections, faulty cables, defective transmitters or receivers, or long lasting external disturbances. Error ConfinementError Confinement
- 27. 27 ¥ The error flags are counted and stored. Ð Receive errors are given a weighting of 1. Ð Transmit errors are given a weighting of 8. ¥ Transmitting node errors can be quickly detected. Error CountsError Counts
- 28. 28 ¥ If an error count in either the transmit or receive register is greater than zero, the node enters Error Active mode. Ð Error Active nodes are still fully functional, but are in an alert condition. Ð Subsequent good messages decrement the Error Count registers by a count of 1. Ð If no further errors are detected, and both Error Counts go back to zero, an Error Active node returns to Normal mode. Error Active ModeError Active Mode
- 29. 29 ¥ If the Error Count in either the transmit or receive registers exceeds 255, the node will take itself off-line by going into ÒBus-Off modeÓ. Ð Permanently faulty nodes will cease to be active on the bus. ¥ Nodes in the Bus Off state can go back to Error Active mode Ð 128 occurrences of 11 consecutive recessive bits on the bus need to occur. Bus-Off ModeBus-Off Mode
- 30. 30 ¥ The alarm levels are defined by CAN 2.0 ¥ MSCAN implements a level sensitive flag for each error condition - Error Active Mode.............................. 001 to 127 - Warning............................................... 096 - Error Passive Mode............................ 128 to 254 - BusOff Mode....................................... > 255 Error Flag LevelsError Flag Levels (MSCAN HC08/HC12)(MSCAN HC08/HC12)
- 31. 31 ¥ If a CAN node receives messages faster than it can process the messages, then the CAN module will signal an overload condition and then send an overload interrupt to the CPU. ¥ Causes of an Overload Frame Ð A receiver node needs more time to process current data before receiving the next Message Frame . Ð The detection of a dominant bit during the INTermission field Overload FrameOverload Frame
- 32. 32 Technical OverviewTechnical Overview CAN Controller RequirementsCAN Controller Requirements FullCAN vs BasicCANFullCAN vs BasicCAN BasicCAN Receive StructuresBasicCAN Receive Structures
- 33. 33 ¥ Simple user interface to CPU ¥ Message filtering and buffering ¥ Protocol handling ¥ Physical layer interface (1) CPU Interface (3) CAN Protocol Layer (2) Message filtering + buffering Control + status (4) Physical interface H.W. Errors CANH CANL IRQ IRQ CAN bus Microcontroller Requirements of a CAN ControllerRequirements of a CAN Controller
- 34. 34 ¥ FullCAN Controller: Ð Typically 16 message buffers, sometimes more. Ð Global and Dedicated Message Filtering Masks Ð Dedicated H/W for Reducing CPU Workload Ð More Silicon => more cost È e.g. Powertrain ¥ BasicCAN Controller: Ð 1 or 2 Tx and Rx buffers Ð Minimal Filtering Ð More Software Intervention Ð Low cost È e.g. Car Body More cost, less CPU overhead (per bit per sec) Less cost, more CPU overhead (per bit per sec) FullCAN vs BasicCANFullCAN vs BasicCAN
- 35. 35 Advantages: ¥ LESS software intervention since data storage already assigned ¥ LESS time critical Disadvantages: ¥ Loses efficiency if > 14 IDÕs Ð Leads to worst case interrupt loading ¥ More silicon required than Basic CAN => Higher cost Transmit 0 Rx 14/ Tx 1 Rx 2 / Tx 13 Rx 1 / Tx 14 Receive 0 CPU Interface ID Filter 14 ID Filter 2 ID Filter 1 GLOBAL filter Protocol Layer: - Internal arbitration - Error handling - Remote frames - etc A FullCAN ControllerA FullCAN Controller
- 36. 36 Advantages: ¥ Low Cost ¥ Not a fixed link between a receive buffer and a message identifier Disadvantages: ¥ Software intensive ¥ More likely to get an overflow due to minimal receive buffers Analyze Identifier CAN Data Storage Assign RAM area Move 8 Data bytes to RAM area Service CAN IRQ CAN Receive BufferCAN Protocol Layer BasicCANBasicCAN Method 1, Rx StructureMethod 1, Rx Structure
- 37. 37 Advantages: ¥ Area of data storage is assigned in Hardware depending on ID ¥ Allows some flexibility: Less ID masks leaves more general purpose RAM / Stack space, important for high level languages Disadvantages: ¥ MORE Time critical, Only allows a certain amount of filtering is possible, dependent on bus speed ¥ MORE silicon area CAN protocol layer Temp Data Buffer Received ID Test ID Mask Compare Transmit Control Tx, Priority Receive MessageReceive MessageReceive Message Identifier Identifier Identifier Store Received Message Identifier Mask RAM (e.g. NEC ÒMCANÓ) 1 2 3 0 1 2 3 0 ÒhitÓ scored BasicCANBasicCAN Method 2, Rx StructureMethod 2, Rx Structure
- 38. 38 ¥ Full CAN is not appropriate for Car Body for cost reasons: Ð The RAM required for message buffering and filtering is very silicon intensive and expensive ¥ A Full CAN receiver can have worst case Rx interrupt situations similar to Basic CAN receivers. Ð A FullCAN controller with less receive buffers than there are message identifiers experiences increased loading on the globally filtered Rx buffer È This is THE SAME situation as on a Basic CAN controller. Summary of CAN ImplementationsSummary of CAN Implementations
- 40. 40 1) MCAN (on HC05X family) 2) MSCAN08 3) MSCAN12 4) TouCAN FULL CAN: More cost, less CPU overhead (per bit per sec) BASIC CAN: Less cost, more CPU overhead (per bit per sec) Motorola CAN ImplementationsMotorola CAN Implementations
- 41. 41 CAN Interface management logic Transmit buffer Receive buffer 0 Receive buffer 1 Bit timing logic logic Bit stream processor Error management logic Microprocessor Protocol / Bus related logic bus line CPU Interface Transceiver related logic Phys Interface ¥ 11 bit Identifier acceptance filter ¥ 2 Rx and 1 Tx buffers MCAN HC05X FamilyMCAN HC05X Family
- 42. 42 Rx Buffer Rx Buffer CAN Protocol Controller HC08 CPU Interface (Memory Mapped I/O) 1 x 32 bits or 2 x 16 bits or 4 x 8 bits Global Identifier Filtering: Internal Priority Scheduling Tx Buffer 3 Priority Register Tx Buffer 2 Priority Register Tx Buffer Priority Register MSCAN 08 Buffer and Filter SchemeMSCAN 08 Buffer and Filter Scheme
- 43. 43 "Hit" "Hit" 3 FILTER MODES Single Filter Mode Double Filter Mode Quadruple Filter Mode Mask 0-3 Mask 0-1 Mask 2-3 "Hit" "Hit" "Hit" "Hit" "Hit" "Hit" "Hit" "Hit" "Hit" Mask 0 Mask 1 Mask 2 Mask 3 ¥ ID Accepted ¥ CPU interrupted MS08CAN Filter SchemeMS08CAN Filter Scheme
- 44. 44 HC05 - MCAN One 11-Bit Acceptance Filter HC08- MSCAN Four 8-Bit GLOBAL Acceptance Filter Assumptions: 4MHz Bus Frequency All Messages have to be accepted 80 % Bus load average of 4 data Bytes / message (1296 µs/message with no stuff bit) 80% Bus load --> 617 messages / s Receive Routine: 800 cycles = 200 µs Total Receive Interrupt Time per s: 617 * 200 µs = 123 ms CPU load ONLY for 4MHz HC05 MSCAN Receive: 12.3% Assumptions: 8MHz Bus Frequency Only required messages accepted (70%) 80 % Bus load average of 4 data Bytes / message (1296 µs/message with no stuff bit) CPU load ONLY for 8MHz HC08 MSCAN Receive: 3.5% 80% Bus load, 70% accepted messages --> 431 messages / s Receive Routine: 650 cycles = 81.25 µs Total Receive Interrupt Time per s: 431 * 81.25 µs = 35 ms Rx Interrupt CPU LoadRx Interrupt CPU Load HC05 vs HC08HC05 vs HC08
- 45. 45 3 FILTER MODES Double Filter Mode: 2 x 32 bits Quadruple Filter Mode: 4 x 16 bits Octuple Filter Mode: 8 x 8 bits Mask 0-3 Mask 4-7 Mask 0-1 Mask 2-3 Mask 4-5 Mask 6-7 Mask 0 Mask 1 Mask 2 Mask 3 Mask 4 Mask 5 Mask 6 Mask 7ID Accepted ¥ DOUBLE the number of filters of MSCAN08 ¥ Further reduces CPU interrupt loading ¥ Otherwise identical to MSCAN08 MSCAN12 Filter SchemeMSCAN12 Filter Scheme
- 46. 46 HC12- MSCAN12 Eight 8-Bit GLOBAL Acceptance Filter Assumptions: 8MHz Bus Frequency Only required messages accepted (50%) 80 % Bus load average of 4 data Bytes / message (1296 µs/message with no stuff bit) CPU load ONLY for 8MHz HC12 MSCAN12 Receive: 1.15% 80% Bus load, 50% accepted messages --> 308 messages / s Receive Routine: 300 cycles = 37.5 µs Total Receive Interrupt Time per s: 308 * 37.5 µs = 11.5 ms HC08- MSCAN08 Four 8-Bit GLOBAL Acceptance Filter Assumptions: 8MHz Bus Frequency Only required messages accepted (70%) 80 % Bus load average of 4 data Bytes / message (1296 µs/message with no stuff bit) CPU load ONLY for 8MHz HC08 MSCAN Receive: 3.5% 80% Bus load, 70% accepted messages --> 431 messages / s Receive Routine: 650 cycles = 81.25 µs Total Receive Interrupt Time per s: 431 * 81.25 µs = 35 ms Rx Interrupt CPU LoadRx Interrupt CPU Load HC08 vs HC12HC08 vs HC12
- 47. 47 ¥ Implementation of the CAN protocol - Version CAN 2.0A/B Ð Standard and extended data frames Ð 0 - 8 bytes data length Ð programmable bit rate up to 1MBit/s ¥ Double buffered receive storage system ¥ Triple buffered transmit storage scheme with internal prioritization using Òlocal priorityÓ concept ¥ Flexible maskable identifier filters ¥ Programmable wake-up functionality with integrated low-pass filter ¥ Programmable loop-back mode supports selftest ¥ Separate signaling and interrupt capabilities for all CAN receiver and transmitter error states ¥ Programmable clock source (PLL or oscillator) ¥ Programmable link to on-chip timer module for time stamping or network synchronization ¥ Low power sleep mode MSCAN Module FeaturesMSCAN Module Features
- 48. 48 16 Rx/Tx Message Buffers CONTROL Receiver Transmitter SLAVE BUS INTERFACE UNIT INTER-MODULE BUS (IMB) Tx0 Tx1 Rx0 Rx1 ¥ Full implementation of the CAN protocol - Version 2.0B ¥ 16 Rx/Tx Message Buffers of up to 8 bytes Data Length ¥ Programmable Bit Rate up to 1 Mbit/sec ¥ Programmable Global Receive identifier mask ¥ 2 Dedicated Receive identifier masks ¥ Programmable transmit-first scheme ¥ Time stamping to allow network timing synchronization ¥ Low power ÒsleepÓ mode, with programmable Òwake upÓ ¥ Motorola IMB-Family Modular Architecture The High PerformanceThe High Performance TouCAN ModuleTouCAN Module
- 49. 49 68HC908EB8 8K FLASH 32QFP 68HC908EB8 8K ROM HC08 AUTOMOTIVE PORTFOLIOHC08 AUTOMOTIVE PORTFOLIO 68HC08AB60 60K ROM 68HC08AB48 48K ROM 68HC08AB32 32KROM 68HC08AB24 24K ROM 68HC08AB16 16K ROM 68HC08AB0 EXT. MEMORY 100TQFP 68HC908AZ/AS60 60K FLASH 68HC908AZ/AS32 32K FLASH MSCAN/J1850 44/64QFP/52PLCC 68HC08AZ60 64QFP 60K ROM 68HC08AZ48 64QFP 48K ROM 68HC08AZ32 44/64QFP 32K ROM 68HC08AZ24 44/64QFP 24K ROM 68HC08AZ16 44/64QFP 16K ROM 68HC08AZ0 EXT. MEMORY MSCAN 100TQFP 68HC08AS32 32K ROM 68HC08AS20 20K ROM J1850 64QFP/52PLCC FLASH 08AT CAN 08AZ J1850 08AS General Purpose 08AB