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R.M.K. COLLEGE OF ENGINEERING
AND TECHNOLOGY
SMALL SIGNAL ANALYSIS OF CASCODE AND
CASCADE AMPLIFIER
Dr.N.G.Praveena
Associate Professor/ECE
Multistage Amplifiers
 Increase the overall small-signal voltage gain
Cascode Amplifiers
 VOLTAGE GAIN
AV=
𝑽𝑶
𝑽𝑺
-----(1)
From the input circuit,
𝐕𝛑𝟏=VS
From the output circuit,
𝐕𝐨= - 𝐠𝐦𝟐𝐕𝛑𝟐 (𝑹𝑪 𝑹𝑳) -----(2)
Apply KCL to the E2 of the small signal equivalent circuit,
𝐠𝐦𝟏𝐕𝛑𝟏 =
𝐕𝛑𝟐
𝐫𝛑𝟐
+ 𝐠𝐦𝟐𝐕𝛑𝟐
𝐠𝐦𝟏𝐕𝐬 =
𝐕𝛑𝟐
𝐫𝛑𝟐
+ 𝐠𝐦𝟐𝐕𝛑𝟐 (∴ 𝐕𝛑𝟏=VS)
𝐠𝐦𝟏𝐕𝐬 =
𝐕𝛑𝟐
+𝐠𝐦𝟐
𝐕𝛑𝟐𝐫𝛑𝟐
𝐫𝛑𝟐
(∴ 𝐠𝐦𝟐𝐕𝛑𝟐=β2)
𝒈𝒎𝟏𝑽𝒔 =
𝐕𝛑𝟐(1+β2)
𝐫𝛑𝟐
𝐕𝛑2=
𝐫𝛑𝟐
(𝟏+𝛃𝟐
)
𝐠𝐦𝟏𝐕𝐒 −−−−−(3)
Sub (3) in (2)
𝑽𝟎 = -𝐠𝐦𝟐
𝒓𝝅𝟐
(𝟏+𝜷𝟐
)
𝒈𝒎𝟏𝑽𝑺(𝑹𝒄 𝑹𝑳) AV=
𝑽𝑶
𝑽𝑺
= -𝒈𝒎𝟏𝐠𝐦𝟐
𝒓𝝅𝟐
(𝟏+𝜷𝟐
)
(𝐑𝐜 𝑹𝑳) (using 1)
 Input Resistance (Ri)
𝑹𝒊𝟐 =𝐑𝟐 𝐑𝟑 𝐫𝛑𝟏
 Output Resistance
VS is set to zero
𝑽𝝅𝟏=0 , gm1𝑽𝝅𝟏=0 , 𝑽𝝅𝟐 = 𝟎 , 𝒈𝒎𝟐𝑽𝝅𝟐 = 𝟎
R0 = 𝐑𝐂 𝐑𝐋
Cascade Amplifiers
Analysis of Stage 2
 Input Resistance (Ri2)
𝑹𝒊𝟐 = 𝒓𝝅𝟐
 Voltage Gain(𝑨𝑽𝟐 )
𝑨𝑽𝟐 =
𝑽𝑶
𝑽𝝅𝟐
The output voltage at stage 2,
𝑽𝑶= 𝐠𝐦𝟐𝑽𝝅𝟐 (𝑹𝑪 𝑹𝑳)
∴ 𝑨𝑽𝟐 =
𝑽𝑶
𝑽𝝅𝟐
= 𝐠𝐦𝟐 (𝑹𝑪 𝑹𝑳)−−−−(1)
Analysis of Stage 1
 VOLTAGE GAIN(𝑨𝑽𝟏 )
𝑨𝑽𝟏 =
𝑽π𝟐
𝑽𝝅𝟏
The output voltage at stage 1,
𝑽𝝅𝟐 = 𝒈𝒎𝟏𝑽𝝅𝟏 𝑹𝑪𝟏 𝑹𝒊𝟐
𝑨𝑽𝟏 =
𝑽π𝟐
𝑽𝝅𝟏
= 𝒈𝒎𝟏 𝑹𝑪𝟏 𝑹𝒊𝟐 ------(2)
 OVERALL VOLTAGE GAIN
𝑨𝑽 =
𝑽𝟎
𝑽𝑺
=
𝑽𝟎
𝑽𝝅𝟐
×
𝑽𝝅𝟐
𝑽𝝅𝟏
×
𝑽𝝅𝟏
𝑽𝑺
-----(3)
Apply voltage divider rule at the input, we get
𝑽𝝅𝟏=
𝑹𝒊𝟏
𝑹𝒊𝟏
+𝑹𝑺
𝑽𝑺
𝑽π𝟏
𝑽𝑺
=
𝑹𝒊𝟏
𝑹𝒊𝟏
+𝑹𝑺
-------(4)
Sub equation (1),(2) and (4) in equation (3),
𝑨𝑽 = 𝒈𝒎𝟐 𝑹𝑪𝟐 𝑹𝑳 𝒈𝒎𝟏 𝑹𝑪𝟏 𝑹𝒊𝟐 .
𝑹𝒊𝟏
𝑹𝒊𝟏
+𝑹𝑺
𝑨𝑽 = gm1𝐠𝒎𝟐 𝑹𝑪𝟐 𝑹𝑳 𝑹𝑪𝟏 𝑹𝒊𝟐 .
𝑹𝒊𝟏
𝑹𝒊𝟏
+𝑹𝑺
 Input resistance
𝐑𝐢𝟏 = 𝐑𝟏 𝐑𝟐 𝐫𝛑𝟏
 Output Resistance
VS is set to zero
𝑽𝝅𝟏=0 gm1𝑽𝝅𝟏=0 𝑽𝝅𝟐 = 𝟎 𝒈𝒎𝟐𝑽𝝅𝟐 = 𝟎
R0 = RC2

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Cascade and cascode amplifiers

  • 1. R.M.K. COLLEGE OF ENGINEERING AND TECHNOLOGY SMALL SIGNAL ANALYSIS OF CASCODE AND CASCADE AMPLIFIER Dr.N.G.Praveena Associate Professor/ECE
  • 2. Multistage Amplifiers  Increase the overall small-signal voltage gain
  • 4.  VOLTAGE GAIN AV= 𝑽𝑶 𝑽𝑺 -----(1) From the input circuit, 𝐕𝛑𝟏=VS From the output circuit, 𝐕𝐨= - 𝐠𝐦𝟐𝐕𝛑𝟐 (𝑹𝑪 𝑹𝑳) -----(2) Apply KCL to the E2 of the small signal equivalent circuit, 𝐠𝐦𝟏𝐕𝛑𝟏 = 𝐕𝛑𝟐 𝐫𝛑𝟐 + 𝐠𝐦𝟐𝐕𝛑𝟐 𝐠𝐦𝟏𝐕𝐬 = 𝐕𝛑𝟐 𝐫𝛑𝟐 + 𝐠𝐦𝟐𝐕𝛑𝟐 (∴ 𝐕𝛑𝟏=VS) 𝐠𝐦𝟏𝐕𝐬 = 𝐕𝛑𝟐 +𝐠𝐦𝟐 𝐕𝛑𝟐𝐫𝛑𝟐 𝐫𝛑𝟐 (∴ 𝐠𝐦𝟐𝐕𝛑𝟐=β2) 𝒈𝒎𝟏𝑽𝒔 = 𝐕𝛑𝟐(1+β2) 𝐫𝛑𝟐 𝐕𝛑2= 𝐫𝛑𝟐 (𝟏+𝛃𝟐 ) 𝐠𝐦𝟏𝐕𝐒 −−−−−(3) Sub (3) in (2) 𝑽𝟎 = -𝐠𝐦𝟐 𝒓𝝅𝟐 (𝟏+𝜷𝟐 ) 𝒈𝒎𝟏𝑽𝑺(𝑹𝒄 𝑹𝑳) AV= 𝑽𝑶 𝑽𝑺 = -𝒈𝒎𝟏𝐠𝐦𝟐 𝒓𝝅𝟐 (𝟏+𝜷𝟐 ) (𝐑𝐜 𝑹𝑳) (using 1)
  • 5.  Input Resistance (Ri) 𝑹𝒊𝟐 =𝐑𝟐 𝐑𝟑 𝐫𝛑𝟏  Output Resistance VS is set to zero 𝑽𝝅𝟏=0 , gm1𝑽𝝅𝟏=0 , 𝑽𝝅𝟐 = 𝟎 , 𝒈𝒎𝟐𝑽𝝅𝟐 = 𝟎 R0 = 𝐑𝐂 𝐑𝐋
  • 7. Analysis of Stage 2  Input Resistance (Ri2) 𝑹𝒊𝟐 = 𝒓𝝅𝟐  Voltage Gain(𝑨𝑽𝟐 ) 𝑨𝑽𝟐 = 𝑽𝑶 𝑽𝝅𝟐 The output voltage at stage 2, 𝑽𝑶= 𝐠𝐦𝟐𝑽𝝅𝟐 (𝑹𝑪 𝑹𝑳) ∴ 𝑨𝑽𝟐 = 𝑽𝑶 𝑽𝝅𝟐 = 𝐠𝐦𝟐 (𝑹𝑪 𝑹𝑳)−−−−(1)
  • 8. Analysis of Stage 1  VOLTAGE GAIN(𝑨𝑽𝟏 ) 𝑨𝑽𝟏 = 𝑽π𝟐 𝑽𝝅𝟏 The output voltage at stage 1, 𝑽𝝅𝟐 = 𝒈𝒎𝟏𝑽𝝅𝟏 𝑹𝑪𝟏 𝑹𝒊𝟐 𝑨𝑽𝟏 = 𝑽π𝟐 𝑽𝝅𝟏 = 𝒈𝒎𝟏 𝑹𝑪𝟏 𝑹𝒊𝟐 ------(2)  OVERALL VOLTAGE GAIN 𝑨𝑽 = 𝑽𝟎 𝑽𝑺 = 𝑽𝟎 𝑽𝝅𝟐 × 𝑽𝝅𝟐 𝑽𝝅𝟏 × 𝑽𝝅𝟏 𝑽𝑺 -----(3) Apply voltage divider rule at the input, we get 𝑽𝝅𝟏= 𝑹𝒊𝟏 𝑹𝒊𝟏 +𝑹𝑺 𝑽𝑺 𝑽π𝟏 𝑽𝑺 = 𝑹𝒊𝟏 𝑹𝒊𝟏 +𝑹𝑺 -------(4) Sub equation (1),(2) and (4) in equation (3), 𝑨𝑽 = 𝒈𝒎𝟐 𝑹𝑪𝟐 𝑹𝑳 𝒈𝒎𝟏 𝑹𝑪𝟏 𝑹𝒊𝟐 . 𝑹𝒊𝟏 𝑹𝒊𝟏 +𝑹𝑺 𝑨𝑽 = gm1𝐠𝒎𝟐 𝑹𝑪𝟐 𝑹𝑳 𝑹𝑪𝟏 𝑹𝒊𝟐 . 𝑹𝒊𝟏 𝑹𝒊𝟏 +𝑹𝑺
  • 9.  Input resistance 𝐑𝐢𝟏 = 𝐑𝟏 𝐑𝟐 𝐫𝛑𝟏  Output Resistance VS is set to zero 𝑽𝝅𝟏=0 gm1𝑽𝝅𝟏=0 𝑽𝝅𝟐 = 𝟎 𝒈𝒎𝟐𝑽𝝅𝟐 = 𝟎 R0 = RC2