Ch 3 CPU.pptx Architecture computer organization

Chapter 3 : CPU
CPU stands for Central Processing Unit. It is the primary component of a computer
system that performs most of the processing tasks within the computer.
It is also known as the brain of a computer, since it controls all the functions and
processes of the computer system.
The CPU is responsible for executing instructions, processing data, performing
calculations, and managing the flow of information between different components of the
computer.
It is typically located on the motherboard and is connected to other components such as
memory, input/output devices, and storage media.

John Von Neumann Machine Model
Model for designing and building computers, based on the following three
characteristics or consists of the following main sub-systems:
1. Memory
2. CPU(ALU,CU and Registers)
3. Input/Output System (I/O)
The connection and attachments of parts, in a definite sequence to produce
finished machine which is called assembly level machine organization.
So, at a top level, a computer consists of: CPU, Memory and I/O components.
All computers more or less based on the same basic design, of the John Von
Neumann Architecture!
The components are interconnected in order to execute programs by CPU.

Top level Structure of a Computer System
.

Cont…
Among the parts of computer that does data processing operations
is called (CPU).
The CPU is made of 3 major parts:
1.Registers: stores intermediate data generated during execution
2.ALU: performs required micro-operations
3.Control Unit: Decodes the instructions and controls transfer of
data among registers and instruct ALU to perform correct
operation

Register
A computer register is a small amount of high-speed storage within a computer
processor.
It is used to store temporary data and instructions that the processor needs to perform
calculations and other tasks.
Registers can help speed up the execution of instructions by allowing the processor to
quickly access the data it needs to perform a specific operation.
Registers are fast memories, but limited in storage capacity. Therefore, intermediate
data are needed to be stored with a register like pointers, counters, temp results, and
partial products.
Those data cannot be saved in main memory because, their access is time consuming.
Therefore, it is more efficient and faster to be stored inside the processor itself.
So the solution is designing multiple registers inside processor and connects them
through a common bus.

Cont…
The number of registers in a processor may vary from just one processor register to other.
In the old age computers, there was only one general purpose register called the
Accumulator (AC) which is the main operand register of the ALU.
A general-purpose register is a type of register that can store different types of data such
as integers, memory addresses and or floating-point numbers.
But in modern CPUs, there are many general-purpose registers.
It is advantageous to have many registers either special or general.
1. The data register (DR) acts as a buffer between the CPU and main memory. It is used as
an input operand register with the accumulator.
2. The address register (AR) holds the address of the memory in which the operand
resides.
3. The instruction register (IR) holds the opcode of the current instruction.
4. The program counter (PC) holds the address of the next instruction to be fetched for
execution.

Cont…
Additional addressable registers can be provided for storing operands and
address.
This can be viewed as replacing the single accumulator by a set of registers.
If the registers are used for many purposes, the resulting computer is said to
have general purpose register organization.
In the case of processor registers, a register is selected by the multiplexers
that form the buses as shown in the figure below.

Organization for seven CPU registers

Cont…
The output of each register is connected to true multiplexer (mux) to form the two
buses A & B.
The selection lines in each multiplexer select one register or the input data for the
particular bus.
The A and B buses forms the input to a common ALU. The operation selected in the
ALU determines the arithmetic or logic micro-operation that is to be performed.
The result of the micro-operation is available for output and also goes into the inputs
of the registers.
The register that receives the information from the output bus is selected by a
decoder.
The resulted ALU data is directed to the input of all 7 registers which one of them will
be selected according to 3 X 8 decoder connected to inputs of the registers.

For example, to perform operation
R1 ← R2 + R3
The control then provides
1. SELA - MUXA select R2 into BUS A
2. SELB - MUXB select R3 into BUS B
3. OPR - (ALU operation selection) is ADDITION
4. SELD - Decoder selection to direct the output to destination register R1

Control Word
There are 14 bit binary selection inputs in the unit, and their combined value
specifies a control word.
It consists of four fields. Three fields contain three bits each, and one field has five
bits.
The three bits of SELA select a source register for the A input of the ALU.
The three bits of SELB select a register for the B input of the ALU
The three bits of SELD select a destination register using the decoder and its seven
load outputs.
The five bits of OPR select one of the operations in the ALU.

Encoding of Register Selection Fields

Cont…
The 3-bit binary code listed in the first column of the table specifies the binary code
for each of the three fields.
The register selected by fields SELA, SELB, and SELD is the one whose decimal
number is equivalent to the binary number in the code.
When SELA or SELB is 000, the corresponding multiplexer selects the external input
data. SELA or SELB = 000 (Input) : MUX selects the external input data.
When SELD = 000,(none) no destination register is selected but the contents of the
output bus are available in the external output.

Stack register
A stack register is a CPU register whose purpose is to keep track of a call stack.
A stack is a memory unit with an address register called Stack Pointer (SP). This
register influence the address for the stack.
Stack is a storage device and the most important feature in the CPU. It stores
information in a way that the item is stored last is the first to be retrieved
(LIFO).
SP value always points at top item in stack and is used to indicate the location of
the last item put onto the stack.

Cont…
There are two operations done on the stack:-
1.PUSH (Push Down) - operation of insertion of items into stack.
2.POP (Pop Up) - operation of deletion item from stack.
These operations are simulated by Incrementing and Decrementing stack register (SP)
value.
To insert new item, first start by incrementing SP value then a new word will be written
where SP now points to (top of stack).
To remove top item from stack, first start by decrementing the content of SP value and
then top of stack holding address is the next item.

Cont…
In digital computers, stack can be implemented in two ways:
1.Register Stack
2.Memory Stack
 Register Stack: it is standalone unit that consists of collection of finite
number of registers.
The below given example shows 64 location stack unit with SP that stores
address of the word that is currently on the top of stack.

Cont…
Note that three items are placed in the stack A, B, and C. Item C is in top of stack so that SP
holds 3 which the address of item C.
To remove top item from stack (popping stack), we start by decrementing the content of SP.
Item B is now in top of stack holding address 2. To insert new item (pushing the stack), we
start by incrementing SP then a new word will be written where SP now points to (top of
stack).
Register stack is generally on the CPU and Memory stack is on the RAM. So we can say that
access to register stack is faster when compared to memory stack.
Memory stack can be large in size where as register stack is limited size.

Cont…
Note that in 64 word stack, we need to have SP of 6 bits only (from 000000 to
111111).
If ( 111111 ) is reached, then at the next push SP will be (000000), that is when
the stack is FULL.
Similarly when SP is 000001 then at the next pop, SP will go to 000000 that is
when the stack is EMTY.
Stack Limits: Check for stack overflow (full) and underflow (empty) that is
checked by using two register
Upper Limit and Lower Limit Register
After PUSH Operation, SP compared with the upper limit register and After
POP Operation, SP compared with the lower limit register

Memory Stack
A stack can also implemented in a random access memory attached to CPU.
The implementation of a memory stack is done by assigning a portion of memory to a
stack operation and using a processor register (SP) as a stack pointer.
So, an area of the computer memory is broken into three segments such as program,
data, and stack.
The address of the next instruction in the program is saved in the pointer Program
Counter (PC) it read the instruction during the fetch stage.
The Address Register (AR) points to an array of the information (operands) and is
used during the execute phase to read an operand
The three registers that are linked to the common bus are PC, AR, and SP.
An element is pushed into or popped from the stack using a stack pointer and the data
register DR holds the data to be written into or read from the stack.

Control unit
Control unit is part of CPU used to perform the following:
1. Reads an instruction from memory
2. The instruction’s address is in the PC
3. Interprets the instruction, generating signals
that tell the other components what to do.
4. Execute an instruction.

Instruction Process
An instruction may take many machine cycles to complete.
Executing a single instruction consists of a particular cycle of events; such as
fetching, decoding, executing and storing.

Cont…
The steps for executing an instruction:
1. Fetch the instruction
2. Decode the instruction
3. Locate the operand
4. Fetch the operand
5. Execute the operation.
6. Store the results
7. Go back to step 1

Cont…
Example :To read a location (A):
Write the address (A) into the MAR.
Send a “read” signal to the memory.
Read the data from MDR.
To write a value (X) to a location (A):
Write the address (A) into the MAR
Write the data (X) to the MDR.
Send a “write” signal to the memory.

Example of Fetch-Decode and Execute Cycle of an instruction
How the CPU can perform calculations, using a process known as the fetch-decode-
execute cycle.
Here, you have a representation of a CPU and RAM and The registers are also
shown, where data can be temporarily stored.

Fetch
The program counter (PC) starts at 0000. This means that the first address in RAM
where the computer will look for an instruction is 0000.

Cont…
The computer needs somewhere to store the current address in RAM that it is looking
for.
This is what the memory address register (MAR) is for. The address 0000 is therefore
copied into the MAR.

Cont…
A signal is now sent down through the address bus to the RAM. The control unit
sends out a memory read signal, and the contents of the address 0000 are copied
through the data bus to the memory data register (MDR).

Cont…
As the data fetched during the fetch stage is an instruction, it is copied into the
instruction register (IR).

Cont…
As the first instruction has been fetched, the system is at the end of the fetch stage of
the cycle and mean while the program counter can be incremented by 1,
So, the system is ready to read the next instruction when the next fetch cycle starts.

Decode
Now, the instruction needs to be decoded.
It is sent via the data bus to the control unit, where it is split into two parts.
The first part is the operation code or opcode, which in this example CPU is the first
four bits. This is the command that the computer will carry out.
The second part, in this case the second four bits, is the operand. This is an address
in RAM where data will be read from or written to, depending on the operation.
The control unit can translate opcodes into instructions. So here the control unit
translates the opcode 0101 into a LOAD FROM RAM instruction.

Execute
Now, the command will be executed. The operand is copied to the MAR, as it
provides the address of the data to be loaded (0100 in this case).
The data at address 0100 is then fetched from RAM and passed up the data bus to the
MDR. As it is not an instruction but simply data, it is then passed to the accumulator
(Acc).

Instruction Formats
In computer architecture, the instruction format is defined as standard machine
instruction format that can be directly decoded and executed by CPU.
We know that a machine instruction has an opcode (operation code) and operands.
It is simply sequence of bits (0 and 1) contained in the machine that define the layout of
the instruction.
So, an instruction is normally made up of a combination of an operation code and some
way of specifying an operands.

Cont…
An opcode specifies what operation should carry out and the operand specifies the
parties (registers, memory location, etc.…).
The operations specified by computer instructions are performed on operands stored
either in memory or in registers.
Example : ADD R1 , R2
This is an instruction where ADD is the opcode and R1 and R2 are the two operands.
Operands are separated by a coma.

Cont…
The operations specified by computer instructions are performed on operands stored
either in memory or in registers.
Operand residing in memory is specified by its memory address and operand residing
in a register is specified by its name.
Therefore, Encoding an instruction set can be done in a variety of ways.
Because, Architectures are differentiated from one another by the number of bits
allowed per instruction, by the number of operands allowed per instruction, and by
the types of instructions and data each can process.

Cont…
The number of operands per instruction can be three, two, one, or zero address
instruction.
So, Instructions can be classified based on the number of operands or the basis of
number of address as:
Three-address
Two-address
One address
Zero-address

Three Address instruction
Three address instructions computer needs three address fields. The address field
may be a register or a memory operand.
A three-address instruction takes the form operation add-1, add-2, add-3.
In this form, each of add-1, add-2, and add-3 refers to a register or to a memory
location.
For example, the instruction ADD R1,R2,R3.
This instruction indicates that the operation to be performed is addition and the
values to be added are those stored in registers R3 and R2 that the results should be
stored in register R1.

Two Address Instructions
This format contains two address fields which specify either a register or a memory data.
It takes the form operation add-1, add-2. In this form, each of add-1 and add-2 refers to
a register or to a memory location.
 For example, the instruction ADD R1,R2.
This instruction adds the contents of register R1 to the contents of register R2 and stores
the results in register R1.
The original contents of register R1 are lost due to this operation while the original
contents of register R2 remain intact.

One Address
One address instructions computers needs one address field. An implied accumulator (A)
register is used for all data manipulation.
Here all the operations are carried out between the accumulator register and a memory
operand.
A one-address instruction takes the form ADD R1.
In this case the instruction implicitly refers to a register, called the Accumulator Racc,
such that the contents of the accumulator is added to the contents of the register R1 and
the results are stored back into the accumulator.
If a memory location is used instead of a register then an instruction of the form ADD B
is used.
In this case, the instruction adds the content of the accumulator Racc to the content of
memory location B and stores the result back into the accumulator.

Cont…
E.g. ADD [X]
It denotes the operation, A <-- A+ M[X]
Where A = Accumulator register, M[X] = Memory data at address X.

Zero Address Instructions
An instruction that contains no address fields; operand sources and destination are both
implicit. It may for example enable stack processing:
E.g.: ADD
The above instruction consists of an operation code only. It has no address field. The
operation has the effect of popping the two top numbers from the stack, adding the
numbers and pushing the sum into the stack.
Here all operands are performed within stack.
POP TOP ;
POP TOP-1 ;
ADD (TOP) +(TOP-1) ;
PUSH result ;

Addressing Modes
Addressing mode specifies the way how the address of an operand is specified in an
instruction.
The different ways in which operands can be addressed are called the addressing modes.
Addressing modes differ in the way the address information of operands is specified.
The simplest way for an instruction to specify an operand is to include the operand
rather than an address or some other information describing where the operand is.

Cont…
There are different types of address modes such as:
1. Immediate Addressing
2. Stack Addressing Mode
3. Direct Addressing
4. Indirect Addressing
5. Register Addressing
6. Register Indirect Addressing
7. Relative Addressing
8. Indexed Addressing

Immediate Addressing mode
Include the operand itself in the instruction, that is, no address information is needed.
The operand is specified in the instruction explicitly.
Instead of address field, an operand field is present that contains the operand.
Operand is part of instruction. It is also called as implicit addressing mode.
Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand

Stack Addressing Mode
The operand is contained at the top of the stack.
Example-
ADD
This instruction simply pops out two symbols contained at the top of the stack.
The addition of those two operands is performed.
The result so obtained after addition is pushed again at the top of the stack.

Direct Addressing mode
The address field of the instruction contains the effective address of the operand in the
memory. Effective address (EA) = address field (A)
Example: ADD A .
Add contents of cell A to accumulator .
That means, look in memory at address A for operand.
It is a single memory reference to access data .Only one reference to memory is required
to fetch the operand.
It is also called as absolute addressing mode.

Indirect Addressing mode
The address field of the instruction specifies the address of memory location that
contains the effective address of the operand.
The address field of the instruction gives the address at which the effective address is
stored in memory.
Two references to memory are required to fetch the operand.

Register Direct Addressing Mode
The operand is contained in a register set and the address field of the instruction
refers to a CPU register that contains the operand.
Limited number of register and very small address field is needed.
Shorter instructions and faster instruction fetch.
No reference to memory is required to fetch the operand. Example
ADD R will increment the value stored in the accumulator by the content of register
R.
AC ← AC + [R]

Register Indirect Addressing Mode
The address field of the instruction refers to a CPU register that contains the effective
address of the operand.
Only one reference to memory is required to fetch the operand.
This addressing mode is similar to indirect addressing mode.
The only difference is address field of the instruction refers to a CPU register.

Relative Addressing Mode
Effective address of the operand is obtained by adding the content of program
counter with the address part of the instruction.
In this mode effective address is obtained by adding displacement to PC. EA= PC +
Address field value. It is a version of displacement addressing.
Program counter (PC) always contains the address of the next instruction to be
executed. The address part of the instruction is called as offset and it can +ve or –ve.
When the offset is added to the PC the resultant number is the memory location
where the operand will be placed.

Indexed Addressing Mode
In index addressing mode, contents of Index register is added to address part of
instruction to obtain effective address.
The address part of instruction holds the beginning address and is called as base.
The index register hold the index value, which is +ve. Base remains same, the index
changes.
When the base is added to the index register the resultant number is the memory
location where the operand will be placed.
Address field hold two values
X = constant value (offset)
R = register that holds address of memory locations

Instruction and Instruction Set
Instruction is a specific command that given to a computer application to perform some
kind of task or function.
So, an instruction set is a group of commands for a CPU in machine language. The term
can refer to all possible instructions for a CPU to enhance its performance in certain
situations.
Some instructions are simple read, write and move commands that direct data to
different hardware.
The instruction set provides commands to the processor, to tell it what it needs to do.
These instructions direct the computer in terms of data manipulation.

Instruction Set Architectures
There are a large number of different CPUs, and they don’t all use the same instruction set. That means
they will not interpret for instructions the same way.
The architecture of the Central Processing Unit (CPU) operates the capacity to function from “Instruction
Set Architecture” to where it was designed.
E.g. In one CPU architecture 501012 may mean add r10, r12 while in another architecture it may mean
load r10, 12.
So ,Instruction Set Architectures is the set of processor design techniques used to implement the
instruction work flow on hardware.
Therefore ,the architectural design of the CPU is either Reduced instruction set computing (RISC) or
Complex instruction set computing (CISC).

Reduced Instruction Set Computers (RISCs)
(RISC) is a computer which only use simple instructions that can be divide into
multiple instructions which perform low-level operation within single clock cycle.
It is computer designed to simplify the individual instructions given to the computer
in order to realise a task.
RISC computer, a task might require more instructions (code) in order to realise a
task, because the individual instructions are written in simpler code.
The key operational concept of the RISC computer is that each instruction performs
only one function (e.g. copy a value from memory to a register).
Having an operation broken into small instruction (RISC) allows the compiler to
optimize the code.

Complex Instruction Set Computers (CISCs)
A complex instruction set computer (CISC) is a computer where single instructions
can execute several low-level operations (such as a load from memory, an arithmetic
operation, and a memory store) or are capable of multi-step operations.
Examples of CISC architectures include complex mainframe computers to simplistic
microcontrollers where memory load and store operations are not separated from
arithmetic instructions.
The CISC instruction has no option but to wait for its operands to come from
memory potentially delaying other instruction .

Properties of RISC
Store/load are the only memory accesses.
Data manipulation instructions are register-to-register.
Simple addressing mode.
Instruction formats are all the same length.
Instructions perform elementary operations.
One instruction per cycle (simple instruction).

Properties of CISC
Memory access is available to most types of instruction.
Many addressing mode (substantial in number).
 Instruction formats are of different lengths.
Instructions perform both elementary and complex operations (microinstructions are
then necessary.
Multiple cycle for executing one instruction (complex instruction).

Instruction Type
The type of instructions forming the instruction set of a machine is an indication of
the power of the fundamental architecture of the machine.
Instructions can in general be classified as in the following Sub sections.
1. Data Movement Instruction
2. Arithmetic Logic Instruction
3. Sequencing Instruction
4. Input/Output Instruction

Data Movement Instructions
Data movement instructions are used to move data among the different units of the
machine.
Most particularly among these are instructions that are used to move data among the
different registers in the CPU.
A simple register to register movement of data can be made through the instruction.
e.g. MOVE R1, R2
This instruction moves the content of register R2 to register R1.
The effect of the instruction is to override the contents of the (destination) register R1
without changing the contents of the (source) register R2.

Some Common Data Movement Operations

Arithmetic and Logical Instructions
Used to perform arithmetic and logical manipulation of registers and memory
contents.
Examples : ADD R1,R2,R0
SUBTRACT R1,R2,R0
The first instruction adds the contents of source registers R0 and R2 and stores the
result in destination register R1(three address instruction).
The second instruction subtracts the contents of the source registers R0 and R2 and
stores the result in the destination register R1.
The contents of the source registers are unchanged by the ADD and the SUBTRACT
instructions.

Sequencing Instructions
The order in which the instructions in a program are carried out. The sequencing instructions are
used to change the sequence in which instructions are executed.
They take the form of Conditional Branching (conditional jump), Unconditional Branching
(jump), or Call instructions.
Unconditional Jump Instructions: Transfers the program sequence to the described memory
address.
while Conditional Jump Instructions Transfers the program sequence to the described memory
address only if the condition is satisfied.
A common characteristic among these instructions is that their execution changes the program
counter (PC) value.

Input/Output Instructions
Input and output instructions (I/O instructions) are used to transfer data between the
computer and peripheral devices.
The INPUT instruction is used to transfer data from an input device to the processor
which interfaced with a computer through dedicated input ports.
Suppose that the input port through which a keyboard is connected to a computer
carries the unique address 1000.

Cont…
Therefore, execution of the instruction INPUT 1000 will cause the data stored in a
specific register in the interface between the keyboard and the computer call it the
input data register, to be moved into a specific register (called the accumulator) in the
computer.
Similarly, the execution of the instruction OUTPUT 2000 causes the data stored in
the accumulator to be moved to the data output register in the output device whose
address is 2000.
Alternatively, the computer can address these ports in the usual way of addressing
memory locations or memory mapped i/o.

~~~~~~~~~~~~THE END~~~~~~~~~~~~~
`````````````````IF QUESTION?``````````````````

Ch 3 CPU.pptx Architecture computer organization

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Ch 3 CPU.pptx Architecture computer organization