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Chapter 5 introduction to VHDL
This document provides an overview of hardware description language (HDL) and VHDL. It begins with an introduction to HDLs and why they are needed to model digital hardware. It then presents an example VHDL code for an even parity detector circuit to demonstrate basic VHDL concepts like entities, architectures, signals, and concurrent statements. Finally, it discusses how VHDL fits into the digital design flow from coding to simulation to synthesis.
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Introduces Hardware Description Language (HDL), outlines the presentation, and provides an overview on hardware description languages in software development.
Discusses programming language characteristics, distinguishing features of HDLs, including concurrency, timing, and encapsulation for digital circuit description.
Describes VHDL (VHSIC HDL) evolution, key versions, and IEEE extensions that enhance its capabilities for modern digital circuit design.
Introduces basic VHDL concepts using parity detection example, detailing entity declaration and architecture, and comparing it to traditional programming.
Explains structural description of circuits using VHDL, and describes 'behavioral' description for implementing sequential logic.
Covers VHDL configurations, emphasizing how multiple architectures can be associated and describing coding for synthesis, focusing on practical aspects.
Discusses basic VHDL programs and core syntax elements including design units, entity declarations, architecture bodies, and coding processes.
Details the lexical elements including comments, identifiers, data types, and how free formatting impacts VHDL programming.
Identifies types of objects in VHDL: signals, variables, constants, and discusses their characteristics and how they function in digital design.
Describes data types in standard VHDL, including std_logic and numeric_std, available operators, and the importance of type conversion for accurate design.
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Chapter 5 introduction to VHDL
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- 2. 2 Outline 1. Overview onhardware description language 2. Basic VHDL Concept via an example 3. VHDL in development flow
- 3. 3 1. Overview onhardware description language
- 4. 4 Programming language • Canwe use C or Java as HDL? • A computer programming language – Semantics (“meaning”) – Syntax (“grammar”) • Develop of a language – Study the characteristics of the underlying processes – Develop syntactic constructs and their associated semantics to model and express these characteristics.
- 5. 5 Traditional PL • Modeledafter a sequential process – Operations performed in a sequential order – Help human's thinking process to develop an algorithm step by step – Resemble the operation of a basic computer model
- 6. 6 HDL • Characteristics ofdigital hardware – Connections of parts – Concurrent operations – Concept of propagation delay and timing • Characteristics cannot be captured by traditional PLs • Require new languages: HDL
- 7. 7 Use of anHDL program • Formal documentation • Input to a simulator • Input to a synthesizer
- 8. 8 Modern HDL • Capturecharacteristics of a digital circuit: – entity – connectivity – concurrency – timing • Cover description – in Gate level and RT level – In structural view and behavioral view
- 9. 9 • Highlights ofmodern HDL: – Encapsulate the concepts of entity, connectivity, concurrency, and timing – Incorporate propagation delay and timing information – Consist of constructs for structural implementation – Incorporate constructs for behavioral description (sequential execution of traditional PL) – Describe the operations and structures in gate level and RT level. – Consist of constructs to support hierarchical design process
- 10. 10 Two HDLs usedtoday –VHDL and Verilog –Syntax and ``appearance'' of the two languages are very different –Capabilities and scopes are quite similar –Both are industrial standards and are supported by most software tools
- 11. 11 VHDL – VHDL: VHSIC(Very High Speed Integrated Circuit) HDL – Initially sponsored by DoD as a hardware documentation standard in early 80s – Transferred to IEEE and ratified it as IEEE standard 1176 in 1987 (known as VHDL-87) – Major modification in ’93 (known as VHDL-93) – Revised continuously
- 12. 12 IEEE Extensions – IEEEstandard 1076.1 Analog and Mixed Signal Extensions (VHDL-AMS) – IEEE standard 1076.2 VHDL Mathematical Packages – IEEE standard 1076.3 Synthesis Packages – IEEE standard 1076.4 VHDL Initiative Towards ASIC Libraries (VITAL) – IEEE standard 1076.6 VHDL Register Transfer Level (RTL) Synthesis – IEEE standard 1164 Multivalue Logic System for VHDL Model Interoperability – IEEE standard 1029 VHDL Waveform and Vector Exchange to Support Design and Test Verification (WAVES)
- 13. 13 2. Basic VHDLConcept via an example
- 14. 14 Even parity detectioncircuit • Input: a(2), a(1), a(0) • output: even
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- 16. 16 • Entity declaration –i/o ports (“outline” of the circuit) • Architecture body – Signal declaration – Each concurrent statement • Can be thought s a circuit part • Contains timing information – Arch body can be thought as a “collection of parts” • What’s the difference between this and a C program
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- 18. 18 VHDL Listing 2.2 •Same entity declaration • Implicit δ-delay (delta delay)
- 19. 19 Structural description • Instructural view, a circuit is constructed by smaller parts. • Structural description specifies the types of parts and connections. • Essentially a textual description of a schematic • Done by using “component” in VHDL – First declared (make known) – Then instantiated (used)
- 20. 20 Example • Even detectorusing previously designed components (xor2 and not1)
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- 23. 23 “Behavioral” description • Noformal definition on “behavioral” in VHDL • VHDL “process”: a language construct to encapsulate “sequential semantics” – The entire process is a concurrent statement – Syntax:
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- 27. 27 Testbench • a “virtual”experiment table – Circuit to be tested – Input stimuli (e.g., function generator) – Output monitor (e.g., logic analyzer) • e.g.,
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- 31. 31 Configuration • Multiple architecturebodies can be associated with an entity declaration – Like IC chips and sockets • VHDL configuration specifies the binding • E.g.,
- 32. 32 3. VHDL indevelopment flow
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- 34. 34 Coding for synthesis •“Execution” of VHDL codes – Simulation: • Design “realized” in a virtual environment (simulation software) • All language constructs can be “realized” • “realized” by a single CPU
- 35. 35 – “Synthesis • Designrealized by hardware components • Many VHDL constructs can be synthesized (e,g, file operation, floating-point data type, division) • Only small subset can be used • E.g., 10 additions • Syntactically correct code ≠ Synthesizable code • Synthesizable code ≠ Efficient code • Synthesis software only performs transformation and local search
- 36. 36 • The coursefocuses on hardware, not VHDL (i.e., the “H”, not “L” of HDL) • Emphasis on coding for synthesis: – Code accurately describing the underlying hardware structure – Code providing adequate info to guide synthesis software to generate efficient implementation
- 37. 37 Basic Language Constructsof VHDL
- 38. 38 Outline 1. Basic VHDLprogram 2. Lexical elements and program format 3. Objects 4. Data type and operators
- 39. 39 1. Basic VHDLprogram
- 40. 40 Design unit • Buildingblocks in a VHDL program • Each design unit is analyzed and stored independently • Types of design unit: – entity declaration – architecture body – package declaration – package body – configuration
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- 42. 42 • mode: – in:flow into the circuit – out: flow out of the circuit – inout: bi-directional • E.g.
- 43. 43 • A commonmistake with mode
- 44. 44 • Fix: usean internal signal
- 45. 45 Architecture body • Simplifiedsyntax • An entity declaration can be associated with multiple architecture bodies
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- 47. 47 Other design units •Package declaration/body: – collection of commonly used items, such as data types, subprograms and components • Configuration: – specify which architecture body is to be bound with the entity declaration
- 48. 48 VHDL Library • Aplace to store the analyzed design units • Normally mapped to a directory in host computer • Software define the mapping between the symbolic library and physical location • Default library: “work” • Library “ieee” is used for many ieee packages
- 49. 49 • E.g. • Line1: invoke a library named ieee • Line 2: makes std_logic_1164 package visible to the subsequent design units • The package is normally needed for the std_logic/std_logic_vector data type
- 50. 50 Processing of VHDLcode • Analysis – Performed on “design unit” basis – Check the syntax and translate the unit into an intermediate form – Store it in a library • Elaboration – Bind architecture body with entity – Substitute the instantiated components with architecture description – Create a “flattened”' description • Execution – Simulation or synthesis
- 51. 51 2. Lexical elementsand program format
- 52. 52 Lexical elements • Lexicalelement: – Basic syntactical units in a VHDL program • Types of Lexical elements: – Comments – Identifiers – Reserved words – Numbers – Characters – Strings
- 53. 53 Comments • Starts with- - • Just for clarity • e.g.,
- 54. 54 Identifier • Identifier isthe name of an object • Basic rules: – Can only contain alphabetic letters, decimal digits and underscore – The first character must be a letter – The last character cannot be an underscore – Two successive underscores are not allowed
- 55. 55 • Valid examples: A10,next_state, NextState, mem_addr_enable • Invalid examples: sig#3, _X10, 7segment, X10_, hi_ _there • VHDL is case insensitive: – Following identifiers are the same: nextstate, NextState, NEXTSTATE, nEXTsTATE
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- 57. 57 Numbers, characters andstrings • Number: – Integer: 0, 1234, 98E7 – Real: 0.0, 1.23456 or 9.87E6 – Base 2: 2#101101# • Character: – ‘A’, ‘Z’, ‘1’ • Strings – “Hello”, “101101” • Note – 0 and ‘0’ are different – 2#101101# and “101101” are different
- 58. 58 Program format • VHDLis “free-format”: blank space, tab, new-line can be freely inserted • e.g., the following are the same
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- 62. 62 Objects • A nameditem that hold a value of specific data type • Four kinds of objects – Signal – Variable – Constant – File (cannot be synthesized) • Related construct – Alias
- 63. 63 Signal • Declared inthe architecture body's declaration section • Signal declaration: signal signal_name, signal_name, ... : data_type • Signal assignment: signal_name <= projected_waveform; • Ports in entity declaration are considered as signals • Can be interpreted as wires or “wires with memory” (i.e., FFs, latches etc.)
- 64. 64 Variable • Declared andused inside a process • Variable declaration: variable variable_name, ... : data_type • Variable assignment: variable_name := value_expression; • Contains no “timing info” (immediate assignment) • Used as in traditional PL: a “symbolic memory location” where a value can be stored and modified • No direct hardware counterpart
- 65. 65 Constant • Value cannotbe changed • Constant declaration: constant const_name, ... : data_type := value_expression • Used to enhance readability – E.g.,
- 66. 66 • It isa good idea to avoid “hard literals”
- 67. 67 Alias • Not aobject • Alternative name for an object • Used to enhance readability – E.g.,
- 68. 68 4. Data typeand operators • Standard VHDL • IEEE1164_std_logic package • IEEE numeric_std package
- 69. 69 Data type • Definitionof data type – A set of values that an object can assume. – A set of operations that can be performed on objects of this data type. • VHDL is a strongly-typed language – an object can only be assigned with a value of its type – only the operations defined with the data type can be performed on the object
- 70. 70 Data types instandard VHDL • integer: – Minimal range: -(2^31-1) to 2^31-1 – Two subtypes: natural, positive • boolean: (false, true) • bit: ('0', '1') – Not capable enough • bit_vector: a one-dimensional array of bit
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- 73. 73 IEEE std_logic_1164 package •What’s wrong with bit? • New data type: std_logic, std_logic_vector • std_logic: – 9 values: ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') • '0', '1': forcing logic 0' and forcing logic 1 • 'Z': high-impedance, as in a tri-state buffer. • 'L' , 'H': weak logic 0 and weak logic 1, as in wired- logic • 'X', 'W': “unknown” and “weak unknown” • 'U': for uninitialized • '-': don't-care.
- 74. 74 • std_logic_vector – anarray of elements with std_logic data type – Imply a bus – E.g., signal a: std_logic_vector(7 downto 0); – Another form (less desired) signal a: std_logic_vector(0 to 7); • Need to invoke package to use the data type: library ieee; use ieee.std_logic_1164.all;
- 75. 75 Overloaded operator IEEE std_logic_1164package • Which standard VHDL operators can be applied to std_logic and std_logic_vector? • Overloading: same operator of different data types • Overloaded operators in std_logic_1164 package
- 76. 76 • Type conversionfunction in std_logic_1164 package:
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- 78. 78 Operators over anarray data type • Relational operators for array – operands must have the same element type but their lengths may differ – Two arrays are compared element by element, form the left most element – All following returns true • "011"="011", "011">"010", "011">"00010", "0110">"011"
- 79. 79 • Concatenation operator(&) • e.g., y <= "00" & a(7 downto 2); y <= a(7) & a(7) & a(7 downto 2); y <= a(1 downto 0) & a(7 downto 2);
- 80. 80 Array aggregate • Aggregateis a VHDL construct to assign a value to an array-typed object • E.g., a <= "10100000"; a <= (7=>'1', 6=>'0', 0=>'0', 1=>'0', 5=>'1', 4=>'0', 3=>'0', 2=>'1'); a <= (7|5=>'1', 6|4|3|2|1|0=>'0'); a <= (7|5=>'1', others=>'0'); • E.g., a <= "00000000" a <= (others=>'0');
- 81. 81 IEEE numeric_std package •How to infer arithmetic operators? • In standard VHDL: signal a, b, sum: integer; . . . sum <= a + b; • What’s wrong with integer data type?
- 82. 82 • IEEE numeric_stdpackage: define integer as a an array of elements of std_logic • Two new data types: unsigned, signed • The array interpreted as an unsigned or signed binary number • E.g., signal x, y: signed(15 downto 0); • Need invoke package to use the data type library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
- 83. 83 Overloaded operators in IEEEnumeric_std package
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- 85. 85 New functions in IEEEnumeric_std package
- 86. 86 Type conversion • Std_logic_vector,unsigned, signed are defined as an array of element of std_logic • They considered as three different data types in VHDL • Type conversion between data types: – type conversion function – Type casting (for “closely related” data types)
- 87. 87 Type conversion betweennumber- related data types
- 88. 88 • E.g. library ieee; useieee.std_logic_1164.all; use ieee.numeric_std.all; . . . signal s1, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0); signal u1, u2, u3, u4, u6, u7: unsigned(3 downto 0); signal sg: signed(3 downto 0);
- 89. 89 • E.g. library ieee; useieee.std_logic_1164.all; use ieee.numeric_std.all; . . . signal s1, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0); signal u1, u2, u3, u4, u6, u7: unsigned(3 downto 0); signal sg: signed(3 downto 0);
- 90. 90 – Ok u3 <=u2 + u1; --- ok, both operands unsigned u4 <= u2 + 1; --- ok, operands unsigned and natural – Wrong u5 <= sg; -- type mismatch u6 <= 5; -- type mismatch – Fix u5 <= unsigned(sg); -- type casting u6 <= to_unsigned(5,4); -- conversion function
- 91. 91 – Wrong u7 <=sg + u1; -- + undefined over the types – Fix u7 <= unsigned(sg) + u1; -- ok, but be careful – Wrong s3 <= u3; -- type mismatch s4 <= 5; -- type mismatch – Fix s3 <= std_logic_vector(u3); -- type casting s4 <= std_logic_vector(to_unsigned(5,4));
- 92. 92 – Wrong s5 <=s2 + s1; + undefined over std_logic_vector s6 <= s2 + 1; + undefined – Fix s5 <= std_logic_vector(unsigned(s2) + unsigned(s1)); s6 <= std_logic_vector(unsigned(s2) + 1);
- 93. 93 Non-IEEE package • Packageaby Synopsys • std_logic_arith: – Similar to numeric_std – New data types: unsigned, signed – Details are different • std_logic_unsigned/ std_logic_signed – Treat std_logic_vector as unsigned and signed numbers – i.e., overload std_logic_vector with arith operations
- 94. 94 • Software vendorsfrequently store them in ieee library: • E.g., library ieee; use ieee.std_logic_1164.all; use ieee.std_arith_unsigned.all; . . . signal s1, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0); . . . s5 <= s2 + s1; -- ok, + overloaded with std_logic_vector s6 <= s2 + 1; -- ok, + overloaded with std_logic_vector
- 95. 95 • Only oneof the std_logic_unsigned and std_logic_signed packages can be used • The std_logic_unsigned/std_logic_signed packages beat the motivation behind a strongly-typed language • Numeric_std is preferred