 = min ( PM[k](t) + BM([k][i])(t) ) (1)
PM[k](t) : Path metric corresponding to state k at instant t
BM([k][i])(t): Branch metric of the transtion from state k at t to state i at t+1
Branch Metric
Unit
(BMU)
ACS
Unit
Survior-Path
Memory Unit
(SMU)
Input Output
Fig.3 Basic computation units in Viterbi decoder
all possible](https://image.slidesharecdn.com/chenchu-181025003857/85/Chenchu-5-320.jpg)
BM[k][i](t)
PM[j](t)
BM[j][i](t)
PM[k](t)
Figure 7. A simple example of inserting pipeline levels into ACS unit](https://image.slidesharecdn.com/chenchu-181025003857/85/Chenchu-11-320.jpg)
Chenchu
- 1. Pipelined Architectures forPipelined Architectures for High-Speed and Area-EfficientHigh-Speed and Area-Efficient Viterbi DecodersViterbi Decoders Chen, Chao-Nan Chu, Hsi-Cheng
- 2. Convolutional code Viterbi decoder In-place path metric updating Inserting pipeline levels into ACS
- 3. Convolutional CodesConvolutional Codes Convolutional encoders map information streams into a long code sequence. k = 1 bit input blocks produce n = 2 code symbols each. The code rate k/n expresses the information per coded bit and the constraint length v defines the encoder memory order. This encoder has 2(v–1) = 4 states. Fig.1 A simple rate ½, v = 3 convolutional encoder inputinput 1st code symbol1st code symbol 2nd code symbol2nd code symbol outputoutput
- 4. Viterbi Algorithm (VA)Viterbi Algorithm (VA) The most commonly employed decoding technique that can be implemented using either software or digital hardware. VA uses the trellis diagram (Fig.2) and can theoretically perform maximum likelihood decoding. It finds the most likely path by means of suitable distance metric between the received sequence and all the trellis paths. Fig.2 Trellis diagram representation of the encoder of Fig.1 0000 0101 1010 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 1010 0101 1010 0101 1010 0101 1010 0101 1111 0000 1111 0000 1111 0000 0101 1010 0101 1010 0101 1010 input bit 0input bit 0 input bit 1input bit 1
- 5. Viterbi DecoderViterbi Decoder BMU: BM are computed from introduced input data ACSU: PMs of all states are updated according to equation (1) SMU: The stored decisions are employed in the SMU to build a unique decoded output PM[i](t+1) = min ( PM[k](t) + BM([k][i])(t) ) (1) PM[k](t) : Path metric corresponding to state k at instant t BM([k][i])(t): Branch metric of the transtion from state k at t to state i at t+1 Branch Metric Unit (BMU) ACS Unit Survior-Path Memory Unit (SMU) Input Output Fig.3 Basic computation units in Viterbi decoder all possible
- 6. State State 0 1 2 3 4 5 6 7 0 2 4 6 1 3 5 7 State 0 4 1 5 2 6 3 7 State 0 1 2 3 4 5 6 7 State 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 State (a) (b) Fig. 4. Example for v=3: (a) butterflies in the traditional approach; (b) states and butterfies during one full cycle of in-place computation State i State i+2v-1 State 2i State 2i+1 Overwrites previous metric of state i Overwrites previous metric of state i+2v-1 Fig. 3. Partial trellis diagram or butterfly for in-place computation of updated path metrics. In-place Path MetricIn-place Path Metric UpdatingUpdating Efficiently save half memory size
- 7. State i State i+32 State 2i State 2i+1 Figure 5. The diagram of BF unit Table 1. State arrangement and path metric updating for constraint length 7 (64 states) Figure 6. A novel architecture for the Viterbi decoder Cycle 0 1 2 3 4 5 6 7 Iterarion 0 Address(DpRAM0-3) 0 1 2 3 4 5 6 7 Address(DpRAM4-7) 0 1 2 3 4 5 6 7 Iteration 1 Address(DpRAM0-3) 0 2 4 6 1 3 5 7 Address(DpRAM4-7) 1 3 5 7 0 2 4 6 Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
- 8. State i State i+32 State 2i State 2i+1 Figure 5. The diagram of BF unit Table 1. State arrangement and path metric updating for constraint length 7 (64 states) Figure 6. A novel architecture for the Viterbi decoder Cycle 0 1 2 3 4 5 6 7 Iterarion 0 Address(DpRAM0-3) 0 1 2 3 4 5 6 7 Address(DpRAM4-7) 0 1 2 3 4 5 6 7 Iteration 1 Address(DpRAM0-3) 0 2 4 6 1 3 5 7 Address(DpRAM4-7) 1 3 5 7 0 2 4 6 Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
- 9. State i State i+32 State 2i State 2i+1 Figure 5. The diagram of BF unit Table 1. State arrangement and path metric updating for constraint length 7 (64 states) Figure 6. A novel architecture for the Viterbi decoder Cycle 0 1 2 3 4 5 6 7 Iterarion 0 Address(DpRAM0-3) 0 1 2 3 4 5 6 7 Address(DpRAM4-7) 0 1 2 3 4 5 6 7 Iteration 1 Address(DpRAM0-3) 0 2 4 6 1 3 5 7 Address(DpRAM4-7) 1 3 5 7 0 2 4 6 Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
- 10. State i State i+32 State 2i State 2i+1 Figure 5. The diagram of BF unit Table 1. State arrangement and path metric updating for constraint length 7 (64 states) Figure 6. A novel architecture for the Viterbi decoder Cycle 0 1 2 3 4 5 6 7 Iterarion 0 Address(DpRAM0-3) 0 1 2 3 4 5 6 7 Address(DpRAM4-7) 0 1 2 3 4 5 6 7 Iteration 1 Address(DpRAM0-3) 0 2 4 6 1 3 5 7 Address(DpRAM4-7) 1 3 5 7 0 2 4 6 Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
- 11. Insert Pipeline Levels into ACSInsert Pipeline Levels into ACS Generally, the maximum number of ACS pipeline levels is only dependent on the ratio N/P (N: number of states ; P: number of ACS unit) N/P 1 2 4 8 16 32 64 ACS pipline levels 1 1 2 5 10 20 40 Table 3. The maximum pipelines levels for (N/P) from 1 to 64 + + SelectorComparator PM[i](t+1) BM[k][i](t) PM[j](t) BM[j][i](t) PM[k](t) Figure 7. A simple example of inserting pipeline levels into ACS unit
- 12. ConclusionConclusion Assuming pipeline levels are equally distributed into ACS, the decoding speed is LP/N ≈ 5/8 of a state-parallel ACS instead of P/N. The maximum possible area-saving can be obtained by selecting a large enough ratio N/P A favorable solution for applications, where area-saving and hence power, is the most crucial while moderate decoding speed degradation is allowed.