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CISC VS. RISC
Agenda
• CPU Architecture.
• Instruction Set Architecture (ISA).
• CISC Philosophy. >>> CISC Pros & Cons.
• RISC Philosophy. >>> RISC Pros & Cons.
• CPU Performance Equation.
• Summary.
CISC VS CISC
Instruction Set Architecture (ISA)
• Group of instructions to execute a program.
• Instructions are in the form of: Opcode + Operand.
• An agreement between hardware and human for making interaction
• Example : ADD R1, R2, R3
• Can be represented as :
00101111100001111001010101010101
10111010100011110101001011011010
• Two major schools of ISA: CISC & RISC.
CISC Philosophy
(Complex Instruction Set Computing)
• The primary goal is to complete a task in as
few lines as possible.
• Used on PCs and laptops that need to
process heavy graphics and computations.
• Each instruction consist of one step.
(ex: MULT 2:3, 5:2, load the two values into
registers, multiplies the operands, and then
stores the product in appropriate register).
CISC Pros & Cons
• Instruction size is different from one operation to another.
• Operation size is smaller but no of cycles are more.
• Needs better hardware and powerful processing.
• Performance is slow due to the amount of clock time taken
by different instructions.
RISC Philosophy
(Reduced Instruction Set Computing)
• Use only simple instructions that can be
executed within one clock cycle.
• Keep all instructions of same size.
• Allow only load/store instruction to
access the memory.
(ex: MULT command divided into three
separate commands:
LOAD, PROD, and STORE).
RISC Pros & Cons
• Allow free use of microprocessors space because of its
simplicity.
• Needs large memory caches on the chip itself so require
very fast memory.
• Give support for high level languages (like C, C++, Java).
• Performance depends on the programmer or compiler.
CPU Performance Equation
• The following equation is commonly used for expressing a
computer's performance ability:
• CISC minimize the number of instructions per program.
• RISC does the opposite, reduce the cycles per instruction.
𝐶𝑃𝑈 𝑇𝑖𝑚𝑒 =
𝑆𝑒𝑐𝑜𝑛𝑑𝑠
𝑃𝑟𝑜𝑔𝑟𝑎𝑚
=
𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠
𝑃𝑟𝑜𝑔𝑟𝑎𝑚
𝑥
𝐶𝑦𝑐𝑙𝑒𝑠
𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠
𝑥
𝑆𝑒𝑐𝑜𝑛𝑑𝑠
𝐶𝑦𝑐𝑙𝑒
Summary

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CISC VS CISC

  • 2. Agenda • CPU Architecture. • Instruction Set Architecture (ISA). • CISC Philosophy. >>> CISC Pros & Cons. • RISC Philosophy. >>> RISC Pros & Cons. • CPU Performance Equation. • Summary.
  • 4. Instruction Set Architecture (ISA) • Group of instructions to execute a program. • Instructions are in the form of: Opcode + Operand. • An agreement between hardware and human for making interaction • Example : ADD R1, R2, R3 • Can be represented as : 00101111100001111001010101010101 10111010100011110101001011011010 • Two major schools of ISA: CISC & RISC.
  • 5. CISC Philosophy (Complex Instruction Set Computing) • The primary goal is to complete a task in as few lines as possible. • Used on PCs and laptops that need to process heavy graphics and computations. • Each instruction consist of one step. (ex: MULT 2:3, 5:2, load the two values into registers, multiplies the operands, and then stores the product in appropriate register).
  • 6. CISC Pros & Cons • Instruction size is different from one operation to another. • Operation size is smaller but no of cycles are more. • Needs better hardware and powerful processing. • Performance is slow due to the amount of clock time taken by different instructions.
  • 7. RISC Philosophy (Reduced Instruction Set Computing) • Use only simple instructions that can be executed within one clock cycle. • Keep all instructions of same size. • Allow only load/store instruction to access the memory. (ex: MULT command divided into three separate commands: LOAD, PROD, and STORE).
  • 8. RISC Pros & Cons • Allow free use of microprocessors space because of its simplicity. • Needs large memory caches on the chip itself so require very fast memory. • Give support for high level languages (like C, C++, Java). • Performance depends on the programmer or compiler.
  • 9. CPU Performance Equation • The following equation is commonly used for expressing a computer's performance ability: • CISC minimize the number of instructions per program. • RISC does the opposite, reduce the cycles per instruction. 𝐶𝑃𝑈 𝑇𝑖𝑚𝑒 = 𝑆𝑒𝑐𝑜𝑛𝑑𝑠 𝑃𝑟𝑜𝑔𝑟𝑎𝑚 = 𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 𝑃𝑟𝑜𝑔𝑟𝑎𝑚 𝑥 𝐶𝑦𝑐𝑙𝑒𝑠 𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠 𝑥 𝑆𝑒𝑐𝑜𝑛𝑑𝑠 𝐶𝑦𝑐𝑙𝑒