Clocked Sequential circuit analysis and design

Clocked Sequential circuit analysis and design

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  Clocked Sequential Circuit:Analysis and Design Learning Objectives: 1. To learn analysis of Synchronous Sequential Circuits 2. To learn Design of Synchronous Sequential Circuit 3. To learn State reduction and Assignment in design 4 April 2019 1 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com
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  Analysis of ClockedSequential Circuit 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 2 Outputs & state of a clocked Sequential circuit is function of inputs and previous state. Analysis of clocked sequential logic circuit consists of obtaining •state table: Also called transition table consists of four sections; inputs, present state, next state and output. •state diagram: Graphical representation of state table. A state is represented by a circle and transition between states is represented by a directed line. Input and output values of the transition is put on the directed line •state equation: Specifies next state in terms of present state and inputs. Output equation is also described in terms of present state and inputs
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  Analysis Steps 4 April2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 3 State & output equation • Assign variable names to input, outputs, flip flops input and output • Determine FF’s input equations in terms of input variable and present state. • Determine next state equation of flip flop’s using FF characteristic equation (state equation). Determine circuit’s output if any, in terms of input variable/ present state (output equation). State Table • List all binary combination of inputs and present states • List next state of FF’s and outputs using state equation and output equation. State Diagram • Mark FF states and connect them with directed lines to next state with input / output values on the line. Each row of state table correspond to a directed line.
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  Analysis : Example 4April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 4 DA A A Y DB B B X CLK Example circuit has one input X, two D FF with outputs A & B and one output Y. DQ XAD BXAXD n B A    1FF;DofequationsticcharacteriUsing s;FF'Input to   equation;Output equation;State 1 1 XBAY XAB BXAXA n n     
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  Analysis: example 4 April2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 5 00 01 11 10 1/0 1/01/0 1/0 0/0 0/1 0/1 0/1 State Table input Present state Next state Output X A B An+1 Bn+1 Y 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 0     equation;outputState/ 1 1 XBAY XAB XBAA n n     
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  Design Steps 4 April2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 6 • From the word description and specification, derive a state diagram of the circuit. Reduce the number of state if possible • Assign binary variables to the state. • Obtain state table from state diagram • Choose the type of FF to be used and fill the binary values at FF input for each state transition using FF excitation table. • Derive the FF input equation. FF input and circuit output are function of inputs and present state variables • Draw the logic diagram using FF input equations and circuit output equation
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  Design Example: SequenceDetector 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 7 Design a sequence detector which detects three or more 1’s coming to an input line. On detection of per sequence, a ‘1’ is generated • Let initial state of circuit is s0 • If input is ‘0’, state is unchanged • If input is ‘1’, state changes to s1 (a ‘1’ has arrived) • If state of circuit is s1 • If input is ‘0’, state changes to s0 (a ‘0’ has arrived) • If input is ‘1’, state changes to s2 (a ‘1’ has arrived) • If state of circuit is s2 • If input is ‘0’, state changes to s0 (a ‘0’ has arrived) • If input is ‘1’, state changes to s3 (a ‘1’ has arrived) •If state of circuit is s3 • If input is ‘0’, state changes to s0 (a ‘0’ has arrived) • If input is ‘1’, state is unchanged (a ‘1’ has arrived) s0 s1 s2 s3 1/0 1/01/1 1/1 0/0 0/0 0/1 0/0
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  Design Example: SequenceDetector 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 8 00 01 10 11 1/0 1/01/1 1/1 0/0 0/0 0/0 0/0 State Table input Present state Next state Input conditions Outpu t X A B An+1 Bn+1 TA TB Y 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 1 Let input is X. To represent 4 states, 2 FF’s are required. Let T FF’s has to be used. State assignment: s0→00, s1→01, s2→10, s3→11 State diagram Excitation Table of T FF Qn Qn+1 T 0 0 0 0 1 1 1 0 1 1 1 0
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  Design Example: SequenceDetector 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 9               XABAXY BABXBXBABXBAXT BAXAXBAXT B A       7,6,, 6,5,4,3,1,, 5,3,2,, Writing TA, TB, and Y as a function of X, A, B in SOP form and simplifying using K-map TA A A Y TB B B X CLK
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  State Reduction andAssignment 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 10 State reduction aims to reduce number of FF’s by reducing number of states, while keeping input output relationship unchanged. Step 1: Make the reduced state table a 0/0 b d f g e c 1/1 1/0 1/1 0/0 1/1 1/1 0/0 1/1 0/0 0/01/0 0/0 0/0 Present State Next State Output X=0 X=1 X=0 X=1 a a b 0 0 b c d 0 0 c a d 0 1 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1
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  State Reduction andAssignment 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 11 Step 2: Find equivalent state in reduced state table and remove one of them Two states are equivalent if, they give same set of output , go to same state or equivalent state for inputs state ‘e’ and ‘g’ are equivalent. Row corresponding to ‘g’ is removed in table and state ‘g’ is replaced by ‘e’ elsewhere Present State Next State Output X=0 X=1 X=0 X=1 a a b 0 0 b c d 0 0 c a d 0 1 d e f 0 1 e a f 0 1 f e f 0 1
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  State Reduction andAssignment 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 12 Step 3: Repeat the step 2 if any equivalent state is found again state ‘d’ and ‘f’ are equivalent. Row corresponding to ‘f’ is removed in table and state ‘f’ is replaced by ‘d’ elsewhere Present State Next State Output X=0 X=1 X=0 X=1 a a b 0 0 b c d 0 0 c a d 0 1 d e d 0 1 e a d 0 1
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  State Reduction andAssignment 4 April 2019 Dr Naim R Kidwai, Professor, Integral University, Lucknow India, www.nrkidwai.wordpress.com 13 Step 3: Repeat the step 2 if any equivalent state is found again state ‘c’ and ‘e’ are equivalent. Row corresponding to ‘e’ is removed in table and state ‘e’ is replaced by ‘c’ elsewhere Present State Next State Output X=0 X=1 X=0 X=1 a a b 0 0 b c d 0 0 c a d 0 1 d c d 0 1 Step 4: If no equivalent state is found, state reduction is complete. Assign binary values to states and implement the circuit. Final reduced diagram is shown in figure, which has four states ie. Require 2 FF’s a 0/0 b d c 1/0 1/1 0/0 1/1 0/01/0 0/0