CMOS Operational Amplifier Design

ELEC 4609 A1O - Integrated Circuit Design & Fabrication
Op-Amp Design Project
45NM CMOS OP-AMP DESIGN
April 11, 2019
Rashad Alsaﬀar - 101006781
Carleton University
Department of Electronics

Op-Amp Report Rashad Alsaffar - 101006781
1 Introduction
The purpose of this project was to explore schematic and layout design approaches of an opera-
tional amplifier using 45nm SOI CMOS process within Cadence Virtuoso, operating from a 1.2V
supply. Analog integrated circuit introduces new techniques for schematic-level simulation of indi-
vidual MOSFET performance and contribution to the final product. Layout can be explored through
several mediums as we will explore.
The following schematic was built within Cadence Virtuoso, detailing the multiple stages of the
operational amplifier, including bias, differential-input, gain and output buffering stages:
Figure 1: Two-Stage Op-Amp Schematic-View Design [1]
Each transistor within the schematic above played a dedicated role within its stage. The transistor
sizing dimensions were provided and implemented into Cadence within the table below:
Figure 2: Two-Stage Op-Amp Original FET Dimensions [1]
Unfortunately simulation errors were experienced using said values provided in the figure above, and
instead alternative values were utilized for FET dimensions (see Figure 18 in the attached Appendix),
utilizing variables WR = 7nm and L = 200nm.

2 Schematic Design
The gdpk045 library was utilized, providing nmos1v and pmos1v components translating to NMOS
and PMOS devices, respectively. The two-stage op-amp display from Figure 1 was implemented
within Cadence as a fully operational schematic:
Figure 3: Implemented Two-Stage Op-Amp Schematic
All transistor sizing is visible within the schematic above, as well as the names of each device in
correlation with the pre-conceived schematic within Figure 1.
Initially body effect was negated by connecting the bulk of each device to their relative source. Un-
fortunately, this could not be implemented within layout or within the IC fabrication/manufacturing
stages due to the limitations of poly and metal materials. Instead, the bulk connections of each
device were connected properly to one of the power lines, VDD or VSS; NMOS device bulk connec-
tions were established through VSS and PMOS device bulk connections were established through VDD.
Confirmation of the finalized schematic by a TA allowed for the procedure of symbol generation
and simulations via testbenches using ADE L Spectre tools.
Figure 4: Implemented Two-Stage Op-Amp Test Bench

The middle ﬁgure was the generated symbol of the op-amp with designated power lines VDD and
VSS, diﬀerential inputs Vin+ and Vin−, as well as a circuit output VOUT .
Supplied test benches within ADE L provided several testing conditions for four simulations: Voffset,
Open-Loop Gain, Risetime (10%-90%) and Falltime (10%-90%). Simulation conditions provided
functioning simulations for risetime and falltime test benches, while the remaining two would be
tested using ADE XL tools.
Figure 5: Op-Amp Risetime (10%-90%) Spectre Simulation
Figure 6: Op-Amp Falltime (10%-90%) Spectre Simulation

The simulation plots above characterize an approximate device risetime of 0.4µs and approximate
device falltime of 60ns. The provided plots above however characterize transient test benches under
nominal conditions, i.e. NN, 1.2V, 25◦
C
Advanced ADE XL simualtion tools were required to test the device across fast and slow performance
speeds as characterized by the table below; variations include supply voltage and temperature:
Figure 7: Two-Stage Op-Amp PVT Variations [1]
Multiple temperature conditions were considered when simulating PVT variations within ADE XL.
The original test benches within ADE L were imported within the enhanced design environment and
new test simulations were performed in detail below:
Figure 8: Two-Stage Op-Amp PVT Data Simulations
Important device parameters of the op-amp can be found in the figure above, including Voffset, open-
loop gain, unity-gain bandwidth (UGBW), phase margin and power dissipation. The table below
identifies the particular values characterized by the device response:
Figure 9: Two-Stage Op-Amp PVT Data Simulations (Condensed)
Circuit performance is in fact very dependant on temperature and environmental effects. Progression
of the device will now scale into layout design.

3 Layout Design
We will discuss the multitude of techniques involved with Analog CMOS IC design, including device
orientation, matching, parasitic compensation, fingers, etc.
3.1 Transistor Layout Structure
It is important for the MOSFET devices to have multiple contacts across the source and drain, so
as to avoid micro-fractures and parasitic resistance within the device.
Analog transistor devices with a large W
L
ratio may experience unwanted parasitic capacitance be-
tween bulk connections. To negate this effect, transistors can be split into multiple ”fingers” in order
to compensate for the total width of the device whilst reducing parasitic capacitance.
The figure below details the nmos1v layout design obtained from the gdpk045 library. The transis-
tor above provides a width of 3µm. This is quite large, however the transistor can be ”shrunk” by
providing multiple fingers, three in particular, with each finger width providing W
3
= 1µm.
Figure 10: Wide Analog Transistor Fingers Demonstration
The particular example above demonstrates 1
3
bulk-parasitic capacitance reduction between the
source and drain of the transistor.
3.2 Matching
Matching is one of the most important considerations in Analog CMOS IC design. Layout designers
aim to ”match” transistors. This is apparent particularly when trying to match gate-source voltage
VGS across a differential pair, or matching current across a current mirror.
Matching can present itself in the form of device orientation, interconnections, matching metal con-
nections, and reduction of unwanted parasitic capacitance/resistance.
3.2.1 Dummy Elements
Passive components can be matched by providing ”dummy elements”; added layers that have no
layout functionality or electrical connections. The purpose of including them is to provide symme-
try within an environment of components, improving the reliability and yield of the chip during
fabrication. For example, dummies can be utilized as shorted transistors.

3.3 Layout Methods
Two particular analog layout design methods will be discussed in detail pertaining to the layout
design of our op-amp.
3.3.1 Interdigitated Devices
A common example we will examine is matching two transistors with a common node:
Figure 11: Common-node Transistor Setup
The process gradint is almost evenly distributed between split-up devices A and B; we will say each
possess four fingers. The combined eight elements can be interdigitated into the following forms:
AABBAABB or ABBAABBA
3.3.2 Common-Centroid Devices
Using the same transistor configuration as described in Figure 11 (now using two finger), an al-
ternative design method known as common-centroid layout can be utilized. Its advantages are the
multitude of patterns/device organization and compensated process gradients.
It is important for devices organized in this manner to follow certain design rules including sym-
metry to both x and y axes, dispersion of elements within the ”array” whilst orienting the array
elements properly and making it as compact as possible.
A & B represent the active poly layer correlating to the respected transistor device. The follow-
ing figures below translate the interdigitated and common-centroid representations in the form of
a layout (note metal connections are not drawn to scale nor do they represent proper design rules,
strictly for presentation):
Figure 12: Interdigitated Layout Example Figure 13: Common-Centroid Layout Example

3.4 Stacked Layout
One of the most important stages of analog layout design is the setup of a stacked layout diagram.
Multi-finger common-width transistor devices can be ”stacked”.
The original schematic displayed in Figure 1 can be utilized for the stacked layout procedure. Com-
mon devices can be grouped together within the same stack; equivalent sizes must be considered for
critical transistors.
3.5 Stick Diagram
A stick diagram is composed of single poly line fingers with indicated drain and source connections.
This ”stick-like” figure can expand within multi-transitor schematics which we will use to break down
our op-amp.
Assuming the width of MOSFETs A and B within the schematic characeterized in Figure 11, the
stick diagram would correspond below:
Figure 14: Mult-Transistor Stick Diagram
3.6 Top Level Floorplan
A top level floorplan can be constructed from the given transistor sizes. As instructed we were allowed
to change the number of fingers per transistor while making sure each device’s W
L
ratio remained
the same. Due to unknown W
L
ratios from the used transistor values involved with the generated
simulation, i.e. Appendix tabulated values, and instead the values detailed in Figure 2 were used as
a starting point for a floorplan generation.
Figure 15: Schematic Grouping of Transistors for Top Level Floorplan

The image above details the grouping of transistors based on transistor type and dependency on
mirroring devices. This may not have been the most appropriate approach, however I will detail the
entire procedure and briefly discuss an alternative grouping method.
Several calculations were put into place to manipulate the existing values of the transistor dimen-
sions. As previously mentioned, transistor length/width as well as finger size could change as long
as the W
L
ratio remained the same. To ensure this, careful consideration was taken to provide an
equivalent amount of fingers across each side of the floorplan.
The figure below details the newly defined transistor dimension values:
Figure 16: Updated Values of Transistor Dimensions for Top Level Floorplan
The initial design decision had been to establish a common-centroid orientation across the entire
layout; symmetry conditions were established to mimic the particular layout finger placements.
It should be noted that the transistors connected to the compensation capacitor and bias resis-
tor, as well as devices involved with the structuring of the output buffer stage were all attached
separately. Consideration was taken with regards to the placement of each device within the floor-
plan. The output buffer devices were stationed at the top and bottom rows of the floor plan while
the remaining devices were placed on opposite sides attached to their relevant stage (device Q15
within the bias stage and device Q16 within the common-source gain stage).
Initially the first step was to assign 12 fingers to each of the devices within the differential pair (Q1
and Q2), as well as making it the center-point of the entire layout, i.e. establish common-centroid
symmetry matching with respect to the differential pair. Each device was assigned 12 fingers as per
its original standard. From this point on the top row of PMOS devices and bottom row of NMOS
devices (see grouping in Figure 15) were grouped and were set to total the same number of fingers
as the differential pair. Careful consideration was taken with regards to devices established within
a current mirror being identical, devices within a following stage having a larger number of fingers
than devices in prior stages, etc.
Devices involved within current mirrors shared equivalent dimensions and finger quantity. It was
important that critical devices involved within current mirrors were identical with each other. Inter-
digitated layout techniques were primarily used for the isolated differential pair.

In between the four symmetric 4-finger transistors were pairs that were cut down in finger size to
equal a total of 12 on the top and bottom row. The output buffer pair was a noticeable opportunity
for symmetry above and below the floorplan.
The main design decisions involved with the calculations surrounded the initial floorplan group-
ing as displayed in Figure 15. The detailed image below displays the full floorplan below:
Figure 17: Final Top Level Floorplan
3.7 Alternative Floorplan Design
As previously mentioned, there were slight issues involved with the original floorplan process. For
example, it was a challenge to distribute an equal number of fingers towards the devices within
each group of transistors, particularly with an uneven number of transistors between the NMOS and
PMOS row.
An alternative method would be further examination of the W
L
ratios of each device, as well as
a common factor between groups of transistors that can be used to determine the appropriate dis-
tribution of fingers among the grouped devices.
3.8 Layout Results
Initially the layout had been attempted using the updated transistor dimension values as seen in the
Appendix. Unfortunately, this caused many issues with regards to layout generation and editing.
Sizing and proper orientation was very small, and therefore this attempt was avoided.
Future plans are to enhance the initial floorplan and produce a functioning analog CMOS IC layout.
Layout design with original values would have to be considered due to the shortcomings I faced
during layout generation.

4 References
[1]: R. Amaya, ”Op-Amp Project v4”, 4609 IC Design and Fabrication, Accessed link:
https://culearn.carleton.ca/moodle/pluginﬁle.php/2959298/mod resource/content/2/ELEC4609 OpAm
5 Appendix
5.1 Alternate Transistor Sizing
Figure 18: Two-Stage Op-Amp Schematic Transistor Alternative Dimensions

CMOS Operational Amplifier Design

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