cmoslogic_data7.pdf
- 1. CMOS Logic Sudhanshu Janwadkar, Teaching Assistant, SVNIT, Surat Lecture Notes 16-17th February 2017
- 2. Introduction Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers of conducting and insulating materials to form a sandwich- like structure. These structures are manufactured using a series of chemical processing steps involving oxidation of the silicon, selective introduction of dopants, and deposition and etching of metal wires and contacts. CMOS technology provides two types of transistors: an n-type transistor (nMOS) and a p-type transistor (pMOS). Transistor operation is controlled by electric fields so the devices are also called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)
- 4. Introduction Each transistor consists of a stack of the conducting gate, an insulating layer of silicon dioxide (SiO2), and the silicon wafer, also called the substrate, or body, or bulk. An nMOS transistor is built with a p-type body and has regions of n-type semiconductor adjacent to the gate called the source and drain A pMOS consists of p-type source and drain regions with an n-type body. In a CMOS technology, with both flavors of transistors, the substrate is either n-type or p-type. The other flavor of transistor must be built in a special well in which dopant atoms have been added to form the body of the opposite type.
- 5. MOS Principle The gate is a control input: It affects the flow of electrical current between the source and drain.
- 6. N-channel MOSFET Consider an nMOS transistor. The body is generally grounded so the p–n junctions of the source and drain to body are reverse-biased. If the gate is also grounded, no current flows through the reverse-biased junctions. Hence, we say the transistor is OFF. If the gate voltage is raised, it creates an electric field that starts to attract free electrons to the underside of the Si–SiO2 interface. If the voltage is raised enough, the electrons outnumber the holes and a thin region under the gate called the channel is inverted to act as an n- type semiconductor. Hence, a conducting path of electron carriers is formed from source to drain and current can flow. We say the transistor is ON.
- 7. P-channel MOSFET For a pMOS transistor, The body is held at a positive voltage. When the gate is also at a positive voltage, the source and drain junctions are reverse-biased and no current flows, so the transistor is OFF. When the gate voltage is lowered, positive charges are attracted to the underside of the Si–SiO2 interface. A sufficiently low gate voltage inverts the channel and a conducting path of positive carriers is formed from source to drain, so the transistor is ON.
- 8. MOSFET as Switch The gate of an MOS transistor controls the flow of current between the source and drain Simplifying this to the extreme allows the MOS transistors to be viewed as simple ON/OFF switches. When the gate of an nMOS transistor is 1, the transistor is ON and there is a conducting path from source to drain. When the gate is low, the nMOS transistor is OFF and almost zero current flows from source to drain. A pMOS transistor is just the opposite, being ON when the gate is low and OFF when the gate is high.
- 10. CMOS Inverter When the input A is 0, the nMOS transistor is OFF and the pMOS transistor is ON. Thus, the output Y is pulled up to 1 because it is connected to VDD but not to GND. Conversely, when A is 1, the nMOS is ON, the pMOS is OFF, and Y is pulled down to ‘0.’ Schematic and Symbol for a CMOS inverter The bar at the top indicates VDD and the triangle at the bottom indicates GND.
- 11. CMOS NAND Gate Gate Schematic Symbol
- 12. CMOS NAND Gate It consists of two series nMOS transistors between Y and GND and two parallel pMOS transistors between Y and VDD. If either input A or B is 0: At least one of the nMOS transistors will be OFF, breaking the path from Y to GND. But at least one of the pMOS transistors will be ON, creating a path from Y to VDD. Hence, the output Y will be 1. If both inputs are 1, both of the nMOS transistors will be ON and both of the pMOS transistors will be OFF. Hence, the output will be 0.
- 13. CMOS NAND Gate
- 15. CMOS Logic Structure In general, a static CMOS gate has an nMOS pull-down network to connect the output to 0 (GND) and pMOS pull-up network to connect the output to 1 (VDD) In general, when we join a pull-up network to a pull-down network to form a logic gate, they both will attempt to exert a logic level at the output. The networks are arranged such that one is ON and the other OFF for any input pattern.
- 16. Connection and behaviour of series and parallel transistors
- 17. CMOS NOR Gate The nMOS transistors are in parallel to pull the output low when either input is high. The pMOS transistors are in series to pull the output high when both inputs are low
- 18. 3 input NOR Gate??
- 19. 3 input NOR Gate
- 20. 3 input NAND Gate??
- 21. 3 input NAND Gate
- 22. Compound Gates
- 25. Compound Gates
- 28. Pass Transistors and Transmission Gates The strength of a signal is measured by how closely it approximates an ideal voltage source. The power supplies, or rails, (VDD and GND) are the source of the strongest 1s and 0s. An nMOS transistor is an almost perfect switch when passing a 0 and thus we say it passes a strong 0. However, the nMOS transistor is imperfect at passing a 1. We say it passes a degraded or weak 1. An pMOS transistor is an almost perfect switch when passing a 1 and thus we say it passes a strong 1. However, the nMOS transistor is imperfect at passing a 1. We say it passes a degraded or weak 0
- 29. Pass Transistors and Transmission Gates Concept of Weak 1: Consider an nMOS transistor with the Gate and Drain tied to VDD. Imagine that the source is initially at Vs = 0. Vgs > Vtn, so the transistor is ON and current flows. If the voltage on the source rises to Vs = VDD – Vtn, Vgs falls to Vtn and the transistor cuts itself OFF. Therefore, nMOS transistors attempting to pass a 1 never pull the source above VDD – Vtn. This loss is called threshold drop.
- 30. Pass Transistors and Transmission Gates Concept of Weak 0: Similarly, pMOS transistors pass 1s well but 0s poorly. If the pMOS source drops below |Vtp|, the transistor cuts off. Hence, pMOS transistors only pull down to within a threshold above GND,
- 31. When an nMOS or pMOS is used alone as an imperfect switch, we call it a pass transistor. Pass Transistors and Transmission Gates
- 32. Pass Transistors and Transmission Gates By combining an nMOS and a pMOS transistor in parallel, we obtain a switch, which 0s and 1s are both passed in an acceptable fashion. We term this a transmission gate or pass gate.