Controller area network

Editor's Notes

• #5: The Identifier defines a static message priority during bus access. Nodes may be added to the CAN network without requiring any change in the software or hardware of any node or the application layer. As a consequence of the concept of Message filtering any number of nodes may receive and act simultaneously upon the same message. When the bus is free any node may start to transmit a message. The node with the message of highest priority to be transmitted gains bus access. To detect errors the following measures have been taken: • Monitoring (each transmitter compares the bit levels detected on the bus with the bit levels being transmitted) • Cyclic Redundancy Check (CRC) • Bit-Stuffing • Message Frame Check
• #7: Start of frame marks the beginning of Data frames and Remote frames. It consists of a single dominant bit. A node is only allowed to start transmission when the bus is idle. All nodes have to synchronize to the leading edge caused by Start of frame of the node starting transmission first.
• #9: In order to carry out the CRC calculation the polynomial to be divided is defined as the polynomial whose coefficients are given by the destuffed bit-stream consisting of Start of frame, Arbitration field, Control field, Data field(if present) and, for the 15 lowest coefficients, by 0. This polynomial is divided (the coefficients are calculated modulo-2) by the generator-polynomial: X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1 The CRC Sequence is followed by the CRC Delimiter which consists of a single recessive bit. A RECEIVER which has received a valid message correctly reports this to the TRANSMITTER by sending a dominant bit during the ACK Slot All nodes having received the matching CRC Sequence report this within the ACK Slot by overwriting the recessive bit of the TRANSMITTER by a dominant bit. The ACK Delimiter is the second bit of the ACK field and has to be a recessive bit. As a consequence, the ACK Slot is surrounded by two recessive bits.
• #10: Each Data frame and Remote frame is delimited by a flag sequence consisting of seven recessive bits.
• #12: There are two forms of error flag: an ACTIVE Error flag and a PASSIVE Error flag. 1) ACTIVE Error flag consists of six consecutive dominant bits. 2) The PASSIVE Error flag consists of six consecutive recessive bits unless it is overwritten by dominant bits from other nodes. There are two kinds of Overload condition, both of which lead to the transmission of an Overload flag: 1) Where the internal conditions of a receiver are such that the receiver requires a delay of the next Data frameor Remote frame, 2) On detection of a dominant bit during INTERMISSION. The Error Delimiter consists of eight recessive bits.
• #13: Data frames and Remote frames are separated from preceding frames, whatever type they may be (Data frame, Remote frame, Error frame, Overload frame), by a field called Interframe space. In contrast, Overload frames and Error frames are not preceded by an Interframe space and multiple Overload frames are not separated by an Interframe space.
• #14: provides an extra delay between successive Data or remote frames. An Overload Frame can be generated by a node either when a dominant bit is detected during Interframe Space or when a node is not ready to receive the next message
• #15: •Synchronization Segment – This time segment synchronizes the different nodes connected on the CAN bus. A bit edge is expected to be within this segment. Based on CAN protocol, the Synchronization Segment is assumed to be 1 TQ. •Propagation Segment – This time segment compensates for any time delay that may occur due to the bus line or due to the various transceivers connected on that bus. •Phase Segment 1 – This time segment compensates for errors that may occur due to phase shift in the edges. The time segment may be lengthened during resynchronization to compensate for the phase shift. •Phase Segment 2 – This time segment compensates for errors that may occur due to phase shift in the edges. The time segment may be shortened during resynchronization to compensate for the phase shift. The Phase Segment 2 time can be configured to be either programmable or specified by the Phase Segment 1 time.