Cpu register, instruction exucution and interrupts unit 1 by ram k paliwal
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The document discusses CPU registers, instruction execution, and interrupts in operating systems, detailing various types of registers and their roles during instruction execution cycles. It explains the instruction execution process, including fetching and executing instructions, as well as distinguishing between hardware and software interrupts. Additionally, it covers different classes of interrupts and the sequence of events triggered by them.
Cpu register, instruction exucution and interrupts unit 1 by ram k paliwal
- 1. Unit -1 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS IN OPERATING SYSTEM BY RAM K PALIWAL 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 1
- 2. CPU Register CPU registers The registers vary in number and type, depending on the computer architecture. ◦ Accumulators ◦ Index registers ◦ Stack pointers ◦ General-purpose registers ◦ condition-code information registers. When any process is running along with the program counter, this state information (CPU register information) must be saved when an interrupt occurs, to allow the process to be continued correctly afterward 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 2
- 3. Instruction Execution 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 3 All computers have an instruction execution cycle. A basic instruction execution cycle can be broken down into the following steps: 1. Fetch cycle 2. Execute cycle
- 4. Instruction Execution The fetched instruction is loaded into the instruction register (IR). The instruction contains bits that specify the action the processor is to take. The processor interprets the instruction and performs the required action. In general, these actions fall into four categories: 1. Processor-memory: Data may be transferred from processor to memory or from memory to processor. 2. Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module. 3. Data processing: The processor may perform some arithmetic or logic operation on data. 4. Control: An instruction may specify that the sequence of execution be altered. 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 4
- 5. Interrupts Virtually all computers provide a mechanism by which other modules (I/O, memory) may interrupt the normal sequencing of the processor. Interrupts are provided primarily as a way to improve processor utilization. For example, most I/O devices are much slower than the processor. Types of Interrupts: Hardware Software 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 5
- 6. Interrupts Hardware Interrupts: If the signal for the processor is from external device or hardware is called hardware interrupts. Example: from keyboard we will press the key to do some action this pressing of key in keyboard will generate a signal which is given to the processor to do action, such interrupts are called hardware interrupts. Hardware interrupts can be classified into two types they are ◦ Maskable Interrupt: The hardware interrupts which can be delayed when a much highest priority interrupt has occurred to the processor. ◦ Non Maskable Interrupt: The hardware interrupts which cannot be delayed and should process by the processor immediately. 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 6
- 7. Interrupts Software Interrupts: Software interrupt can also divided in to two types. ◦ Normal Interrupts: the interrupts which are caused by the software instructions are called software instructions. ◦ Exception: unplanned interrupts while executing a program is called Exception. For example: while executing a program if we got a value which should be divided by zero is called a exception. 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 7
- 8. Interrupts Classes of Interrupt Program: Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, and reference outside a user’s allowed memory space. Timer: Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis. I/O: Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions Hardware Failure: Generated by a failure, such as power failure or memory parity error. 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 8
- 9. Interrupt Processing An interrupt triggers a number of events, both in the processor hardware and in software. Figure shows a typical sequence. When an I/O device completes an I/O operation, the following sequence of hardware events occurs: 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 9
- 10. Interrupt Processing 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 10
- 11. References 1. Operating System Concept ninth Edition by Abraham Silberschatz and Galvin 2. Operating Systems, internals and Design Principles, sixth edition by William Stalling 9/3/2019 CPU REGISTER, INSTRUCTION EXECUTION AND INTERRUPTS- UNIT 1- BY RAM K PALIWAL 11
Editor's Notes
- #4: The two steps are referred to as the fetch stage and the execute stage. Program execution halts only if the processor is turned off, some sort of unrecoverable error occurs, or a program instruction that halts the processor is encountered. At the beginning of each instruction cycle, the processor fetches an instruction from memory. Typically, the program counter (PC) holds the address of the next instruction to be fetched. Unless instructed otherwise, the processor always increments the PC after each instruction fetch so that it will fetch the next instruction in sequence (i.e., the instruction located at the next higher memory address). For example, consider a simplified computer in which each instruction occupies one 16-bit word of memory. Assume that the program counter is set to location 300. The processor will next fetch the instruction at location 300. On succeeding instruction cycles, it will fetch instructions from locations 301, 302, 303, and so on. This sequence may be altered, as explained subsequently.
- #5: Control: An instruction may specify that the sequence of execution be altered. For example, the processor may fetch an instruction from location 149, which specifies that the next instruction be from location 182. The processor sets the program counter to 182. Thus, on the next fetch stage, the instruction will be fetched from location 182 rather than 150.
- #10: 1. The device issues an interrupt signal to the processor. 2. The processor finishes execution of the current instruction before responding to the interrupt. 3. The processor tests for a pending interrupt request, determines that there is one, and sends an acknowledgment signal to the device that issued the interrupt. The acknowledgment allows the device to remove its interrupt signal. The processor next needs to prepare to transfer control to the interrupt routine. To begin, it saves information needed to resume the current program at the point of interrupt. The minimum information required is the program status word (PSW) and the location of the next instruction to be executed, which is contained in the program counter. These can be pushed onto a control stack. 5. The processor then loads the program counter with the entry location of the interrupt-handling routine that will respond to this interrupt. Depending on the computer architecture and OS design, there may be a single program, one for each type of interrupt, or one for each device and each type of interrupt. If there is more than one interrupt-handling routine, the processor must determine which one to invoke. This information may have been included in the original interrupt signal, or the processor may have to issue a request to the device that issued the interrupt to get a response that contains the needed information.
- #11: 6. At this point, the program counter and PSW relating to the interrupted program have been saved on the control stack. However, there is other information that is considered part of the state of the executing program. In particular, the contents of the processor registers need to be saved, because these registers may be used by the interrupt handler. So all of these values, plus any other state information, need to be saved. 7. The interrupt handler may now proceed to process the interrupt.This includes an examination of status information relating to the I/O operation or other event that caused an interrupt. It may also involve sending additional commands or acknowledgments to the I/O device. 8. When interrupt processing is complete, the saved register values are retrieved from the stack and restored to the registers. 9. The final act is to restore the PSW and program counter values from the stack. As a result, the next instruction to be executed will be from the previously interrupted program.