Create your first model for a simple logic circuit
- 1. VHDL 360©by: Mohamed Samy Samer El-Saadany
- 2. CopyrightsCopyright © 2010 to authors. All rights reservedAll content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Mohamed Samy and Samer El-Saadany or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws.Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses.Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners.VHDL 360 ©2
- 3. Module 1Create your first model for a simple logic circuit
- 4. ObjectiveCreate your first VHDL model for simple logic circuitsSkills gained:Know the basic structure of a VHDL model (entity, architecture)Model simple combinational logicVHDL 360 ©4
- 6. With-Select
- 8. VHDL Design UnitsAfter understanding our first model*, let’s move forward & understand how to construct one6VHDL 360 ©*Module 0: Introduction to VHDL
- 9. VHDL Design UnitsA VHDL Model (Design unit) consists of:EntityDefine ports (inputs and outputs)ArchitectureDefine operation (input/output relation)VHDL 360 ©7
- 10. Entity Descriptionentity <entity_name> isport ( <port_name> : <mode> <type>; <port_name> : <mode> <type>;…-- last port has no semicolon <port_name> : <mode> <type> );Endentity;8VHDL 360 ©<mode>: port directionIN: Input that can only be readOUT: Output that can only be written toINOUT: Input or output can be read and written toSyntax:Example:ENTITY model1 IS--VHDL is case insensitivePORT( a :INstd_logic; b :INstd_logic; c :INstd_logic; d :INstd_logic; e :OUTstd_logic);END model1 ;
- 11. Entity Description9VHDL 360 ©Bit values:‘0’ --Binary Zero‘1’ -- Binary OneStd_logic values‘U’ -- Uninitialized‘X’ -- Forcing Unknown‘0’ --Forcing Zero‘1’ -- Forcing One‘Z’ -- High Impedance‘W’ -- Weak Unknown‘L’ -- Weak Zero‘H’ -- Weak One‘-’ -- Don’t CareTypes:VHDL offers the following standard types:Integer: -231 to 231-1Bit, Bit_vector…IEEE Packages offer more types:Std_logic, std_logic_vector…Require use of appropriate IEEE packagesExample: Using Standard TypesExample: Using IEEE TypesLIBRARY ieee; USE ieee.std_logic_1164.all;ENTITY model1 ISPORT( a :INstd_logic;b :INstd_logic; c :INstd_logic; d :INstd_logic; e:OUTstd_logic_vector(7 downto 0));END model1 ;ENTITY model1 IS PORT( a :INbit_vector(3 downto 0);b :INbit; c :INbit; d :INbit; e :OUTbit);END model1 ;
- 12. Exercise 1Write the entity of the following:1-bit Full Adder10VHDL 360 ©
- 13. Answer of Exercise 1 11VHDL 360 ©LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITYfullAdderIS PORT( In1, In2, CarryIn:INstd_logic;Sum :OUTstd_logic;CarryOut:OUT std_logic);ENDfullAdder;
- 14. Architecture Descriptionarchitecture <arch_name> of <entity_name> is-- architecture declarations begin-- architecture bodyendarchitecture;12VHDL 360 ©Syntax:A given architecture represents one possible implementation for its associated entityArchitecture declaration: defines internal signals, components, types …etc to be used in architecture bodyArchitecture body: defines implementation details of input/output relationshipMultiple architectures can exist for each entityExample:Internal signalsARCHITECTURErtlOF model1 ISSIGNAL x :std_logic;SIGNAL y :std_logic;BEGIN x <= a AND b; y <= c AND d; e <= x OR y;ENDrtl;signal <sig_name>: <sig_type>;Concurrent Assignments
- 15. Architecture Body<target> <= <expression>;13VHDL 360 ©Architecture body can only contain concurrent statements, in this module we will only focus onConcurrent assignmentsWith-selectWhen-elseConcurrent AssignmentsLHS can be an internal signal or an output portRHS is an expression that operates on internal signal and/or input portsSyntax:Example:ARCHITECTUREexprOF example1 ISSIGNAL u, w, x, y, z :std_logic;SIGNAL a, b, c :integer;BEGIN x <= y AND z;-- logical expression w <=NOT x; u <= w;-- direct assignment c <= a + b;-- arithmetic expressionENDexpr;Arithmetic Operators+ , - , * , /Logical OperatorsNOTAND, NANDOR, NORXOR, XNOR
- 16. Internal signalsWe use Internal Signals for:Internal connections in structural descriptionIntermediate calculationsAvoid illegal port usage situations:Read Output portSyntax:architecture <arch_name> of <entity_name> is-- architecture declarations signal <sig_name>: <sig_type>;begin-- assign to internal signal<sig_name> <= <expression>;-- read the internal signal<sig_name> <= <expression>;endarchitecture;Example:LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY illegal ISPORT( A :INstd_logic; B :INstd_logic; C :INstd_logic; F :OUTstd_logic; G :OUTstd_logic);END illegal ;ARCHITECTUREstructOF illegal IS -- Internal signal declarationsSIGNAL sig1 :std_logic;SIGNAL sig2 :std_logic;SIGNAL sig3 :std_logic;BEGIN F <= sig3 AND sig1 AND C; G <= F AND sig1 AND sig2;-- Reading Out port F is illegal sig3 <=NOT(A);sig1 <=NOT(B); sig2 <=NOT(C);ENDstruct;Illegal use of an output port(used as the “and” gate input)14VHDL 360 ©
- 17. Internal signalsExample:LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_arith.all;ENTITY legal ISPORT( A :INstd_logic; B :INstd_logic; C :INstd_logic; F :OUTstd_logic; G :OUTstd_logic);END legal ;ARCHITECTUREstructOF legal IS -- Internal signal declarationsSIGNAL sig1 :std_logic;SIGNAL sig2 :std_logic;SIGNAL sig3 :std_logic;SIGNAL sig4 :std_logic;BEGIN sig4 <= sig3 AND sig1 AND C;-- using internal signal sig4 G <= sig4 AND sig1 AND sig2; F <= sig4; sig3 <=NOT(A);sig1 <=NOT(B); sig2 <=NOT(C);ENDstruct;Internal Signals used for intermediate relations15VHDL 360 ©
- 18. Expressions & Operators16VHDL 360 ©Each operator is defined for specific data type(s)Arithmetic operators are defined for standard integer typesLogical operators are defined for the standard bit, bit_vector typesLogical & arithmetic operators are defined for std_logic & std_logic_vector types in IEEE std_logic_* packages You need to use the appropriate package before applying an operator on a typeExample:ARCHITECTUREstructOFexprIS -- Internal signal declarations SIGNAL x, y, z :integer;BEGIN-- Operators can be chained to form complex expressions F <= C AND (NOT(B)) AND (NOT(A));-- parentheses control association of operators and operands-- use parentheses for readability G <= (COR (NOT(A)))XOR(NOT(B) AND(BNORC)); Z <= X + Y; -- using addition operator defined for integer typeENDstruct;
- 19. Operators*17VHDL 360 ©*More operator will be presented throughout the course
- 20. Operators18VHDL 360 ©Example:-- Library & package used for architecture scopeLIBRARY ieee; USE ieee.std_logic_unsigned.all; -- Need to use unsigned arithmetic operatorsARCHITECTUREexprOF example1 ISSIGNAL u, w :std_logic_vector(3 downto 0);SIGNAL a :integer;BEGIN-- Adding an integer to an std_logic_vector returning std_logic_vector u <= w + a;ENDexpr;Where’s the Carry Out?!
- 21. Exercise 2Write the architecture of the following:1-bit Full Adder19VHDL 360 ©
- 22. Answer of Exercise 2 20VHDL 360 ©LIBRARY ieee; USE ieee.std_logic_1164.all;ENTITYfullAdderIS PORT( In1, In2, CarryIn:INstd_logic;Sum :OUTstd_logic;CarryOut:OUT std_logic);ENDfullAdder;ARCHITECTUREexprOFfullAdderIS signal temp :std_logic;BEGINtemp <=In1 XOR In2; Sum <= temp XORCarryIn;CarryOut<= (In1 AND In2) OR (CarryInAND temp);ENDexpr;
- 23. 21VHDL 360 ©abFcdSel(1:0)Architecture BodyWith-Select<select_signal> can be an internal signal or an input port<target> can be an internal signal or an output port<value> constants representing one of possible <select_signal> values.“When others” is a must if not all values of <select_signal> are coveredSyntax:With <select_signal> select <target> <= <expression> when <value>, <expression> when <value>, …. < expression> whenothers;Example:Architecture behave ofmux_withisBeginWithselselect F <= a when"00", b when"01", c when"10", d whenothers; -- needed to cover missing “sel” valuesEndArchitecture;
- 24. 22VHDL 360 ©abFcdSel(1:0)Architecture BodyWhen-elseLHS can be an internal signal or an output portRHS is an expression that operates on internal signal and/or input ports when the branch condition is trueLast “else” branch covers all missing conditionsSyntax:<target> <= <expression> when <condition>else <expression> when <condition>else <expression> when <condition> …else<expression> ;Example:Architecture behave ofmux_whenisBeginF <= a whensel="00"else b whensel="01"else c whensel="10"else d;-- This is one statement with semicolon at the end onlyEndArchitecture;
- 25. Exercise 3 aF24Fa42Write the entity and architecture of the following (using with-select then using when-else):2x4 Decoder4x2 EncoderEncoder4x2Decoder2x423VHDL 360 ©
- 26. Decoder 2x4(with-select)aF24libraryIEEE;useIEEE.std_logic_1164.all;entity decoder2x4 isport(a:instd_logic_vector(1downto0); F:outstd_logic_vector(3downto0));endentity;Architecture behave of decoder2x4 isBegin with A select F <="0001"when"00","0010"when"01", "0100"when"10", "1000" when others;EndArchitecture;24VHDL 360 ©
- 27. Decoder 2x4 (when-else)aF24libraryIEEE;useIEEE.std_logic_1164.all;entity decoder2x4 isport(a:instd_logic_vector(1downto0); F:outstd_logic_vector(3downto0));endentity;Architecture behave of decoder2x4 isBegin F <="0001" when a ="00"else "0010"when a ="01"else "0100" when a ="10"else "1000";EndArchitecture;25VHDL 360 ©
- 28. Encoder4x2 (with-select)Fa24libraryIEEE;useIEEE.std_logic_1164.all;entity encoder4x2 is port(a:instd_logic_vector(3downto0); F:outstd_logic_vector(1downto0));endentity;Architecture behave of encoder4x2 isBeginWith a select F <="00"when"0001","01"when"0010", "10"when"0100", "11"whenothers;EndArchitecture;26VHDL 360 ©
- 29. Next ModuleModule 2: Writing more complex ModelsVHDL 360 ©27
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