CROSSTALK MINIMIZATION FOR COUPLED RLC INTERCONNECTS USING BIDIRECTIONAL BUFFER AND SHIELD INSERTION

International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
DOI : 10.5121/vlsic.2013.4304 31
CROSSTALK MINIMIZATION FOR COUPLED
RLC INTERCONNECTS USING BIDIRECTIONAL
BUFFER AND SHIELD INSERTION
Damanpreet Kaur and V.Sulochana
Centre for Development of Advanced Computing (C-DAC) Mohali, India
damannrng@gmail.com, vemus@cdac.in
ABSTRACT
Crosstalk noise is often induced in long interconnects running parallel to each other. There is a need to
minimize the effect of these crosstalk noise so as to maintain the signal integrity in interconnects. In this
paper crosstalk noise is minimized using various techniques such as repeater (bidirectional buffer)
insertion along with shielding, skewing and shielding & skewing simultaneously. With the help of these
techniques crosstalk noise is controlled to a great extent in long interconnects. Pre-layout and Post-layout
simulations for crosstalk are carried out for these techniques at 180nm technology node using Cadence
EDA tools. The influences of these techniques are analyzed and it is found that crosstalk is reduced up to
32 % with repeater insertion, 47% with skewing, 58% with shielding and 81% with skewing & shielding
simultaneously.
KEYWORDS
Crosstalk, Bidirectional Buffer, Shielding, Skewing.
1. INTRODUCTION
The feature size of integrated circuits has been reduced in the search of enhanced speed, power,
silicon area and cost characteristics [1]. Semiconductor technologies with feature sizes of several
tens of nanometers are currently in progress. As per, International Technology Roadmap for
Semiconductors (ITRS), the future nanometer scale circuits will contain large number of
transistors on single chip and operate at clock speeds well over high frequencies. Distributing
robust and reliable power, ground and other control signals through interconnects in such a high-
speed, high-complexity.
Environment is quite a challenging task. The performance of a high-speed chip is dependent on
interconnects, which connect different cells within a VLSI chip. With ever-growing length of
interconnects and frequency in a chip, the effects of interconnects cannot be constrained to RC
models alone. The importance of on-chip inductance is continuously increasing and the
introduction of new materials for low resistance interconnects is in progress. Now a days
interconnect delay dominates gate delay in current deep sub micrometer VLSI circuits [2]. With
the continuous scaling of technology and increased die area, this behavior is expected to continue.
Wide wires are frequently found in global and semi-global interconnects in upper metallic layers.
These wires are low resistive lines that can have significant inductive effects. Owing to presence

32
of these inductive effects, the new generation VLSI designers have been forced to model
interconnects as distributed RLC models [3]. These RLC line when running parallel to each other
have capacitive coupling, which makes the design of interconnects even more important in terms
of crosstalk. Many of the research work have been aimed at reducing delay and power dissipation
only [4]. Crosstalk noise effects have not been given generally much concern. In a modern
interconnect design, interconnects in an adjacent metal layers are tried to keep orthogonal to each
other. This is done to reduce crosstalk as much as possible. But with growing interconnect density
and reduced chip size, even the non-adjacent interconnects exhibit significant coupling effects.
The impact of this has made on chip’s performance of concern in todays design era. The effect of
crosstalk induced overshoot generated at a noise-site. The peak overshoot generated at a noise-
site can wear out the thin gate oxide layer resulting in permanent failure of the chip [5]. This
problem will be noteworthy as the feature size of transistor reduces with advancement of
technology. Drawing out exact values of capacitance and inductance induced noise for an
interconnect is a very challenging task. For an on-chip interconnect, the different performance of
capacitive noise must be taken into consideration. As we know electrostatic interaction between
wires is of very short range, consideration of only nearest interconnects provides sufficient
accuracy for capacitive coupled noise.
General methods for reducing the effects of crosstalk include bus encoding [6–9], wire spacing
adjustments [10], buffer insertion [11], and shielding [12].In this paper buffer insertion, skewing,
shielding and skewing & shielding simultaneously has been considered for minimizing crosstalk.
1.1 Repeater Insertion
Uniform repeater insertion is an efficient technique for driving long interconnects. Uniform
repeater insertion technique divides the interconnect into equal sections and make use of equal
size repeaters to drive each section [5]. The primary objective of a uniform repeater insertion
system is to minimize the time for a signal to propagate through a long interconnect. In this paper
it is revealed that inserting repeaters, other than fulfilling its primary goal reduces crosstalk levels
also.
1.2 Skewing
In this paper crosstalk is reduced using system resource that is time. Time or timing slack has
been previously used in buses [13, 14], where the delay of a coupled bus was reduced by
intentionally skewing the timing of adjacent wires. Skewing was applied to reduce the energy
dissipation of a coupled bus [15] and was used to reduce bus peak power [16]. In this crosstalk
voltage induced on quiet victim wires is reduced as proposed in [17].
1.3 Shielding
Shield insertion is an effective method to reduce crosstalk noise and signal delay uncertainty and
has become common practice when routing critical signal and power lines [18]. Inserting shield
lines can greatly reduce capacitive coupling [19] by providing a closer current return path for
both the interconnect lines.
The remainder of the paper is organized as follows. Section II provides present work
implementing crosstalk reduction techniques and discusses obtained results. Finally, conclusions
are drawn.

2. RELATED WORK
Tianpei Zhang et.al[11] presents a method for incorporating crosstalk reduction criteria into
global routing under a broad power supply network paradigm. This method utilizes power/ground
wires as shields between signal wires to reduce capacitive coupling, while considering the
constraints imposed by limited routing and buffering resources. An iterative procedure is
employed to route signal wires, assign supply shields, and insert buffers so that both
buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and
buffer insertion are considered simultaneously via a dynamic programming
calculations are based on Devgan’s metric, and the work demonstrat
metric shows good fidelity on average. An effective noise margin inflation technique is also
proposed to compensate for the pessimism of Devgan’s metric. Experimental results on test cases
with up to about 10 000 nets poin
number of nets.
Gargi Khanna and Rajeevan Chandel[20]
(both active gate and passive capacitive loads) on the nonideal effects of a coupl
interconnect system. Signal delay, power dissipation and crosstalk noise in interconnect can be
influenced by variation in load of another interconnect which is coupled to it. For active gate and
passive capacitive load variations, such effects are
coupled interconnect pair in a 0.13mm technology. Crosstalk between a coupled pair, is affected
by transition time of the coupled signal, interconnect length, distance between interconnects, size
of driver and receiver, pattern of input, direction of flow of signal and clock skew. In this work,
influence of aggressor-line load variations (both active gate and passive capacitive loads) on the
non-ideal effects of delay, power consumption and crosstalk in a victim
interconnect system are determined through SPICE simulation. In this experiment, the victim line
is terminated by a fixed capacitive load and the coupled to aggressor line has variable load, either
passive capacitive or active gate. Distr
considered for the SPICE simulations
3. PRESENT WORK AND
In this paper RLC interconnect model as in Figure 1. is used to study the effect of crosstalk. RLC
parameter values are obtained from ptm models
RLC interconnect model analysis
Figure 2. It is observed that at 1GHz signal is distorted which may lead to degradation of signal.
So there is a need to maintain the signal integrity which is done using repeater insertion.
presents a method for incorporating crosstalk reduction criteria into
between signal wires to reduce capacitive coupling, while considering the
r/routing capacity and signal integrity goals are met. In each iteration, shield assignment and
buffer insertion are considered simultaneously via a dynamic programming-like approach. Noise
calculations are based on Devgan’s metric, and the work demonstrates, for the first time, that this
with up to about 10 000 nets point towards an asymptotic runtime that increases linearly with the
Gargi Khanna and Rajeevan Chandel[20] analyzes the effects of aggressor-line load variations
(both active gate and passive capacitive loads) on the nonideal effects of a coupl
passive capacitive load variations, such effects are studied through SPICE simulations of a
er, pattern of input, direction of flow of signal and clock skew. In this work,
line load variations (both active gate and passive capacitive loads) on the
ideal effects of delay, power consumption and crosstalk in a victim-line of a coupled VLSI
passive capacitive or active gate. Distributed RLC transmission model of interconnect is
considered for the SPICE simulations.
ND ANALYSIS
parameter values are obtained from ptm models R= 36.666ohms, L= 1.8358nH and C=82.932fF.
Figure1. RLC interconnect model
RLC interconnect model analysis has been done and simulation results at 1GHz are shown in
33
presents a method for incorporating crosstalk reduction criteria into
between signal wires to reduce capacitive coupling, while considering the
r/routing capacity and signal integrity goals are met. In each iteration, shield assignment and
like approach. Noise
es, for the first time, that this
t towards an asymptotic runtime that increases linearly with the
line load variations
(both active gate and passive capacitive loads) on the nonideal effects of a coupled VLSI-
studied through SPICE simulations of a
er, pattern of input, direction of flow of signal and clock skew. In this work,
line load variations (both active gate and passive capacitive loads) on the
of a coupled VLSI-
ibuted RLC transmission model of interconnect is
= 36.666ohms, L= 1.8358nH and C=82.932fF.
has been done and simulation results at 1GHz are shown in

Figure 2 .
Figure 3. RLC interconnect model layout
Bidirectional buffers are used in programmable logic devices for amplifying a signal on a line
wherein signal flow may be in either direction on line [20]. In this paper Bidirectional buffer is
designed as a repeater in RLC interconnects. This bidirection
buffers and invertors. Control input pin decides the direction of signal flow as in Table 1.
Table 1. Bidirectional Buffer direction
Control
1
0
Figure 4.Bidirectional buffer using tristate buffers and invertors
In Figure 4. Bidirectional Buffer is designed as a repeater at 1GHz in both directions as per input
to control signal. Figure 5. shows when control is high signal flows from A to B and Figure 6.
shows when control is low signal flows from B to A in bidirectional buffer.
e 2 .RLC interconnect simulations at 180nm
Figure 3. RLC interconnect model layout
designed as a repeater in RLC interconnects. This bidirectional buffer is made up of tri
Table 1. Bidirectional Buffer direction
Direction of bidirectional buffer
A to B
B to A
4.Bidirectional buffer using tristate buffers and invertors
hows when control is low signal flows from B to A in bidirectional buffer.
34
al buffer is made up of tri-state

Figure 5. Bidirectional Buffer from A to B
Figure 6. Bidirectional Buffer from B to A
In Figure 7. bidirectional buffer is designed and is inserted as repeater in RLC
model. Ctrl pin determines the condition of signal flow either from A to B or vice versa.
Figure 7. Bidirectional buffer insertion in interconnects
Figure 8. shows the layout of buffer insertion in interconnects at 180nm. Bidirectional buf
placed at extreme ends with RLC in between them.VDD supply and GND pins are shown in
layout.
Figure 8. Layout of Bidirectional buffer insertion in interconnects
Figure 5. Bidirectional Buffer from A to B
Figure 6. Bidirectional Buffer from B to A
In Figure 7. bidirectional buffer is designed and is inserted as repeater in RLC interconnect
Figure 7. Bidirectional buffer insertion in interconnects
Figure 8. shows the layout of buffer insertion in interconnects at 180nm. Bidirectional buf
Figure 8. Layout of Bidirectional buffer insertion in interconnects
35
interconnect
Figure 8. shows the layout of buffer insertion in interconnects at 180nm. Bidirectional buffer are

Transient analysis of this bidirectional buffer is inserted in RLC interconnect model
in Figure 9. It is observed in Figure 9. that with buffer insertion in RLC signal has restored to
great extent.
Figure 9 . Bidirectional Buffer insertion in interconnects
Two parallel interconnect lines are considered along with coupling
effect of crosstalk in interconnects as in Figure 10. Value of coupling capacitance as per ptm
model is chosen to be 88.37fF. The crosstalk is measured with these circuits with voltage sources
switching in same and in opposite dir
as critical node in terms of crosstalk.
Figure 10. Coupling in interconnects
Figure 11. Layout depicting coupling in interconnects
Due to coupling capacitance crosstalk is observed at the i
when there is switching of voltage drivers in same direction crosstalk observed is less and when
they are switching in opposite directions crosstalk observed is more.
Transient analysis of this bidirectional buffer is inserted in RLC interconnect model
Figure 9 . Bidirectional Buffer insertion in interconnects
Two parallel interconnect lines are considered along with coupling capacitances to study the
switching in same and in opposite directions at the receiving buffer input node being referred to
as critical node in terms of crosstalk.
Figure 11. Layout depicting coupling in interconnects
Due to coupling capacitance crosstalk is observed at the input of receiver driver. It is found that
they are switching in opposite directions crosstalk observed is more.
36
obtained is as
capacitances to study the
ections at the receiving buffer input node being referred to
It is found that

Crosstalk induced in circuits due to adjacent interconnects may distort the original signal so it is
undesirable in circuits. To minimize this crosstalk minimization technique such as shielding is
implemented in Figure 13. In this ground lines are placed a
the crosstalk by providing a closer current return path for both the interconnect lines.
Figure 13. Shielding in interconnects
implemented in Figure 13. In this ground lines are placed around the victim lines so as to reduce
Figure 13. Shielding in interconnects
37
round the victim lines so as to reduce

38
Figure 14. Shielding technique in interconnects
Figure 15. Shielding in interconnects layout
Skewing, one of the technique to reduce crosstalk is also implemented. In this delay time of
500ps is inserted, so that delay is introduced between the switching times of the drivers which
may lead to reduction of crosstalk.
Figure 16. Skewing technique in interconnects

39
Further crosstalk reduction is implemented using both skewing and shielding techniques
simultaneously in by inserting delay time of 500ps in Figure 13. It is observed that crosstalk is
reduced maximum in this case.
Figure 17. Shielding and skewing simultaneously technique in interconnects
Techniques such as skewing, shielding and skewing & shielding simultaneously reduces the
crosstalk. The maxima of the signal is calculated at critical node and crosstalk values at prelayout
and postlayout simulations are as shown in Table 2.
TABLE 2. Crosstalk values at different techniques
Direction of
bidirectional
buffer
Layout Switching
direction
RLC
coupling
shielding skewing Skewing &
shielding
A to B
Pre-
layout
same 1.270 V 1.210V 1.196V 1.166V
opposite 1.607V 1.212V 1.26V 1.169V
B to A Same 1.270V 1.210V 1.196V 1.164V
opposite 1.607V 1.212V 1.259V 1.169V
A to B
Post-
layout
Same 1.282 V 1.213V 1.201V 1.168V
Opposite 1.794V 1.214V 1.214V 1.172V
B to A Same 1.282V 1.213V 1.201V 1.168V
opposite 1.794V 1.214V 1.214V 1.172V.

40
4. CONCLUSIONS
In order to reduce crosstalk noise, bidirectional buffer operating at 1 GHz frequency is proposed
along with buffer insertion and various techniques such as shielding, skewing so as to reduce the
crosstalk noise. The proposed buffer also helped to reduce delay. It was observed that crosstalk
noise is effectively reduced with these techniques and delay is reduced by 34% with buffer
insertion. Thus through the various results obtained using cadence at 180 nm technology node
crosstalk is analyzed and reduced through different techniques up to 32% with repeater
insertion,47% with skewing, 58% with shielding and 81% with skewing &shielding
simultaneously.
5. FUTURE DEVELOPMENT OF THIS WORK AND APPLICATION AREAS
Crosstalk minimization techniques can be implemented in SOC (system on chip) circuits.
Crosstalk degrades the signal integrity which is not desirable for reliable VLSI circuits.Since
logic of the signal must be maintained for functionality of various analog and digital circuits so its
necessary to reduce the effect of crosstalks due to interconnects on ICs.
ACKNOWLEDGEMENTS
We would like to extend a special thanks to C-DAC Mohali for providing us means to carry out
our research work in meticulous way. We are also grateful to MHRD, Govt of india for providing
us a platform to do our research work.
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Authors
Damanpreet Kaur is pursuing Masters of Technology at C-DAC Mohali in VLSI
Design. She has obtained her Bachelor of Engineering degree in Electronics &
Communication Engineering from Punjab technical University, Jalandhar in 2011. Her
research interests include Digital & Analog VLSI Design. Her email-id is
damannrng@gmail.com.
Vemu Sulochana has obtained her Bachelor of Technology degree from JNTU
Kakinada and Master of Technology degree from NIT, Hamirpur in 2004 and 2009
respectively. In 2011, she joined C-DAC, Mohali to conduct innovative research in the
area of VLSI design, where she is now a Project Engineer - II. Her research is
concerned with low power VLSI design, Design of high speed VLSI interconnects. She
is conducting research in IC interconnect characterization, modeling and simulation for
the high speed VLSl circuit design. Her email-id is vemus@cdac.in

CROSSTALK MINIMIZATION FOR COUPLED RLC INTERCONNECTS USING BIDIRECTIONAL BUFFER AND SHIELD INSERTION

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