Design of 17-Bit Audio Band Delta-Sigma Analog to Digital Converter

Design of 17-Bit Audio Band Delta-Sigma Analog to Digital Converter
Karthikvel Rathinavel
rathinak@oregonstate.edu
Oregon State University
June 02, 2016
A. Introduction
This report discusses the design approach for an
Analog to digital delta sigma converter. The
systematic design approach followed for designing
the ADC converter is unique for the given
specifications. The report outlines the initial
considerations for the given specifications and the
choice of architecture. It also discusses the
simulation results of the output spectrum for the top
level blocks and the effect of non-idealities.
B. Design approach and choice of form
My initial design approach was to set the parameters
such Peak SQNR, Order, quantizer resolution based
on the empirical data. Taking into account the
thermal noise and the quantizer noise, I made a rough
estimate of the Peak SQNR.
= 6.02 + 1.76
~ + 10 log( ) + . 20. log( )
Next, I decided my Order and Quantizer Resolution
according to the OSR and the rough estimate of the
Peak SQNR. I calculated OSR to the nearest binary
exponent. For a clock frequency of 5.2 MHz, I was
able to obtain an OSR of 128.
=
2
For a given Order, OSR and quantizer resolution,
there are many possible modular architectures that
can be followed. I used a Cascade of Integrators
Feedforward Form (CIFF), because it inherently
possess a lower thermal noise for the first integrator.
Thus we get lower capacitances and hence lower chip
area when it is implemented in transistor level. In
addition, by using CIFF structure, we have only one
feedback path. The feedforward paths sums all the
signals coming from the delaying integrators, before
the input of the quantizer. This leads to lower
harmonic distortion. Also the amplifier’s slew rate
can be considerably reduced in CIFF structure. This
is because this structure uses delaying integrators.
However the downside of using CIFF modular
architecture is higher power consumption and that it
cannot directly place the optimized zeroes exactly on
the unit circle for maximum SQNR.
C. Required and Simulated Specifications
Parameter Required Results
Signal Bandwidth 20 KHz 20 KHz
Clock Frequency < 8MHz 5.2MHz
Accuracy 17 19
Peak SQNR - 136.6 dB
OSR - 128
Order - 3rd
Form - CIFF
- 3
Quantizer
Resolution
- 2
Table1: Specifications for A/D Modulator
D. Theoretical Design
Using the Delta sigma toolbox the ideal structure was
modelled in MATLAB. By careful consideration of
the specifications, number of quantization levels and
. An ideal theoretical model of the A/D
converter was obtained. The maximum out of band
gain of the NTF, , decides the modular stability.
I choose to use = 3. In order to optimize the
NTF zeroes, I kept opt = 1.
The STF and the NTF obtained from for the CIFF
architecture is shown in the equations below:
= 1
=
( − 1)( − 2 + 1)
( − 0.356)( − 0.662 + 0.304)

E. Block Diagram
F. Simulation Results
A number of observations can be drawn from
plotting the NTF, STF gain blocks, zero pole plot of
the NTF, power spectral density of the delta sigma
modulator, SQNR etc. It is important to that for ideal
conditions we don’t consider input thermal noise or
thermal conditions. The SNR calculated for this
theoretical model will be slightly greater than the
practical Simulink model in which we consider input
noise. Some of the simulations results that were
obtained for the theoretical model are shown in
figures 1 to 7.
Figure 1: NTF and STF Gain plots across frequency
Figure 2: Optimized Poles of NTF
By choosing opt = 1, in the theoretical model we can
optimize the zeroes of the NTF, to lie exactly on the
unit circle.

Figure 4: Input (u) and Output (v) plot across time
Figure 5: SQNR vs Input Level
The SQNR vs input level is shown in the figure
above. It can be seen that the peak SQNR is higher
than our rough estimation. This is because we
consider an ideal theoretical model which has no
noise in the input and no quantization noise.
Figure 6: Power Spectral Density of the Modulator
G. Dynamic Range Scaling
After realizing the theoretical model, the output of
each integrated is scaled such that maximum swing
can be obtained. This process of scaling the output
by scaling the coefficients is called dynamic range
scaling.
Coefficient Before
Scaling
Dynamically
Scaled
Rounded
1.9821 2.4191 2.42
1.5040 2.5978 2.6
0.4131 1.9004 1.9
1 0.8194 0.82
1 1 1
0.00036139 0.00096244 0.00096244
1 0.8194 0.82
1 0.7066 0.71
1 0.3755 0.38
Table 2: Coefficients of CIFF Structure, before and after scaling
In the figure below (figure 7), the output of each
integrator is plotted against the input. The black lines
are the output of each integrator after dynamic range
scaling and the dashed lines are the output waveform
before dynamic range scaling.

Figure 7: Before and after dynamic range scaling of the output of
each integrator of the Delta sigma Modulator
The power spectral density of the modulator is shown
in the figure 8 (below). It can be noted that the SNR
is lower than that of the theoretical model. This is
because, I used real integrators in order to observe
the effects of other non-idealities such as finite,
bandwidth, finite gain, slew rate of the amplifier etc.
Figure 8: Power Spectral Density of the Modulator with real
integrators
H. Effect of Non-Idealities
Once the scaled coefficients are obtained after
performing dynamic range scaling, we can model the
CIFF structure and observe the effects of non-
idealities on the theoretical model. Figures 9 to 13
demonstrate the effect of different non-idealities on
the output spectrum of the modulator.
H.1 Finite Gain
Figure 9: Effect of Non-Idealities; Finite Gain
The effect of finite bandwidth was observed by
varying the amplifier’s gain bandwidth product,
keeping the gain constant. The Power Spectral
Density (PSD) of the output, is shown for bandwidth
in the figure below.
H.2 Finite Bandwidth
Figure 10: Effect of Non-Idealities; Finite Bandwidth

H.3 Slew Rate of Amplifier
Figure 11: Effect of Non-Idealities; Slew Rate of the amplifier
The effect of increase in slew rate was observed. The
corresponding PSD of the output was shown in the
figure above (figure 11).
H.4 Analog Noise
Figure 12: Effect of Non-Idealities; Analog Noise
White noise was added to the input of the modulator
in order to observe the effect of white noise. The
variation in the power spectral density of the output
of the modulator is illustrated in the figure above
(figure 12).
H.5 Capacitor Mismatch
Figure 13: Effect of Non-Idealities; Capacitor Mismatch
I. Decimation Filter
To remove the noise in the digital output of the delta
sigma modulator, we use a decimator followed by an
IIR Filter. The decimator is a cascade integrator
comb decimator that downsamples every 4 samples
of the output. Next I used an elliptical filter of order
10 that collects the output of the decimator and filters
out the higher frequency noise. The block diagram of
this is shown below in figure 14.
Figure 14: Block Diagram of Decimation Filter
The magnitude response of the decimator is shown
below in figure 15.
Figure 15: Magnitude response of Decimation Filter which
downsamples the output of the modulator by 4

The IIR elliptical filter used to filter the output of the
decimeter had an order of 10 and a passband and
stopband ripple of 0.1 dB and -130 dB respectively.
The stopband frequency was kept to the bandwidth
of the modulator. This meant that we effectively
downsampled the output of the decimeter by 32.
Figure 16: Magnitude response of 10th
Order Elliptical Filter
which downsamples the output of the decimator by 32
It can be seen from the above figure (figure 16) that
the elliptical filter has four sections which removes
the signal noise level in the output of the modulator.
J. Slew Rate Calculation
For our design we were given that the output is
allowed to slew for 30% of the total settling time. On
a circuit level, I was using a or of 2.5 V.
Thus the minimum slew rate [2] needed by the
amplifiers can be calculated by the equation: -
=
30%
= 66.66
This gives us a rough estimate of the slew rate needed
by the amplifiers. The integrators will not settle fast
enough if the amplifiers’ slew rate is drastically
reduced.
K. Switched Capacitor Implementation
I attempted to simulate the delta sigma modulator in
circuit level by designing the CIFF structure in
Cadence. The simulations that were obtained after
running a transient analysis were not as expected.
The circuit was designed by replacing the integrator
blocks with amplifiers and using switched capacitor
circuit with scaled capacitance values. A DAC was
made for the feedback path. The scaled values for the
capacitances were obtained from the gain blocks.
Non overlapping clocks were given to the two clocks
such that one switched was closed when the other
switch was open. The clocks had a peak amplitude of
2.5 V and the reference common mode voltage,
was used as 1.25 V.
The unit capacitance required for the first stage
integrator was derived from the equation [2].
=
2 (10 )
(
1
+
1
)
≈ 56
The gain of each stage was produced by using a
feedback capacitance and a series capacitance. The
ratio between these two capacitances was the
required ratio. The block capacitance used for this
purpose was 1 pF. The total capacitance used in the
circuit was approximately 303 pF.
Conclusion
The design for a 17 bit analog to digital converter
was successfully implemented with a 3rd
order CIFF
structure and the effect of non-idealities was
observed by simulating the architecture in MATLAB
Simulink. The modulator coefficients were scaled
such the output of each integrator gave good output
swing. In addition, decimation filter was
implemented which completed the loop for the A/D
modulator.
References
[1] R. Schreier, G. Temes, “Second and Higher Order
Delta Sigma Data Modulators,” Mar 2008.
[2] Jon Guerber, “Design of an 18-bit, 20 KHz Audio
Delta-Sigma Analog to Digital Converter,” Oregon
State University OR, June 2009.
[3] Brian Young, “Design of a High Speed Delta-
Sigma A/D Converter,” Oregon State University OR,
June 2009.
[4] Tony Chan Carusone, David A. Johns, Kenneth
W. Martin., “Analog Integrated Circuit Design,”
2nd ed.,(2012).

Design of 17-Bit Audio Band Delta-Sigma Analog to Digital Converter

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