Design of a Two-Stage Single Ended CMOS Op-Amp

Abstract— Motivated by course requirements and personal
interest in CMOS design, the following papers describes the
process taken to design a classical two-stage op amp configuration
with PMOS input transistors and Miller compensation with a
nulling resistor. This design takes into consideration
specifications on the minimum channel length, supply voltage,
load capacitance, open loop gain, phase margin, and unity gain
frequency. An analytical approach to solving the design is the
initially prepared. Then minor modifications are made, via the
assistance of simulations tools, to ensure all specifications of the
two stage op-amp are met.
I. INTRODUCTION
HE design of a CMOS op-amp contains multiple stages.
Identifying the basic structure of the op-amp as well as the
compensation type is the first stage. Additionally,
identifying the dc currents and transistor sizes and verifying
the results via simulations (such as SPICE) follows. The
physical implementation of the design, fabrication,
specification verification via measurements, and final
medications are the additional stages which will not be
covered in the following two stage operational amplifier
design. Due to the specifications given for the design, the
classical two-stage op amp configuration (voltage to current
and current to voltage stages) with PMOS input transistors and
Miller compensation with a nulling resistor was chosen (shown
in Appendix A).
The analytical design approach taken for the two stage
operational amplifier begins by indentifying the parameters of
the current mirror. The differential input parameters, second
gain parameters, and active load parameters follow
respectively. The final analytical parameter incorporates the
resultant compensation. With the utilization of SPICE
simulation and the BSIM3 model, the analytical design
undergoes minor modifications to achieve the design
requirements.
II. PARAMETER EXTRACTION
While the supply voltage is given, the supply current,
operating temperature, and temperature range are ignored for
this design. The process specifications can be identified via
simulation of the BSIM3 model in SPICE. The process
specifications which are necessary for this design are Vtn, Vtp,
Kn’, Kp’, λn, and λp. In order to identify Vtn, Vtp, Kn’, and
Kp’, linearly sweep values of Vgs for an N-MOS and a P-
MOS transistor biased in the saturation region. Vtn and Vtp
are identified graphically by determining the value of Vgs
when the drain current through the N-MOS and P-MOS
transistor become zero. Kn’ and Kp’ are identified by the slope
of the √(Id) vs. Vgs curve (slope = √[K’ / 2 * (W/L)]). λn and
Submitted for review no later than December 6th
, 2007 by 13:00 PST
λp are obtained by varying the Vds and identifying the current
through an N-MOS and P-MOS transistor biased in the
saturation region. Once the currents are obtained, λn and λp
can be identified from equation one
(eq.1: 1 1
2 2
1
1
d ds
d ds
I V
I V
λ
λ
   + ×
=   
+ ×   
).
III. DESIGN OF THE OPERATIONAL AMPLIFIER
While there are multiple approaches in analytically
designing an operational amplifier, the subsequent method
utilized consists of selecting the preferred drain currents for
each gain stage, identifying the current mirror parameters to
achieve such values, and finally designing the gain stages to
achieve the op-amp’s specifications. The following describes
such process; In Appendix B is the detailed calculations listed
in respective order with the proceeding process.
A. Current Mirrors
The segments of the two stage op-amp which pertains to the
current mirror includes; Iref, M5, M7, and M8. The purpose of
the current mirrors is to supply a drain current to each of the
two gain stages. The reference current (Iref) as well as the
current for each of the two stages must be determined. In this
design, the reference current was arbitrarily chosen to be
20µA. While not in the requirements of the design, a larger
reference current has not been selected to minimize the effect
of reference current error. Based upon the requirements of the
op-amp, the gain-bandwidth (GB) as well as the open-loop
gain (Avo) can be utilized in order to identify the current
margin of the first stage. (If there were maximum power
dissipation, input common mode range, and/or slew rate
requirements, they would be taken into account in selecting the
current of the first stage.) The chosen current must be large
enough to adhere to the GB requirement (eq.2: 1m
C
G
GB
C
= )
while small enough to maintain the requirement for open loop
gain (eq.3:
( )
1 2
2
5 6,7
2 m m
vo
d d N P
G G
A
I I λ λ
× ×
=
× × +
). The current of
the first gain stage was chosen to be 300µA. From equation 3
and 4 (eq.4:
'
2 6,7
6
2m d N
W
G I K
L
 
= × × × 
 
), the current
for the second stage can be chosen as a balance between
increasing the trans-conductance without sacrificing the open-
loop gain. For simplicity of design, the current of the first and
second stage was chosen to be the same (300µA).
Transistor 8 is in a diode-connected configuration (drain is
directly connected to the gate); therefore the device will
Design of a Two-Stage Single Ended CMOS Op-Amp
(November 2007)
STEVEN G. ERNST
T

operate in either the saturation or cut-off region. Transistor 8
plays a direct role in determining the VdSAT for the other
biasing transistors. With this in mind, the (W/L) ratio for
transistor 8 was chosen to be 8. With equation 5, the (W/L)
ratio for M5 is calculated (eq. 5: 5
5 88
IW W
L I L
   
= ×   
   
).
Additionally with equation 6, the (W/L) ratio for M7 is
calculated (eq. 6: 7
7 88
IW W
L I L
   
= ×   
   
).
B. Differential Input Stage
As shown in equation 2, the trans-conductance of the first
gain stage can be calculated if the gain-bandwidth and the
compensation capacitor (CC) are known. To ensure the two
stage op-amp achieves the minimum gain-bandwidth
(determined by the unity gain frequency), a gain-bandwidth
buffer of 5 is included in equation 2. From Allen [1], when a
phase margin of 60o
is required, the compensation capacitor
must be chosen to be greater than 0.22 times the capacitance
seen as the output. With such condition, an arbitrarily chosen
value of 5pF for the compensation capacitor and a gain-
bandwidth buffer of 5, the gain of the first stage is identified
and utilized in equation 7 (eq. 7:
2
1
'
1,2 5
m
d P
GW
L I K
 
= 
× 
) to
calculate the (W/L) ratio of the differential input stage.
C. Second Gain Stage
The second pole of the two stage op-amp is determined
directly by the gain of the second stage and inversely by the
load capacitance (eq. 8: 2
2
m
L
G
P
C
= ). In order to obtain a
sufficient phase margin (PM), the second pole of the two stage
op-amp must be located past the unity gain frequency. From
Allen [1], the second pole should be extended by at least 1.73
times the gain-bandwidth. For a margin of safety, the value of
2.2 is recommended. With equation 2, equation 8, and the
buffer of 2.2, the trans-conductance of the second stage can be
calculated. Furthermore, the (W/L) ratio of the transistor in the
second gain stage (M6) can be calculated from equation 9 (eq.
9:
2
2
'
6 62
m
d N
GW
L I K
 
= 
× × 
).
D. Active Load Stage
To ensure a reduced input offset voltage, the systematic
offset condition must apply; the drain voltages of M3 and M4
must remain the same. This allows the current for the first gain
stage to equally split between M1 and M2. With the systematic
offset condition applied, the (W/L) ratio for M3 and M4 can
be calculated from equation 10 (eq.
10: 5
3,4 66
1
2
d
d
IW W
L I L
    
= × ×    
    
).
E. Compensation
Included in series with the Miller compensation (previously
estimated in the differential input stage) on the second gain
stage is a nulling resister. The purpose of the nulling resister is
to eliminate or move the right hand plane (RHP) zero to the
left plane. From Hershenson, Boyd, and Lee [2], the value of
the nulling resistor can be estimated by equation 11 (eq.
11:
2
1
M
R
G
= ).
F. Defining Widths and Lengths
Due to channel length modulation, the minimum channel
length should not be chosen for an op-amp design. From
Kartikeya Mayaram (November 2007) [3], the channel length
is best chosen if it is at least 3 to 4 times the minimum
allowable length. For the intended operation of the differential
input and active load stage, transistors M1, M2, M3, and M4
must have matching widths and matching lengths.
Additionally, the biasing transistors (M5, M7, and M8) must
have matching lengths. For the above reasons and due to
simplicity, all lengths are set equal (1um). All transistor widths
are calculated from equation 12 (eq. 12: i i
i
W
W L
L
 
= × 
 
)
where Li is the same for every transistor.
IV. SIMULATION
Once the design parameters were identified, the two stage
op-amp is ready for the last stage of modification. For this
design, PSPICE was chosen as the preferred simulation device.
The analytical result of the op-amp with the BSIM3 model will
not always meet all the specifications. For this reason, minor
modifications of the device parameters. With these
modifications, the design parameters are fully identified, and
the performance of the op-amp can be simulated. The net-list
for such simulation can be found in Appendix C.
A. Offset Voltage
The input common mode range is determined by grounding
the non-inverting input, connecting the inverting input to the
output, and measuring the dc operating point on the inverting
input/output node. This dc operating point is the offset voltage.
B. Open-Loop Gain
The open loop gain is achieved by plotting the magnitude of
the output vs. the input (in dB) of the op-amp while sweeping
the input with an AC source and visually identifying the
magnitude at low frequencies.
C. Unity-Gain Frequency
The unity-gain frequency is achieved similar to that of the
open-loop gain. Simply plot the magnitude of the output vs.
the input of the op-amp (in dB) while sweeping the input with
an AC source and visually identify the frequency at which the
gain is 0dB (1V/V).

D. Phase Margin
The phase margin is achieved by plotting the phase of the
output vs. input (in degrees) of the op-amp and identifying the
magnitude of the value of the phase that corresponds with the
unity-gain frequency. The phase margin is then calculated by
subtracting the corresponding value from 180 degrees.
E. Input Common Mode Range
The input common mode range is determined by applying
the offset voltage from the non-inverting input to the inverting
input, applying a voltage source from the non-inverting input
to ground, and sweeping dc values of the voltage source by the
range of the supply voltages. From a plot of the output
voltages, both edges of the linear region identify VICMAX and
VICMIN.
F. Input Referred Noise Voltage
Within the simulation software, PSPICE, there is a prebuilt
function specifically designed to evaluate the input referred
noise voltage (.NOISE output input). As the frequency
of the input to the op-amp is swept, this function will identify
the input referred noise voltage. Therefore, one can probe the
desired frequency to distinguish the noise voltage referred to
the input.
G. Power Supply Rejection Ratio
As there are positive and negative power supplied to the op-
amp, the power supply rejection ratio (PSRR) can be viewed
from two viewpoints. The positive PSRR can be determined by
equation 13 (eq. 13:
( 0)
( 0)
V dd dd
dd in out
A V V
PSRR
A V V
+ =
= =
=
). The
negative PSRR can be determined by equation 14 (eq.
14:
( 0)
( 0)
V dd ss
ss in out
A V V
PSRR
A V V
− =
= =
=
). In order to simulate the
PSRR, ground the non-inverting input and tie the inverting
input to the output.
V. RESULTS
Table I includes a comprehensive list of the design
specifications and the performance of the two stage op-amp. It
can be seen that the performance of the two stage op-amp
exceeds each of the specifications.
TABLE I
SPECIFICATIONS AND PERFORMANCE
Constraints / Variables Specifications Performance
Open-loop gain > 70 dB 74.46dB
Unity-gain frequency > 10 MHz 79.28MHz
Phase margin 60o
64.3o
ICMR 0.75V
VICMAX 0V
VICMIN -0.75V
IR Noise Voltage @ 1 kHz 1.8mV
IR Noise Voltage @ 4 MHz 11µV
PSRR (Vdd) @ 1kHz 78.5dB
PSRR (Vdd) @ 10MHz 44.9dB
PSRR (Vss) @ 1kHz 77.9dB
PSRR (Vss) @ 10MHz 15.4dB
Table II includes the design parameters of the two stage op-
amp.
TABLE II
DESIGN PARAMETERS
Constraints / Variables Specifications Design Parameters
W1 = W2 260µm
W3 = W4 45µm
W5 120µm
W6 90µm
W7 120µm
W8 8µm
L1-8 ≥ 0.18µm 1µm
Iref 20µA
CL 4pF 4pF
CC 5pF
R 800
VI. CONCLUSION
When the open-loop gain, phase margin, unity gain
frequency, power supply, and load capacitance are the only
constraints in designing a two stage operational amplifier, the
design parameters listed in table II can be determined via the
approach taken in this paper. Identifying the current mirror
through educated analytical methods, then categorizing the
remaining parameters to adhere to the specifications is one
approach which, in this case, yields desired results.
ACKNOWLEDGMENTS
In addition to the listed references, information used
throughout the paper was taken from general knowledge
obtained by the author thorough out his educational career,
industrial career, and hobbyist projects.
REFERENCES
[1] P.E. Allen. “Chapter 6 – CMOS Operational Amplifiers.” CMOS
Analog Circuit Design. 2005.
http://aicdesign.org/scnotes/2004notes/Chap06_2UP_5_2_04_.pdf
[2] Maria del Mar Hershenson, Stephen P. Boyd, and Thomas H. Lee.
“Optimal Design of a CMOS Op-Amp via Geometric Programming.”
IEEE. January 2001.
http://www.stanford.edu/~boyd/papers/pdf/opamp_tcad.pdf
[3] Kartikeya Mayaram. Professor. School of Electrical Engineering and
Computer Science. Oregon State University.
[4] Kartikeya Mayaram. “Lecture notes for ECE 522.” Fall 2007. Oregon
State University
Steven G. Ernst Born in Salem, Oregon in
1984. He became a member of IEEE in 2007.
Currently pursuing a master’s of science degree
in Electrical Engineering at Oregon State
University in Corvallis, Oregon. The
anticipated date of graduation is June 2009. He
received his bachelor’s of science degree in
Electrical Engineering at Oregon State
University in Corvallis, Oregon in March of
2007. His interests include Power Electronics
and Power Systems. His research focuses on
Energy Systems.
He has worked for Intel Corporation as a
JUNIOR DESIGN ENGINEER in 2006 –
2007. He has worked for Siltronic Corporation as a FACILITIES ENGINEER
in 2005. He currently is working for the Army Corps of Engineers as a
STUDENT ENGINEER in Portland, Oregon since 2007.

APPENDIX
A. Two Stage CMOS Operational Amplifier Configuration
B. Calculations
( ) ( )
2 2
'
2
2 2 8.4575 3
143.059
1
1
N
slope E A
K
W V
L
× × − µ
= = =
   
   
   
( ) ( )
2 2
'
2
2 2 4 3
32
1
1
P
slope E A
K
W V
L
× × − µ
= = =
   
   
   
1 1
2 2
1
1
d P ds
d P ds
I V
I V
λ
λ
   + ×
=   
+ ×   
1 52.93 4
0.010791
2.9 4 1 4
P
P
P
E
E
λ
λ
λ
 + ×− 
→ = ∴ =  
− + ×   
1 1
2 2
1
1
d N ds
d N ds
I V
I V
λ
λ
   + ×
=   
+ ×   
1 44.3 4
0.010922
4.39 4 1 6
N
N
N
E
E
λ
λ
λ
 + ×− 
→ = ∴ =  
− + ×   
Set Iref = 20µA
Set I5 = 300µA
Set I6 = 300µA
Set (W/L)8 = 8
5
5 88
300 8
120
20 1
IW W
L I L
µ
µ
     
= × = × =     
     
7
7 88
300 8
120
20 1
IW W
L I L
µ
µ
     
= × = × =     
     
Set buffer = 5
Set CC = 5pF
1 2
5 2 10 5 15.7m C
mA
G C GB buffer p M
V
= × × = × ×Π× × =
( )
22
1
'
1,2 5
15.7
256.76
300 32
m
d P
mGW
L I K µ µ
 
= = = 
× × 
1
2
2.2
2.2 m
m L L
C
G
G C GB C
C
×
= × × = ×
2
2.2 15.7
4 2.765
5
m mA
p
p V
×
= × =
( )
22
2
'
6 6
2.765
89.0659
2 2 300 143.059
m
d N
mGW
L I K µ µ
 
= = = 
× × × × 
5
3,4 66
1
2
d
d
IW W
L I L
    
= × ×    
    
( )
1 300
89.0659 44.5329
2 300
µ
µ
 
= × × = 
 
2
1 1
361.669
2.765M
R
G m
= = = Ω
( )1,2 256.76 1 256.76W m mµ µ= × =
( )3,4 44.5329 1 44.5329W m mµ µ= × =
( )5,7 60 1 60W m mµ µ= × =
( )6 89.0659 1 89.0659W m mµ µ= × =
( )8 8 1 8W m mµ µ= × =
C. PSPICE Code
*Two Stage Op-Amp Design
M1 5 0 4 4 CMOSP W = 260u L = 1u AD = 154.2p AS = 154.2p
PD = 515.2u PS = 515.2u
PD = 515.2u PS = 515.2u
M3 5 5 3 3 CMOSN W = 45u L = 1u AD = 27p AS = 27p
PD = 91.2u PS = 91.2u
M4 6 5 3 3 CMOSN W = 45u L = 1u AD = 27p AS = 27p
PD = 91.2u PS = 91.2u
M5 4 2 1 1 CMOSP W = 120u L = 1u AD = 72p AS = 72p
PD = 241.2u PS = 241.2u
M6 7 6 3 3 CMOSN W = 90u L = 1u AD = 53.4p AS = 53.4p
PD = 179.2u PS = 179.2u
M7 7 2 1 1 CMOSP W = 120u L = 1u AD = 72p AS = 72p
PD = 241.2u PS = 241.2u
PD = 17.2u PS = 17.2u
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v
Vi 8 0 DC 0 AC 1V
* BSIM3 model inserted here i.e. .MODEL CMOSN NMOS LEVEL=7
* BSIM3 model inserted here i.e. .MODEL CMOSP PMOS LEVEL=7
.PROBE
.AC DEC 10 1 200MEG
.OP
.END
****************************DC*OPERATING*POINTS********************************
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE
( 1) .9000 ( 2) .1713 ( 3) -.9000 ( 4) .5619
( 5) -.3006 ( 6) -.3006 ( 7) .0620 ( 8) 0.0000
( 10) -.3006

D. KN’ and VTN Parameters Extraction
E. KP’ and VTP Parameters Extraction
F. Magnitude and Phase of the Two Stage Op-Amp
Vgs 2 0 1
Vds 1 0 0.1V
M1 1 2 0 0 CMOSN W=1u L=1u
*BSIM3 MODEL
.DC Vgs 0 1.5 0.01
.PROBE
.OP
.END
*RESULTS:
*VTN = 0.4V
*KPN = 143.059uA/V^2
Vg 2 0 1
VdS 1 0 -0.1V
M1 0 2 1 1 CMOSP W=1u L=1u
*BSIM3 MODEL
.DC Vg -1 1 0.1
.PROBE
.OP
.END
*RESULTS:
*VTP = -0.29V
*KPN = 32uA/V^2

G. Open-Loop Gain
H. Unity-Gain Frequency & Phase Margin
I. ICMR
M1 5 9 4 4 CMOSP W = 260u L =1u AD = 154.2pAS = 154.2pPD = 515.2uPS = 515.2u
M3 5 5 3 3 CMOSN W = 45u L =1u AD = 27p AS = 27p PD = 91.2u PS = 91.2u
M5 4 2 1 1 CMOSP W = 120u L =1u AD = 72p AS = 72p PD = 241.2uPS = 241.2u
M6 7 6 3 3 CMOSN W = 90u L =1u AD = 53.4p AS = 53.4p PD = 179.2uPS = 179.2u
M8 2 2 1 1 CMOSP W = 8u L =1u AD = 4.8p AS = 4.8p PD = 17.2u PS = 17.2u
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v
Vic 8 0 DC 0
Vos 8 9 11.69E-06
*BSIM3 MODELS
.PROBE
.DC Vic -1.1 1.1 .01
.OP
.END
*RESULTS:
*Vicmax = 0V
*Vicmin = -0.75V
*ICMR = 0.75V

J. Input Referred Noise Voltage
K. Power Supply Rejection Ratio (Vdd)
L. Power Supply Rejection Ratio (Vss)
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v
Vi 8 0 DC 11.69E-06 AC 1
*BSIM3 MODELS
.PROBE
.AC DEC 10 0.1 200MEG
.OP
.NOISE V(7) Vi
.END
*RESULTS: 1.8mV, 11uV
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v AC 1V
Vss 3 0 -0.9v
*Vi 8 0 DC 0
*BSIM3 MODELS
.PROBE
.AC DEC 10 1 200MEG
.OP
.END
*RESULTS: 78.5dB, 44.9dB
R1 6 10 800
Cc 10 7 5pF
CL 7 0 4pF
Iref 2 3 20uA
Vdd 1 0 0.9v
Vss 3 0 -0.9v AC 1V
*BSIM3 MODELS
.PROBE
.AC DEC 10 0.5 200MEG
.OP
.END
*RESULTS: 77.9dB, 15.4dB

Design of a Two-Stage Single Ended CMOS Op-Amp

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