Design of area optimized aes encryption core using pipelining technology

International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN
0976 – 6464(Print), ISSN 0976 – 6472(Online) Volume 4, Issue 2, March – April (2013), © IAEME
308
DESIGN OF AREA OPTIMIZED AES ENCRYPTION CORE USING
PIPELINING TECHNOLOGY
Anubhav Gupta1
, Harish Bansal2
1
Student M.Tech(VLSI), M.M Engineering College, Maharishi Markandeshwar University,
Mullana (Ambala)
2
Asstt. Prof. M.M Engineering College, Maharishi Markandeshwar University, Mullana
(Ambala)
ABSTRACT
A new pipelining technology based design scheme of the AES-128 (Advanced
Encryption Standard, with 128-bit key) encryption algorithm is proposed in this paper. For
maintaining the speed of encryption, the pipelining technology is applied and the mode of
data transmission is modified in this design so that the chip size can be reduced. The 128-bit
plaintext and the 128- bit initial key, as well as the 128-bit output of cipher text, are all
divided into four 32-bit consecutive units respectively controlled by the clock. The synthesis
verification based on HJTC0.18um CMOS process shows that this new program can
significantly decrease quantity of chip pins and effectively optimize the area of chip.
Keywords: Area optimization; Pipelining; VHDL.
1. INTRODUCTION
The number of individuals and organizations using wide computer networks for
personal and professional activities has recently increased a lot. A cryptographic algorithm is
an essential part in network security. With the rapid development and wide application of
computer and communication networks, the information security has aroused high attention.
Information security is not only applied to the political, military and diplomatic fields, but
also applied to the common fields of people’s daily lives. With the continuous development
of cryptographic techniques, the long-serving DES algorithm with 56-bit key length has been
broken because of the defect of short keys. The "Rijndael encryption algorithm" invented by
Belgian cryptographers Joan Daemen and Vincent Rijmen's had been chosen as the standard
INTERNATIONAL JOURNAL OF ELECTRONICS AND
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 4, Issue 2, March – April, 2013, pp. 308-314
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309
AES (Advanced Encryption Standard) algorithm whose packet length is 128 bits and the key
length is 128 bits, 192 bits, or 256 bits. Since 2006, the Rijndael algorithm of advanced
encryption standard has become one of the most popular algorithms in symmetric key
encryption. AES can resist various currently known attacks.
Hardware security solution based on highly optimized programmable FPGA provides
the parallel processing capabilities and can achieve the required encryption performance
benchmarks. The current area-optimized algorithms of AES are mainly based on the
realization of S-box mode and the minimizing of the internal registers which could save the
area of IP core significantly.
In this paper, we present an design of the AES block cipher with pipelining
technology. We have exploited the temporal parallelism available in the AES algorithm. Our
chip contains the same ten units, and each unit can execute one round of the algorithm. Using
external pipelined design, ten rounds of the algorithm are executed in parallel in a chip.
Furthermore, using internal pipelining and key exchange pipelining, pipelining technology
was utilized in the intermediate nine round transformations so that the new algorithm
achieved a balance between encryption speed and chip area, which met the requirements of
practical application.
The results show that this new algorithm with pipelining technology and special mode
of data transmission can significantly decrease the quantity of chip pins and reduce the chip
area.
2. AES OVERVIEW
AES is a symmetric cipher that processes data in 128-bit blocks. It supports key sizes
of 128, 192, and 256 bits and consists of 10, 12, or 14 iteration rounds, respectively. Each
round mixes the data with a roundkey, which is generated from the encryption key.
Decryption inverts the iterations resulting in a partially different data path.
The steps involved are given below:
1. Key Expansion using Rijndael's key schedule
2. Initial Round
o AddRoundKey
3. Round
o Sub Bytes—a non-linear substitution step where each byte is replaced with another
according to a lookup table.
o Shift Rows—a transposition step where each row of the state is shifted cyclically a certain
number of steps.
o Mix Columns—a mixing operation which operates on the columns of the state,
combining the four bytes in each column
o AddRoundKey—each byte of the state is combined with the round key; each round key is
derived from the cipher key using a key schedule.

310
Figure 1. AES round operations
4. Final Round (no Mix Columns)
o Sub Bytes
o Shift Rows
o AddRoundKey
This is the iterative looping architecture of the AES. VHDL code is written for the AES
encryption algorithm for finding cipher for any given plaintext input.
3. RELATED WORK
After the ratification of AES, a large number of its hardware implementations have
appeared. Whereas the earlier designs mainly focused on intensively pipelined, high-speed
implementations, the more recent work has concentrated on compact and low-power
architectures considering low-cost devices and feedback modes of operation.
Basically pipelining means to process the data that is given as input in a continuous
manner without having to wait for the current process to get over. This pipelining concept is
seen in many processors. In the architecture in the registers are used to store the current
output of the round that is being executed. Now instead of passing the output of each round to
the next round directly we use a register which would act as a bypass or an internal register.
Since the current rounds value is stored in the register the next input to the current round can
be given as soon as the current output is obtained. And the input to the next round is given
from the register thus avoiding a direct contact between the two rounds. This is not possible
in the iterative looping architecture because the next input can be given only when the whole

311
round based processing is over since the same hardware is used over and again in the process
of obtaining the cipher text. Thus, the pipelined architecture increases the speed of execution
for obtaining the cipher text but at a cost of increased hardware. In the substitute bytes we use
a look up table based S-box. This contributes for some of the hardware in the form of block
RAMs. With the help of a search based look up table (LUT) we can reduce the hardware cost
to a considerable extent.
From the above analysis, we can find that the process of AES encryption can be
mainly divided into two parts: key schedule and round transformation. The improved
structure is also divided into these two major processes.
The initial key will be sent to the two modules: Keyexpansion and Keyselection,
while the plaintext is to be sent to the round transformation after the roundkey is selected. But
the operand of data transmission is turned into a 32-bit unit.
Figure 2. The new improved structure of AES algorithm
The functions of various parts of the structure shown above are described as follow:
1. The initial round of encryption:
The four packets of consecutive 32-bit plaintext (128 bits) have been put into the
corresponding registers. Meanwhile, another four packets of consecutive 32-bit initial key
(128 bits) have been put into other registers by the control of the enable clock signal.
Furthermore, this module should combine the plaintext and initial key by using the XOR
operators.
2. Round Transformation in the intermediate steps:
A round transformation mainly realizes the function of SubBytes and MixColumns with 32-
bit columns. Four packets of round transformation are processed independently. Then the
results of MixColumns and the 32-bit keys sourced from Keyexpansion are combined by
using XOR operators. Here, the round transformation is a module with 64 input ports (32- bit
plaintext+32-bit key) and 32 output ports.
The function of SubByte is realized by Look-Up Table (LUT). It means that the operation is
completed by the Find and Replace after all replacement units are stored in a memoy
(256×8bit = 1024 bit).

312
The implementation of MixColumn is mainly based on the mathematical analysis in the
Galois field GF(28). Only the multiplication module and the 32-bit XOR module of each
processing unit (one column) are needed to design, because the elements of the multiplication
and addition in Galois field are commutative and associative. Then the function of
MixColumn can be achieved.
4. FUNCTIONAL SIMULATION AND SYNTHESIS
In this paper, the new structure of AES-128 encryption algorithm introduced above is
implemented with VHDL hardware description language, while minimizing the input /output
ports to save redundant area of the chip. The V file named aes_control in the project of the
design contains the input and output ports, interface converters and controllers. Other
function modules are described in independent V files respectively. We used ModelSim SE
PLUS 6.0 for the waveform simulation platform and verified the results.
The Simulation in the Modelsim SE PLUS 6.0 Platform
Firstly, all project files of the design were compiled in Modelsim SE PLUS 6.0
simulation platform. If the files were all compiled successfully, the simulated waveforms
could be obtained when loading the test file test_bench_top. Figure shows the simulation
waveform of the new algorithm
Figure 3. The 32-bit plaintext, 32-bit initial key and 32-bit cyphertext
The initial 128-bit input tmp0 sequences are extracted to four 32-bit words as the
plaintext (128bit) meanwhile, the 128-bit input sequences tmp1 are extracted to four 32-bit
words as initial key (128bit); the sequences of tmp2(128bit) are the correct ciphertext data,
which is used for validating the correctness of the new encryption scheme. We found that the
input in0 of four continuous state words and 128 bits plaintext tmp0 express the same by the
control signal of en; four consecutive state-words of input in1 are consistent with 128 bits
key. After a complete process of AES encryption, the output stream data_out_32 exports four
continuous 32-bit sequences, which are consistent with the 128bits ciphertext tmp2. In
conclusion, the logic function of improved algorithm is correct and it satisfies the
requirement of AES encryption algorithm.

313
Above table shows that the logic elements of the new improved structure increase and
the total registers is more than twice of the original quantity. The reason lies on the
segmentation of data in the Round Transformation. The pipelining process of four 32-bit
packets data needs more registers than before. A certain clock delay will be produced in the
encryption process, because of the processing mode of packets. So the pipelining technology
is used in the round transformation, ensuring that the encryption speed meets the actual
demand.
The pipelining technology and 32-bit packet segmentation greatly reduces the area of the
chip.
Dynamic power consumption accounts for the majority of the circuit power consumption, and
the dynamic power is relatively reduced compared with the unimproved algorithms, and the
encrypted rate decreases. However, this clock delay is acceptable and still meets the
application requirement.
5. CONCLUSION
A design using pipelining technology for area-optimized AES algorithm which meets
the actual application is proposed in this paper. After being coded with VHDL Hardware
Description Language, the waveform simulation of the new algorithm was taken in the
ModelSim SE PLUS 6.0. Ultimately, a synthesis simulation of the new algorithm has been
done. The result shows that the design with the pipelining technology and special data
transmission mode can optimize the chip area effectively. Meanwhile, this design reduces
power consumption to some extent, for the power consumption is directly related to the chip
area. Therefore the encryption device implemented in this method can meet some practical
applications.

314
REFERENCES
[1] J.Yang, J.Ding, N.Li and Y.X.Guo, “FPGA-based design and implementation of reduced
AES algorithm” IEEE Inter.Conf. Chal Envir Sci Com Engin(CESCE).,Vol.02, Issue.5-6,
pp.67-70, Jun 2010.
[2] A.M.Deshpande, M.S.Deshpande and D.N.Kayatanavar,“FPGA Implementation of AES
Encryption and Decryption”IEEE
Inter.Conf.Cont,Auto,Com,and Ener., vol.01, issue04, pp.1-6,Jun.2009.
[3] Hiremath.S. and Suma.M.S.,“Advanced Encryption Standard Implemented on FPGA”
IEEE Inter.Conf. Comp Elec Engin. (IECEE), vol.02,issue.28,pp.656-660,Dec.2009.
[4] Abdel-hafeez.S.,Sawalmeh.A. and Bataineh.S.,“High Performance AES Design using
Pipelining Structure over GF(28)” IEEE Inter Conf.Signal Proc and Com.,vol.24-27, pp.716-
719,Nov. 2007.
[5] Rizk.M.R.M. and Morsy, M., “Optimized Area and Optimized Speed Hardware
Implementations of AES on FPGA”, IEEE Inter Conf. Desig Tes Wor.,vol.1,issue.
16,pp.207-217, Dec. 2007.
[6] Liberatori.M.,Otero.F.,Bonadero.J.C. and Castineira.J. “AES-128 Cipher. High Speed,
Low Cost FPGA Implementation”, IEEE Conf. Southern Programmable Logic(SPL),
vol.04,issue.07,pp.195-198,Jun. 2007.
[7] Abdelhalim.M.B., Aslan.H.K. and Farouk.H. “A design for an FPGAbased
implementation of Rijndael cipher”,ITICT. Ena Techn N Kn Soc.(ETNKS), vol.5,
issue.6,pp.897-912,Dec.2005.
[8] D. Canright. A very compact S-box for AES. In Proc.7th Int. Workshop on Cryptographic
Hardware and Embedded
Systems (CHES 2005), pages 441–455, Edinburgh, UK, Aug. 29–Sept. 1, 2005.
[9] P. Chodowiec and K. Gaj. Very compact FPGA implementation of the AES algorithm. In
Proc. 5th Int. Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003),
pages 319–333, Cologne, Germany, Sept. 8–10, 2003.
[10] S. Farhan, S. Khan, and H. Jamal. Mapping of high-bit algorithm to low-bit for
optimized hardware implementation. In
Proc. 16th IEEE Int. Conf. on microelectronics (ICM 2004),pages 148–151, Tunis, Tunisia,
Dec. 6–8, 2004.
[11] M. Feldhofer, S. Dominikus, and J. Wolkerstorfer. Strong authentication for RFID
systems using the AES algorithm. In Proc. 6th Int. Workshop on Cryptographic Hardware
and Embedded Systems (CHES 2004), pages 357–370, Boston, MA, USA, Aug. 11–13,
2004.
[12] Sandeep Bidwai, Saylee S. Bidwai, Dr.S.P.Patil and Sunita S. Shinde, “Implementation
& Performance Analysis of Cordic in OFDM Based Wlan System Using VHDL”,
International Journal of Electronics and Communication Engineering & Technology
(IJECET), Volume 3, Issue 3, 2012, pp. 103 - 111, ISSN Print: 0976- 6464, ISSN Online:
0976 –6472.
[13] Nilesh P. Bodne and A.A. Kelkar, “VHDL Modeling for Wi-Fi Mac Layer Transmitter
and Receiver”, International Journal of Electronics and Communication Engineering &
Technology (IJECET), Volume 3, Issue 1, 2012, pp. 171 - 177, ISSN Print: 0976- 6464,
ISSN Online: 0976 –6472.

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