Design Space Vector Modulated PWM Three-Phase Inverter

ELEC 490/492/498/499 Final Report:
Design and Implementation of a Space Vector Modulated
(SVM) PWM Three-Phase Inverter
Submitted By:
Group #34
Luc Lamarche
Nicholas Mochnacki
Faculty Supervisor:
Dr. Alireza Bakhshai

Executive Summary
Space vector (SV) pulse width modulation (PWM) has become an increasingly
implemented technique for 3-phase voltage source inverters (VSI) in applications for
induction and synchronous motors. SV PWM in contrast to sinusoidal pulse width
modulation (SPWM), offers greater DC- Bus utilization, and less commutation losses.[1]
This document provides a discussion of SV PWM, computer simulation of SP PWM, and
an implementation of SV PWM technique.
The SV PWM waveform pattern was implemented using software determined switching
patterns, based on the Timer Compare function using a PIC17F877A microcontroller,
which outputted its gating signals to a 3-phase inverter, and received its Timer Compare
function values via a Motorola 68HC11E microcontroller.
SV PWM waveforms are produced from the computer simulation and the implemented
SV PWM technique are presented and discussed in this report.
2

Table of Contents
1.0 Introduction..............................................................................................4
1.1 Purpose...................................................................................................4
1.2 Background and Objective.....................................................................4
1.3 Overview of the Project Work...............................................................4
2.0 Background and Motivation.................................................................... 5
2.1 Space Vector Theory .............................................................................5
2.1.1 Implementation....................................................................... 7
2.2 Specifications.........................................................................................7
3.0 Design and Production Approach............................................................7
3.1 Scheduling and Division of Labour.......................................................7
3.2 Simulation..............................................................................................8
3.3 Production and Design of a Physical SV PWM.....................................9
3.3.1 Inverter Module........................................................................... 10
........................................................................................................................
3.3.2 Inverter Control Module.............................................................. 11
........................................................................................................................
3.3.3 Calculation Module......................................................................13
3.3.4 User Interface Control Module....................................................15
3.3.5 Handshaking Between the Inverter Control and Calculation Module...........16
4.0 Testing, Evaluation And Results........................................................... 18
5.0 Conclusion............................................................................................. 20
6.0 References .....................................................................................................20
Appendix A............................................................................................................22
Appendix B............................................................................................................25
Appendix C............................................................................................................27
Appendix D............................................................................................................37
3

1.0 INTRODUCTION
1.1 Purpose
This report summarizes the work and results produced by Group #34 of their design and
implementation of a SV PWM Three-Phase Inverter. The intended audience of the
documentation is Dr. Alireza Bakhshai (Faculty Supervisor), Constantin Siriteanu
(Course Instructor), and future Elec 490/492/498 project groups.
1.2 Background and Objectives
Technological advancements in high voltage transistors, has led to an increase in
industrial use of PWM techniques for 3-phase VSI. 3-phase PWM inverters are primarily
used in synchronous and induction motor drives.[2] Which allows for control of the
voltage and frequency delivered to the motor drive, offering an increase in performance
and efficiency delivered to the load. PWM techniques are implemented by providing
gating sequences to an inverter.
The goal of this project is to design and implement a SV PWM Three-Phase Inverter.
The process to achieve this goal required an in depth understanding of the SV PWM
before designing any device used for the project. Then, integrating our knowledge of SV
PWM with a computer simulation, this was done to confirm our knowledge of SV PWM
and prove that our design was capable of achieving the required output gating signals.
After success of the computer model, an overall design was produced and implemented.
1.3 Overview of the Project Work
Overview of the project work consisted of an in depth understanding of SV PWM theory
and implementation, a computer simulation, and a designed and implemented working
SV PWM device. The SV PWM theory is discussed in section 2.1 of this document.
Computer simulation is discussed in section 3.2 of this document. The design and
4

implementation of the SV PWM device implemented was broken into 4 modules. This
design and implementation is discussed in greater detail in section 3.3 of this document.
2.0 BACKGROUND AND MOTIVATION
The project was to build a 3 phase SV PWM. This required and understanding of SV
PWM theory, and a computer simulation to validate our understanding of SV PWM
theory, and ensure that our design and implementation of SV PWM was capable of
achieving the desired goal.
2.1 Space Vector Theory
Space vector theory is a method of controlling the three switches of the inverter to
efficiently convert a constant DC source to variable amplitude, variable frequency AC
power source. Since there are 3 switches for the 3-phase inverter, there are 8 (23
) possible
combinations. These states are mapped to a space vector diagram shown in figure 1. The
two states in which all switches are on and off correspond to the center of the space
vector diagram, it is referred to as the zero vector because its magnitude is equal to zero.
This leaves 6 vectors, which are marked with their switching pattern. Each of the vectors
is separated by 60 degrees and creates six divisions, which are called sectors, which are
numbered I-VI in figure 1. [3]
111
011
101
001
110
010
100
000
CBA
111
011
101
001
110
010
100
000
CBA
Vmax
?
Vref
100
110010
011
001 101
I
II
III
IV
V
VI
Figure 1: Space vector representation diagram
5

A reference vector (Vref) can be created through the principals of vector addition, by
switching from one vector to another for t1 and t2 seconds.[4] For example in our
diagram Vref would be created by switching to the (001) vector for t1 seconds and then to
the (011) vector for t2 seconds. Equation (1) calculates t1 and t2 for any given vector
angle.[4]
(1)
Where T is the cycle period and is given by equation (2) [4]
(2)
and K is the normalized amplitude constant that controls the amplitude of the vector and
can be calculated from equation (3).
K=Vref/VDC. (3)
Each of the six sectors were divided into three separate reference vectors (#vectors=3x6).
Switching through each reference vector in a counterclockwise rotation controls the
desired three-phase inverter output. The two parameters that control the output of the
inverter are f, which is a parameter to equation (2) and corresponds to the output
frequency and Vref, which is a parameter to equation (3), corresponds to the output
voltage. Therefore time t1 and t2 can be calculated through these parameters which are
controlled by the user.
To simplify the equation for use in a 16 bit microprocessor we create a constant Q.
(4)
where R=f/5 since we will only allow frequency increments of 5 Hz. The multiplier 5x106
is to convert the time in second to # cycles for a 5MHz processor.
6

New equation Subbing (4) into eqn. (1) gives us:
(5)
T= t1 + t2 + t0 where t0 is the time in which the inverter is switched to (000) or (111).
Therefore t0 can be solved by ,
t0=T - t2 - t1 (6)
2.1.1 Implementation:
The values produced from this equation are stored on a Motorola 68HC11
microprocessor. When the user specifies the frequency and voltage, the Motorola sends
the relative values from the table to the Inverter Control Module.
2.2 Specifications
The SV PWM is designed for an output frequency of 30 – 400 Hz, and output voltage of
of 30 – 208 Volts line-to-line RMS, from a DC source at 290 Volts.
3.0 DESIGN AND PRODUCTION APPROACH
The design and production approach of the project was broken down into 2 sections.
First section consisted of a computer simulation, and the second was actual physical
design and production of the SV PWM.
3.1 Scheduling and Division of Labour
The group met twice a week to discuss progress and timelines. Even with a few small
problems that were encountered, the project was successfully completed to our
supervisor’s satisfaction in time. Figure 2 shows the division of labour that was followed.
7

This is modified from the proposal since Hui Cheng did not participate in any of the work
therefore the division was recalibrated to compensate. The workload was effectively
divided equally between Nick Mochnacki and Luc Lamarche.
Space Vector Pulse
Width Modulator
Project
Division of Labour
Space Vector Theory
Luc Lamarche 50%
Nicholas Mochnacki %50
Hui Cheng 0%
Computer Simulation
Luc Lamarche 10%
Nicholas Mochnacki 90%
Hui Cheng 0%
Production and Design of
a Space Vector PWM
User Control Module Calculation Control
Module
Inverter Control
Module Inverter
Programming 2 Pic16F877A
Luc Lamarche 95%
Nicholas Mochnacki 5% (debugging)
Hui Cheng 0%
Assembly and SpeedWire
Implementation
Luc Lamarche 50%
Hui Cheng 0%
Programming Motorola
Luc Lamarche 5%(debugging)
Hui Cheng 0%
Parallel Port Communication
Testing and Debugging
Luc Lamarche 50%
Hui Cheng 0%
Soldering
Luc Lamarche 90%
Hui Cheng 0%
SpeedWire Implementation
Luc Lamarche 50%
Hui Cheng 0%
First Draft Program (Fixed
Frequency and Voltage and
no Handshaking)
Luc Lamarche 0%
Hui Cheng 0%
Final Program (Designed for
Variable Voltage and
Frequencey and with
Handhaking)
Luc Lamarche 100%
Hui Cheng 0%
LED 7-Segment Display Theory
Luc Lamarche 50%
Hui Cheng 0%
Parallel Port
Communication Testing
and Debugging
Luc Lamarche 50%
Hui Cheng 0%
Parallel Port Communication
Testing and Debugging
Luc Lamarche 50%
Hui Cheng 0%
Soldering and
SpeedWire Assembly
Luc Lamarche 50%
Hui Cheng 0%
Figure 2: Division of Labour
3.2 Simulation
Using Simulink in Matlab, a simulation was done to ensure that our understanding of SV
PWM theory was correct to produce a functional SV PWM. The Simulink model
allowed for a variable voltage and variable frequency from a 290 volts DC voltage
source. Figure 3 depicts the Power Spectral Density (PSD) of the output achieved for the
computer simulation at 60 Hz and 100 Volts L-L RMS. The Significance of this model,
not only ensured that we were able to produce three sinusoidal outputs out of phase by
8

120 degrees but also that harmonics of multiples of three cancel out when voltages are
connected line-to-line. Figure 3, shows that harmonics from a single-phase output
(depicted on the left) are canceled out for line-to-line voltage, (depicted on the right).
Further Documentation of the Simulation can be found in the Appendix A.
Figure 3: The PSD of Va phase on and Va-b line-line
3.3 Production and Design of a Physical SV PWM
The overall system consisted of 4 Layers (see figure 4), designed with low coupling and
high cohesion. The first layer is the User Interface Control module. It is an interface that
allows a user to change the frequency and voltage of the desired 3-phase output. The
second layer accepts the new frequency and voltage and processes the new control
signals that will realize this new output. It then passes calculated information to the third
layer, which is called the Inverter Control module. This layer is responsible for realizing
the new information and creates the proper control signals. These signals are fed to the
fourth layer, which is the inverter. The inverter uses theses signals to convert a DC source
to a 3-phase power source according to the user specifications.
The approach taken in the project to realize the block diagram in figure 4 is shown in
figure 5. This section describes in detail the individual modules in reverse sequence
starting from the Inverter module and ending at the User Interface Control module.
9

Figure 4: Project Block Diagram
Figure 5: Project Layout
3.3.1 Inverter Module
The Inverter is a device that accepts a DC source as its input and converts it to an variable
voltage, variable frequency 3-phase source. Figure 6 shows a simplified inverter
representation.[2] The outputs are taken at Va, Vb and Vc, where each of these outputs are
out of phase by 120 degrees, creating the 3-phase output. The frequency and voltage is
determined by the six switches shown in figure 6 as A, B, C, A’, B’ and C’. The job for
the Inverter Control module is to control these switches in a specific pattern with specific
timing determined by the space vector theory described in section 2.1. Even though 6
switches are controlled, only three are considered since three of the switches are the
1

compliments of the other three. For example when A is closed A’ must be opened. This
leads to the 8 different combinations (23
) that are used in space vector theory.[1]
Figure 6: Simplified inverter representation
The inverter that was used is the IRAM. This chip included a gate drive that isolated the
inverter circuit with the Inverter Control module.
3.3.2 Inverter Control Module
The Inverter Control Module, shown in Figure 5, controls the 3 switches of the inverter
circuit (Figure 6). The module uses the PIC16F877A microprocessor with a 20Mhz
clock. The main function for this module is to output the specific vector sequences (or
switching patterns) to the inverter for the time delay that was calculated using the space
vector theory in section 2.1. These calculated delays are passed to the module by the
Calculation module with a full handshake process whenever a new frequency and
amplitude is entered. The module’s process is shown in the flow chart in Figure 7. As the
figure shows, the processor is in a continuous loop. After going through the appropriate
initialization steps it starts the loop by checking the current sector. If the sector value
reads a 6 then we have done a full rotation of the vector space and it is reset back to 0.
Otherwise it continues by obtaining the delay value t0 found in the memory and
outputting the zero vectors for t0 clock cycles. It then follows by outputting vector 1 and
vector 2 for t1 and t2 clock cycles respectively. Through vector addition, this process
creates a single vector.[1] It then loops back and creates a second and third vector with
1

angles and lengths specified by the delay times. These three vectors are shown in figure 8
with angles 10, 30 and 50 degrees. After the third vector is produced, the vector value
will increment to 4 and is detected by the processor, which then resets the vector value
back to 0 and increments the sector value. This process is repeated until we complete all
six sectors of the space vector diagram (Figure 1) and then restarts itself back in the first
sector completing a full rotation.
Figure 7: Flow Chart
1

Figure 8 for Inverter Control Module
The code in assembly language that implements the inverter control module with the
PIC16F877A microprocessor can be found in appendix B.
In addition to the main program that creates the vector rotation, there is also an interrupt
subroutine that updates the delay values in the memory by accepting values from the
Calculation module using a full handshake technique. This technique is described in
section 3.2.5.
3.3.3 Calculation module
The Calculation module, shown in Figure 5, determines the width of each pulse outputted
by the Inverter Control module. The Calculation module is loaded with tables for each
selected frequency and voltage implemented by the User Interface Control module. Each
table consists of 42 bytes of data, corresponding to the chosen frequency and voltage.
The data contained in the table consists of 21 pulse width times, each being 2 bytes in
length. The overall function of the Calculation module is to receive the frequency and
voltage from the User Interface module when the enter switch is engaged. The module
then determines the 21 pulse width times for the chosen frequency and voltage, and
transmits the 42 bytes of data to the inverter control module via parallel port
handshaking.
1

The Calculation module is implemented using a Motorola 68HC11E microcontroller.
Table 1 below indicates the configuration of the Pin and their corresponding purpose for
the Motorola 68HC11E.
Table 1 Configuration of Motorola 68HC11E I/O Pins
Pin I/O Purpose
STRA Input Enter switch pushed by user
PortB Output Data bus transmitted to the Inverter Control Module
PortC Input Data bus contains Frequency from the User Interface Control Module
D0 Input Receives Ack from the Inverter Control Module for Handshaking
D2-D5 Output Sends Int/Ready/Ack/Done bits to Inver Control Module for Handshaking
PortE Input Data bus contains Voltage from the User Interface Control Module
The Calculation module used a Motorola 68HC11E, its Flow Chart is displayed in
Figure 9. The Motorola performs a continous loop while checking the status of STRA,
and repeats this loop until the STRA is low. After the STRA is set low, the inputted
voltage and frequency are received and stored from the User Interface Control module,
from PortE and PortC, respectively. The Motorola then determines the address of the 42
Byte table stored in its ROM that corresponds to the given frequency and voltage. Then
it performs a full handshake with the Inverter Control module (which is explained
Section 3.2.5). After the completion of the handshake, the program then returns to its
loop, checking the status of STRA.
1

Figure 9 Flow Chart of the Motorola HC11E performing its role as the Calculation Module
3.3.4 User Interface Control Module
Figure 10: User Interface Control Module schematic
1

The User Interface Control module shown in Figure 5 as two control dial symbols, allows
a user to change the 3-phase AC supply output to a desired frequency and voltage. A
detailed schematic representation of the control is shown in figure 10. The design and
implementation for the two controls are essentially identical therefore only one control
needs to be described. As shown in figure 10, the controls are in digital form. Three 7-
segment LEDs display the voltage/frequency and two push buttons below are used to
increment or decrement the current displayed value. Once a desired voltage and
frequency is selected the user must push the enter button shown in figure 5 in order to
activate the changes. The processor used for the module was the same as the one used for
the Inverter Control module, which is the PIC16F877A. This allowed a faster
implementation since only one type of assembly language had to be learned to code both
modules.
In addition to displaying the voltage/frequency through the LED display, the processor
also outputs the displayed value in binary form to port C, which is connected to the
Calculation module. When the enter button is pushed, an interrupt is triggered in the
Calculation module and it can capture the 8 bits representation of the desired
voltage/frequency from User Interface module.
The code in assembly language that implements the User Interface Control module with
the PIC16F877A microprocessor can be found in appendix C.
3.3.5 Handshaking Between the Inverter Control and Calculation Module
After the Calculation module has determined the address in its ROM corresponding to the
frequency and voltage, it fires an interrupt to the Inverter Control module. The interrupt
halts the Inverter Control module outputting sequence to the Inverter module. Then the
Calculation Module loads the Data Bus and sends a ready bit to the Inverter Control
Module. This ready bit indicates to the Inverter Control module that the data bus is
loaded with new data, and receives the data. After the Inverter Control module has
received and stored this data, it sends an acknowledge bit to the inverter control module.
This acknowledge bit sent to the Calculation module indicates that the data has been
1

successfully received and in response to the acknowledge bit, the Calculation module sets
its ready bit low and sends its own acknowledge bit in response. This acknowledge bit
from the Calculation module then lets the Inverter Control module know that the
Calculation module has received its acknowledge. The Calculation module acknowledge
bit then times out. The Calculation module will either load the data bus with a new value
and repeat this handshaking process starting at the ready bit, or it will send a done bit.
The done bit sent by the Calculation Module tells the Inverter Control Module to exit the
interrupt and return to its outputting sequence to the Inverter module. The done bit times
out and returns to outputs low.
Figure 11 Parellel Port Handshaking Between the Calculation Module and Inverter Control Module
Figure 11, is a waveform of the handshaking between the 2 modules. The Calculation
module was used with Motorola 68HC11E working at 8 MHz. The Inverter Control
module was used with a PIC16F877A clocked at 20 MHz. Since the clocks are working
at different speeds, standalone Asynchronous Parallel Port communication was used. This
also explains why full handshaking was deemed essential, as pulse handshaking could
have proved unreliable for 2 different chips working at different clock speeds (8 & 20
MHz), and different Architectures (RISC and CISC).
1

4.0 TESTING, EVALUATION AND RESULTS
In order to test the design, the output that was measured was taken at the Inverter Control
module output. The reason for this is that the inverter that was purchased was damaged
and was not functioning properly. Taking the measurements of the switching sequence is
essentially the same as taking the measurements at the output since the inverter acts as an
amplifier. Therefore instead of having a DC input of 290V we can treat it as having a DC
input of 5V, which is the maximum swing for the output of the processor.
In order to test the system, two frequencies were used, one at 100Hz and the other at
200Hz with both voltages at 0.6*Vdc. Figure 12 shows the line-to-line output sequence of
the inverter control module.
In order to measure the fundamental frequencies for these pulses a capacitor was used to
filter out the harmonics of the line-to-line signal. In order to show the 120 degrees phase
different between two different outputs, two of the output signals were filtered and
measured as shown in figure 13. This shows the fundamental frequency sine waves of the
two phases. As shown in the figure, the frequency for the 100Hz was measured to be
98.96Hz and 98.81Hz for the two output phases, which gives an error of 1.04Hz and
1.19Hz respectively. The frequency measured for the 200Hz output was 197.2Hz and
194.6Hz. Therefore the 200Hz signals had errors of 2.8Hz and 5.4Hz respectively. The
amplitude difference going from 100Hz to 200Hz in figure 13 are not accurate since a
basic capacitor was used as the filter and therefore does not have a constant amplitude
response.
Figure 14 shows the Fast Fourier Transform for the pulse in figure 12. Unwanted
harmonics are shown to exist close to the fundamental frequencies of 100Hz and 200Hz.
Ideally the system should only have harmonics that are far from the fundamental and can
easily be filtered. With the closer harmonics it is difficult to filter them out.
Although the voltages could not be measured accurately, the fact of getting accurate
frequencies means that the calculation module is producing the proper vector rotation
1

calculations and it is highly likely that the magnitude component or voltage is correct as
well.
Figure 12: measured line-to-line output pulse sequences
a) For frequency=100Hz and voltage=0.6Vdc b) For frequency=200Hz and voltage=0.6Vdc.
Figure 13: Two phase output with filter
a) For frequency=100Hz and voltage=0.6Vdc b) For frequency=200Hz and voltage=0.6Vdc.
Figure 14: Fast Fourier Transform of pulse sequence
1
a) For frequency=100Hz and voltage=0.6Vdc. b) For frequency=200Hz and voltage=0.6Vdc.

5. CONCLUSION
The space Vector Pulse Width Modulated Three Phase Inverter was successfully design
and constructed. The final product includes a User Interface control module that allows a
user to easily specify a voltage and frequency through the digital display. This
information is then fed to the Calculation module, where it processes the information and
determines the appropriate control signals and passes this data to the Inverter Control
module where it is realizes and controls the inverter to obtain the desired output. After
testing the system, we have determined that the frequencies are relatively accurate.
Although actual measurements could not be taken for the voltages, the accuracy should
be approximately the same as the frequency since the calculation module was shown to
produce the proper control signals.
In the future this project could be tested with a 3-phase motor. In addition a feedback
network could be added to measure the output frequency and voltage and feed it back to
the calculation module to correct any errors.
6.0 REFERENCES
[1] Victor R. Stefanovic, and Slobodan N. Vukosavic, “Space vector PWM Voltage
Control with Optimized Switching Strategy,” IEEE IAS-1992 Ann. Meeting, pp. 1025 -
1033.
[2]Zhenyu Yu, "Space-Vector PWM With TMS320c24x/F24x Using Hardware and
Software Determined Switched Patterns", Texas Instruments, Literature Number
SPRA524, March 1999
[3]. N. Mohan, W. Sulkowski, P. Jose, T. Brekken. Including Voltage Space Vector
PWM in Undergraduate Courses. Department of Electrical Engineering at the
University of Minnesota. MN [online]. Available:
http://www.ece.umn.edu/groups/PowerElectronics_Drives/svpwm.pdf
[4] Backshai A, Fast Space Vector Modulation Based on A Neurocomputing Digital
Signal Processor. Department of Electrical & Computer Engineering at Concordia
University. IEEE, 1997
2

LIST OF APPENDICES
Appendix A: Simulink Model
Appendix B: code for inverter control module
Appendix C: code for User Interface Control module
Appendix D: code for Calculation Module
2

Appendix A: Simulink Model
This Appendix provides a diagram of the Simulink model design for the Space vector
pwm. The graphs presented are the gating sequence of the three phases, the Line-Line
voltage of Vca, and the Fundamtal harmonic line-line voltage of Vab, Vbc, and Vca.
Figure 1: Simulink Diagram of Space Vecto PWM
22

Figure 2: Gating sequence for the three phases for 93 V rms per phase
Figure 3: Vca line-line voltage
23

Figure 4: V out of the fundamental frequency for line to line voltages Vab, Vbc, and Vca
24

APPENDIX C
;**********************************************************************
;Inverter Control Module
;**********************************************************************
list p=16f877A ; list directive to define processor
#include <p16f877A.inc> ; processor specific variable definitions
__CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _RC_OSC & _WRT_OFF &
_LVP_ON & _CPD_OFF
;***** VARIABLE DEFINITIONS
w_temp EQU 0x75 ; variable used for context saving
status_temp EQU 0x76 ; variable used for context saving
pclath_temp EQU 0x77 ; variable used for context saving
tableAdd EQU 0x78
VECTOR EQU 0x79
i EQU 0x7A
counterHi EQU 0x7B
counterLo EQU 0x7C
temp EQU 0x7D
table EQU 0x7E
portb000 equ 0x38
portb000a equ 0xb8
portb001 equ 0xb1
portb010 equ 0xaa
portb011 equ 0xa3
portb100 equ 0x9c
portb101 equ 0x95
portb110 equ 0x8e
portb111 equ 0x87
;**********************************************************************
ORG 0x000 ; processor reset vector
nop ; nop required for icd
goto main ; go to beginning of program
;///////////int///////////
ORG 0x004 ; interrupt vector location
movwf w_temp ; save off current W register contents
movf STATUS,w ; move status register into W register
movwf status_temp ; save off contents of STATUS register
movf PCLATH,w ; move pclath register into w register
movwf pclath_temp ; save off contents of PCLATH register
movlw 0x20
movwf tableAdd
CALL reset
bcf INTCON,1
movf pclath_temp,w ; retrieve copy of PCLATH register
movwf PCLATH ; restore pre-isr PCLATH register contents
movf status_temp,w ; retrieve copy of STATUS register
movwf STATUS ; restore pre-isr STATUS register contents
swapf w_temp,f
swapf w_temp,w ; restore pre-isr W register contents
retfie ; return from interrupt
;////////////end of interupt//////////////
Table1
addwf PCL, 1
retlw portb000
retlw portb001
retlw portb011
retlw portb111
retlw portb011
retlw portb001
25

retlw portb000
retlw portb000
retlw portb010
retlw portb011
retlw portb111
retlw portb011
retlw portb010
retlw portb000
retlw portb000
retlw portb010
retlw portb110
retlw portb111
retlw portb110
retlw portb010
retlw portb000
retlw portb000
retlw portb100
retlw portb110
retlw portb111
retlw portb110
retlw portb100
retlw portb000
retlw portb000
retlw portb100
retlw portb101
retlw portb111
retlw portb101
retlw portb100
retlw portb000
retlw portb000
retlw portb001
retlw portb101
retlw portb111
retlw portb101
retlw portb001
retlw portb000
retlw 0xFF
main
;initialize
bcf STATUS, RP0 ;Bank0
clrf i
clrf VECTOR
movlw b'10010000'
movwf INTCON ;enable interupt
movlw 0x20
movwf table ;set lookup table start address(0x20)
bsf STATUS, RP0 ;bank 1
bsf PIE1,2 ;enable the CCP1 interupt
movlw 0x3D ;
movwf TRISB ;Input (signals from other processor)
movlw 0x07 ;Disable the analog-to-digital converter
movwf ADCON1
movlw 0xFF
movwf TRISC ;set as allInput (data from motorola)
bcf TRISE,4 ;PORTD functions in
general purpose I/O
clrf TRISD ;set PortD as outputs
bcf OPTION_REG,5 ;Internal instruction cycle clock
(CLKO)
movlw b'00000001' ;Enable Timer1 and use existing clock
movwf T1CON
movlw b'00001010'
26

movwf CCP1CON ;Compare mode, generate software
interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
bcf PIR1,2 ;clear CCP1 Interrupt Flag
bit
clrf PORTB
;---------------sector0-----------------------------
sector0
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1H
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1L
movf i,0
call Table1
movwf PORTD
bcf PIR1,2
clrf TMR1H
clrf TMR1L
loopcount
btfss PIR1,2
goto loopcount
incf i,1
movf i,0
sublw d'7'
btfsc STATUS,Z
goto nextvect0
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
goto sector0
nextvect0
movlw 0x00
movwf i
incf VECTOR,1
movf VECTOR,0
sublw d'3'
btfsc STATUS,Z
goto nextsect0
nop
nop
nop
nop
goto sector0
nextsect0
clrf VECTOR
movlw d'7'
movwf i
27

movlw 0x20
movwf table
;//////////////////end of sector0///////////////
sector1
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1H
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1L
movf i,0
call Table1
movwf PORTD
bcf PIR1,2
clrf TMR1H
clrf TMR1L
loopcount1
btfss PIR1,2
goto loopcount1
incf i,1
movf i,0
sublw d'14'
btfsc STATUS,Z
goto nextvect1
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
goto sector1
nextvect1
movlw 0x07
movwf i
incf VECTOR,1
movf VECTOR,0
sublw d'3'
btfsc STATUS,Z
goto nextsect1
nop
nop
nop
nop
goto sector1
nextsect1
clrf VECTOR
movlw d'14'
movwf i
movlw 0x20
movwf table
;///////////////////sector 2////////////////////
sector2
movf table,0
incf table,1
movwf FSR
28

movf INDF,0
movwf CCPR1H
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1L
movf i,0
call Table1
movwf PORTD
bcf PIR1,2
clrf TMR1H
clrf TMR1L
loopcount2
btfss PIR1,2
goto loopcount2
incf i,1
movf i,0
sublw d'21'
btfsc STATUS,Z
goto nextvect2
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
goto sector2
nextvect2
movlw d'14'
movwf i
incf VECTOR,1
movf VECTOR,0
sublw d'3'
btfsc STATUS,Z
goto nextsect2
nop
nop
nop
nop
goto sector2
nextsect2
clrf VECTOR
movlw d'21'
movwf i
movlw 0x20
movwf table
;//////////////////end of sector2///////////////
;//sector 3//
sector3
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1H
movf table,0
incf table,1
29

movwf FSR
movf INDF,0
movwf CCPR1L
movf i,0
call Table1
movwf PORTD
bcf PIR1,2
clrf TMR1H
clrf TMR1L
loopcount3
btfss PIR1,2
goto loopcount3
incf i,1
movf i,0
sublw d'28'
btfsc STATUS,Z
goto nextvect3
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
goto sector3
nextvect3
movlw d'21'
movwf i
incf VECTOR,1
movf VECTOR,0
sublw d'3'
btfsc STATUS,Z
goto nextsect3
nop
nop
nop
nop
goto sector3
nextsect3
clrf VECTOR
movlw d'28'
movwf i
movlw 0x20
movwf table
;//////////////////end of sector3///////////////
sector4
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1H
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1L
movf i,0
call Table1
30

movwf PORTD
bcf PIR1,2
clrf TMR1H
clrf TMR1L
loopcount4
btfss PIR1,2
goto loopcount4
incf i,1
movf i,0
sublw d'35'
btfsc STATUS,Z
goto nextvect4
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
goto sector4
nextvect4
movlw d'28'
movwf i
incf VECTOR,1
movf VECTOR,0
sublw d'3'
btfsc STATUS,Z
goto nextsect4
nop
nop
nop
nop
goto sector4
nextsect4
clrf VECTOR
movlw d'35'
movwf i
movlw 0x20
movwf table
;//////////////////end of sector4///////////////
sector5
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1H
movf table,0
incf table,1
movwf FSR
movf INDF,0
movwf CCPR1L
movf i,0
call Table1
movwf PORTD
bcf PIR1,2
clrf TMR1H
clrf TMR1L
31

loopcount5
btfss PIR1,2
goto loopcount5
incf i,1
movf i,0
sublw d'42'
btfsc STATUS,Z
goto nextvect5
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
goto sector5
nextvect5
movlw d'35'
movwf i
incf VECTOR,1
movf VECTOR,0
sublw d'3'
btfsc STATUS,Z
goto nextsect5
nop
nop
nop
nop
goto sector5
nextsect5
clrf VECTOR
clrf i
movlw 0x20
movwf table
;//////////////////end of sector5///////////////
goto sector0
reset:
wait
BTFSC PORTB,5
GOTO done
BTFSC PORTB,2
GOTO getportc
GOTO wait
getportc
movf tableAdd,0
incf tableAdd,1
movwf FSR
movf PORTC,0
movwf INDF
bsf PORTB,1
waitack
btfss PORTB,4
goto waitack
bcf PORTB,1
goto wait
done
RETURN
END ; directive 'end of program'
32

APPENDIX C
;*********************************************************
;User Interface Control Module (Frequency display)
;*********************************************************
list p=16f877A ; list directive to define processor
#include <p16f877A.inc> ; processor specific variable definitions
__CONFIG _CP_OFF & _WDT_OFF & _BODEN_OFF & _PWRTE_ON & _RC_OSC & _WRT_OFF &
_LVP_OFF & _CPD_OFF
w_temp EQU 0x71 ; variable used for context saving
status_temp EQU 0x72 ; variable used for context saving
pclath_temp EQU 0x73 ; variable used for context saving
i0 EQU 0x74
i1 EQU 0x75
i2 EQU 0x76
temp EQU 0x77
freq EQU 0x78
temp1 EQU 0x79
temp2 EQU 0x7A
temp3 EQU 0x7B
check EQU 0x7C
LED0 EQU b'11011101'
LED1 EQU b'01010000'
LED2 EQU b'11101100'
LED3 EQU b'11111000'
LED4 EQU b'01110001'
LED5 EQU b'10111001'
LED6 EQU b'10111101'
LED7 EQU b'11010000'
LED8 EQU b'11111101'
LED9 EQU b'11111001'
;**********************************************************************
ORG 0x000 ; processor reset vector
nop ; nop required for icd
goto main ; go to beginning of program
ORG 0x004 ; interrupt vector location
movwf w_temp ; save off current W register contents
movf STATUS,w ; move status register into W register
movwf status_temp ; save off contents of STATUS register
movf PCLATH,w ; move pclath register into w register
movwf pclath_temp ; save off contents of PCLATH register
; isr code can go here or be located as a call subroutine elsewhere
movf pclath_temp,w ; retrieve copy of PCLATH register
movwf PCLATH ; restore pre-isr PCLATH register contents
movf status_temp,w ; retrieve copy of STATUS register
movwf STATUS ; restore pre-isr STATUS register contents
swapf w_temp,f
swapf w_temp,w ; restore pre-isr W register contents
retfie ; return from interrupt
main
clrf i0
clrf i1
clrf i2
clrf PORTB
33

clrf PORTC
clrf freq
bcf INTCON,4
bsf STATUS, RP0 ;bank 1
movlw 0x00 ;
movwf TRISD ;output
movlw 0x07 ;Disable the analog-to-digital converter
movwf ADCON1
movlw 0x00
movwf TRISC ; ;PORTC as all output
movlw b'00101000'
movwf TRISA ;output
movlw 0x00
movwf TRISB
loopled
movf check,0
sublw d'250'
btfss STATUS,Z
goto rotateled
btfss PORTA,3
CALL incFreq
btfss PORTA,5
CALL decFreq
clrf check
rotateled
incf check
movf i0,0
call Table1
movwf PORTB
movlw 0x04
movwf PORTA
CALL delay2
movlw 0x00
movwf PORTB
movf i1,0
call Table2
movwf PORTB
movlw 0x02
movwf PORTA
CALL delay2
movlw 0x00
movwf PORTB
movf i2,0
call Table2
movwf PORTB
movlw 0x01
movwf PORTA
CALL delay2
movlw 0x00
movwf PORTB
goto loopled
incFreq:
movf i0,0
sublw d'1'
btfss STATUS,Z
goto inc
movf i1,0
sublw d'9'
btfss STATUS,Z
goto inc
34

movf i2,0
sublw d'9'
btfsc STATUS,Z
goto doneinc
inc
incf freq,1
movf freq,0
movwf PORTC
movf i0,0
sublw d'1' ;check to see if its a 1(5)
btfsc STATUS,Z ;if it is not skip
goto checki1
incf i0,1
goto doneinc
checki1 ;at this point we know it i0 was a 5
clrf i0
incf i1,1
movf i1,0
sublw d'10' ;check if i1 is at 10
btfss STATUS,Z ; if it is then goto checki2
goto doneinc
checki2
clrf i1
incf i2
movf i2,0
sublw d'10' ;check if i2 is at 10
btfss STATUS,Z ; if it is then reset to 9
goto doneinc
decf i2 ;we are at max freq and therefore go
back to 9
decf freq ;we are at max freq and therefore go back to
max freq value
doneinc
CALL delay2 ;I could put more here for switch debuncing
RETURN
decFreq:
movf i0,0
btfss STATUS,Z
goto dec1
movf i1,0
btfss STATUS,Z
goto dec1
movf i2,0
btfsc STATUS,Z
goto donedec
dec1
decf freq,1
movf freq,0
movwf PORTC
movf i0,0
sublw d'1' ;check to see if its a 1(5)
btfss STATUS,Z ;if it is skip
goto checki12
decf i0,1
goto donedec
checki12 ;at this point we know it i0 was a 0
incf i0
decf i1
movf i1,0
sublw 0xFF
btfss STATUS,Z ; check if i1 was at 0, if it is then goto checki22
goto doneinc
checki22
35

movlw d'9'
movwf i1
decf i2
movf i2,0
sublw 0xFF
btfss STATUS,Z ; check if i2 was at 0, if it is then reset to 0
goto doneinc
clrf i2
incf freq ;to set back to minimum
donedec
CALL delay2 ;I could put more here for switch debuncing
RETURN
delay2:
clrf temp
delayloop1
incf temp
btfss STATUS,Z
goto delayloop1
RETURN
delay:
clrf temp2
clrf temp3
pauseloop1
clrf temp
pauseloop2
incf temp
btfss STATUS,Z
goto pauseloop2
incf temp2
btfss STATUS,Z
goto pauseloop1
clrf temp2
incf temp3
movf temp3,0
sublw d'10'
btfss STATUS,Z
goto pauseloop1
RETURN
Table1
addwf PCL, 1
retlw LED0
retlw LED5
Table2
addwf PCL, 1
retlw LED0
retlw LED1
retlw LED2
retlw LED3
retlw LED4
retlw LED5
retlw LED6
retlw LED7
retlw LED8
retlw LED9
END ; directive 'end of program'
36

APPENDIX D
Calculation Module
PORTA EQU $1000
PIOC EQU $1002
PORTC EQU $1003
PORTB EQU $1004
PORTCL EQU $1005
DDRC EQU $1007
PORTD EQU $1008
DDRD EQU $1009
PORTE EQU $100A ;ADDRESS OF PARALLEL PORT E
OUTPUTE EQU $0000
OUTPUTCL EQU $0001
ORG $D000
BUF_START RMB 255 (A 256 BYTE BUFFER TO RECEIVE VALUES)
BUF_END RMB 1 (LAST BYTE OF BUFFER)
ORG $CB00
LDS #$CFFF (INITIALIZE STACK POINTER)
JSR SETSOURCE (SET SOURCE OF DATA ON PC7-PC0)
JSR INITC (INITIALIZE PORT C)
JSR INITD
LDAA #$00
STAA PORTD
START
LDAA PIOC (ARM STAF-CLEARING MECHANISM)
LDAA PORTCL (CLEARS STAF AND PRODUCES A STRB)
STAA PORTD
LDAA PORTCL
STAA OUTPUTCL
LDAA PORTE
STAA OUTPUTE
JSR POLL
37

JSR UPDATE ; THIS SUB-ROUTINE DETERMINES THE TABLE TO BE USED.
THE X REGISTER STORE THE ADDRESS
JSR HANDSHAKE
LDAA #$00
STAA PORTD
LDY #$FFFF ;LOAD BIGGEST PO SSIBLE VALUE
INTO X REGISTER
DLOOP3 DEY ;DECREMENT X
BNE DLOOP3 ;THIS LOOP IS FOR EXPERIMENTAL
USE ONLY
BRA START ; RE INITSTAFF MECH
*=====EXIT TO BUFFALO
SWI
INITC CLR DDRC
LDAA #$15
STAA PIOC
RTS
INITD LDAA DDRD
ANDA #%11000000
ORAA #%00111100 ; USUALLY 00111100
STAA DDRD ; PIN 2 .3, 4 ,5 ARE OUTPUTS, PINS 0,1 ARE
INPUTS
RTS
POLL
LDAA #$00
STAA PORTB
LDAA PIOC (4) (READ PIOC TO ARM STAF CLEARING MECHANISM)
ANDA #$80 (2) (CHECK IF STAF=1)
BEQ POLL (3) (STAF=0, CHECK AGAIN)
RTS
38

;=============================== HAND SHAKE
HANDSHAKE
LDAB #42
LDAA 0,X
STAA PORTB
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
LDAA #%00001100 ;SEND READY AND INTERUPT
STAA PORTD
HANDLOOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
39

NOP
NOP
NOP
NOP
NOP
NOP
LDY #$00FF ;LOAD BIGGEST PO SSIBLE VALUE INTO X REGISTER
DLOOPA DEY ;DECREMENT X
BNE DLOOPA ;LOOP BACK IF RESULT WAS NOT ZERO
LDAA #%00010000 ;SEND ACK AND TEST DONE
STAA PORTD
DECB ;DECREMENT ACCUM B
BEQ HANDDONE ;IF IT IS ZERO, THEN BRANCH TO END
; BUFFER SET OUTPUTS TO ZERO BEFORE PROPER OUTPUT
NOP
NOP
INX
LDAA 0,X
STAA PORTB
NOP ;PADDING
NOP
NOP
LDAA #%00001000 ;SEND READY
STAA PORTD
BRA HANDLOOP
HANDDONE LDAA #%00100000 ; SEND AND TEST ACK DONE BIT
STAA PORTD
LDY #$FFFF ;LOAD BIGGEST PO
SSIBLE VALUE INTO X REGISTER
DLOOP5 DEY ;DECREMENT X
BNE DLOOP5 ;THIS LOOP IS FOR EXPERIMENTAL USE ONLY
LDY #$FFFF ;LOAD BIGGEST PO SSIBLE VALUE INTO X
REGISTER
40

DLOOPB DEY ;DECREMENT X
BNE DLOOPB ;THIS LOOP IS FOR EXPERIMENTAL USE ONLY
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
LDAA #$00
STAA PORTD
RTS
;;=======================================================
UPDATE LDAA PIOC
LDAA PORTCL
CMPA #$01
BNE NEXA
LDX #HZ5
RTS
NEXA LDAA PIOC
LDAA PORTCL
CMPA #$02
BNE NEXB
LDX #HZ10
RTS
NEXB LDAA PIOC
LDAA PORTCL
CMPA #$03
BNE NEXC
LDX #HZ15
RTS
NEXC LDAA PIOC
LDAA PORTCL
CMPA #$04
BNE NEXD
LDX #HZ20
RTS
NEXD LDAA PIOC
LDAA PORTCL
CMPA #$05
BNE NEXE
41

LDX #HZ25
RTS
NEXE LDAA PIOC
LDAA PORTCL
CMPA #$06
BNE NEXF
LDX #HZ30
RTS
NEXF LDAA PIOC
LDAA PORTCL
CMPA #$07
BNE NEXG
LDX #HZ35
RTS
NEXG LDAA PIOC
LDAA PORTCL
CMPA #$08
BNE NEXH
LDX #HZ40
RTS
NEXH LDAA PIOC
LDAA PORTCL
CMPA #$09
BNE NEXI
LDX #HZ45
RTS
NEXI LDAA PIOC
LDAA PORTCL
CMPA #$0A
BNE NEXJ
LDX #HZ50
RTS
NEXJ LDAA PIOC
LDAA PORTCL
CMPA #$0B
BNE NEXK
LDAA PORTE
CMPA #$01
BNE NEXT60A
LDX #HZ601
RTS
NEXT60A LDAA PORTE
CMPA #$02
BNE NEXT60B
LDX #HZ602
RTS
NEXT60B LDX #HZ603
42

RTS
NEXK LDAA PIOC
LDAA PORTCL
CMPA #$0D
BNE NEXL
LDX #HZ70
RTS
NEXL LDAA PIOC
LDAA PORTCL
CMPA #$10
BNE NEXM
LDX #HZ80
RTS
NEXM LDAA PIOC
LDAA PORTCL
CMPA #$12
BNE NEXN
LDX #HZ90
RTS
NEXN LDAA PIOC
LDAA PORTCL
CMPA #$14
BNE NEXO
LDX #HZ100
RTS
NEXO LDAA PIOC
LDAA PORTCL
CMPA #$16
BNE NEXP
LDX #HZ110
RTS
NEXP LDAA PIOC
LDAA PORTCL
CMPA #$18
BNE NEXQ
LDX #HZ120
RTS
NEXQ LDAA PIOC
LDAA PORTCL
CMPA #$1A
BNE NEXR
LDX #HZ130
RTS
NEXR LDAA PIOC
LDAA PORTCL
CMPA #$1C
BNE NEXS
LDX #HZ140
43

RTS
NEXS LDAA PIOC
LDAA PORTCL
CMPA #$1E
BNE NEXU
LDX #HZ150
RTS
NEXU
LDX #HZ200
RTS
ORG $8000
HZ5
FCB $12
FCB $BF
FCB $39
FCB $67
FCB $0C
FCB $DE
FCB $25
FCB $AE
FCB $0C
FCB $DE
FCB $39
FCB $67
FCB $12
FCB $BF
FCB $10
FCB $7B
FCB $25
FCB $67
FCB $25
FCB $67
FCB $21
FCB $25
FCB $25
FCB $67
FCB $25
FCB $67
FCB $10
FCB $7B
FCB $12
FCB $BF
FCB $0C
FCB $DE
44

FCB $39
FCB $67
FCB $25
FCB $AE
FCB $39
FCB $67
FCB $0C
FCB $DE
FCB $12
FCB $BF
HZ10 FCB $09
FCB $48
FCB $1C
FCB $9C
FCB $06
FCB $57
FCB $12
FCB $BF
FCB $06
FCB $57
FCB $1C
FCB $9C
FCB $09
FCB $48
FCB $08
FCB $26
FCB $12
FCB $9C
FCB $12
FCB $9C
FCB $10
FCB $7B
FCB $12
FCB $9C
FCB $12
FCB $9C
FCB $08
FCB $26
FCB $09
FCB $48
FCB $06
FCB $57
FCB $1C
45

FCB $9C
FCB $12
FCB $BF
FCB $1C
FCB $9C
FCB $06
FCB $57
FCB $09
FCB $48
HZ15 FCB $06
FCB $20
FCB $13
FCB $03
FCB $04
FCB $2A
FCB $0C
FCB $70
FCB $04
FCB $2A
FCB $13
FCB $03
FCB $06
FCB $20
FCB $05
FCB $5F
FCB $0C
FCB $58
FCB $0C
FCB $58
FCB $0A
FCB $ED
FCB $0C
FCB $58
FCB $0C
FCB $58
FCB $05
FCB $5F
FCB $06
FCB $20
FCB $04
FCB $2A
FCB $13
FCB $03
FCB $0C
FCB $70
FCB $13
FCB $03
FCB $04
46

Design Space Vector Modulated PWM Three-Phase Inverter

More Related Content

What's hot (20)

Viewers also liked (12)

Similar to Design Space Vector Modulated PWM Three-Phase Inverter (20)

Design Space Vector Modulated PWM Three-Phase Inverter