3. 3
Introduction
• The digital system consists of two types of circuits, namely
(i) Combinational circuits
(ii) Sequential circuits
• Combinational circuit consists of logic gates whose output
at any time is determined from the present combination
of inputs. The logic gate is the most basic building block of
combinational logic. The logical function performed by a
combinational circuit is fully defined by a set of Boolean
expressions.
• Sequential logic circuit comprises both logic gates and the
state of storage elements such as flip-flops. As a
consequence, the output of a sequential circuit depends
not only on present value of inputs but also on the past
state of inputs.
4. Combinational Circuits
• A combinational circuit consists of input variables,
logic gates, and output variables.
• The logic gates accept signals from inputs and output
signals are generated according to the logic circuits
employed in it.
• Binary information from the given data transforms to
desired output data in this process.
• Both input and output are obviously the binary signals,
i.e., both the input and output signals are of two
possible states, logic 1 and logic 0.
4
5. 5
Analysis Procedures
The analysis of a combinational
circuit starts with
• Given logic diagram
• Culminates with a set of Boolean functions
• Obtain Truth Table
• Possibly an explanation of the
circuit operation
6. 6
• To obtain the output Boolean functions from a
logic diagram, we proceed as follows:
1. Label all gate outputs that are a function of
input variables with arbitrary symbols — but
with meaningful names. Determine the Boolean
functions for each gate output.
2. Label the gates that are a function of input
variables and previously labeled gates with
other arbitrary symbols. Find the Boolean
functions for these gates.
3. Repeat the process outlined in step 2 until the
outputs of the circuit are obtained.
4. By repeated substitution of previously defined
functions, obtain the output Boolean functions
in terms of input variables.
8. 8
• The derivation of the truth table for a circuit is a
straightforward process once the output Boolean
functions are known
A B C F2 F’2 T1 T2 T3 F1
0 0 0 0 1 0 0 0 0
0 0 1 0 1 1 0 1 1
0 1 0 0 1 1 0 1 1
0 1 1 1 0 1 0 0 0
1 0 0 0 1 1 0 1 1
1 0 1 1 0 1 0 0 0
1 1 0 1 0 1 0 0 0
1 1 1 1 0 1 1 0 1
9. 9
Design Procedures
• The design of combinational circuits starts from the
specification of the design objective and culminates in
a logic circuit diagram or a set of Boolean functions
from which the logic diagram can be obtained.
• The procedure involves the following steps:
1. From the specifications of the circuit, determine the
required number of inputs and outputs and assign a
symbol to each.
2. Derive the truth table that defines the
required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for
each output as a function of the input variables.
4. Draw the logic diagram and verify the correctness of
the design (manually or by simulation).
10. Binary Adder, Subtractor
• The basic building blocks that form the basis
of all hardware used to perform the arithmetic
operations on binary numbers are half-adder,
full adder, half-subtractor, full-subtractor.
14
11. Half-Adder
• A half-adder is a combinational circuit that can be used to add
two binary bits. It has two inputs that represent the two bits to
be added and two outputs, with one producing the SUM output
and the other producing the CARRY.
Inputs
A B
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Block schematic of half-adder
Outputs
Carry (C) Sum
(S)
Logic Implementation of Half-adder
15
Truth table of Half-adder
K-map simplification for Carry and Sum
12. Full-Adder
• A full adder is a combinational circuit that
forms the arithmetic sum of three input bits. It
consists of 3 inputs and 2 outputs
Block schematic of Full-adder
12
15. • Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
• Carry, Cout = AB+ ACin + BCin .
Implementation of full-adder in Sum of Products
15
16. • The logic diagram of the full adder can also be implemented with
two half-adders and one OR gate. The S output from the second
half adder is the exclusive-OR of Cin and the output of the first half-
adder, giving
16
18. Half -Subtractor
• A half-subtractor is a combinational circuit that can be used to
subtract one binary digit from another to produce a DIFFERENCE
output and a BORROW output. The BORROW output here specifies
whether a 1 has been borrowed to perform the subtraction.
Input Output
A B Difference Borrow
Block schematic of Half-subtractor
Truth table of Half-subtractor Logic Implementation of Half-Subtractor
(D) (Bout)
K-map simplification for Half subtractor
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0 22
19. Full Subtractor
• A full subtractor performs subtraction operation
on two bits, a minuend and a subtrahend, and
also takes into consideration whether a 1 has
already been borrowed by the previous adjacent
lower minuend bit or not.
Block schematic of Full-adder
19
20. 20
The truth table for Full-subtractor
Inputs Outputs
A B Bin Difference(D) Borrow(Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
24. Binary Adder (Parallel Adder)
• A binary adder is a digital circuit that
produces
the
arithmetic sum of two binary numbers.
• It can be constructed with full adders connected in
cascade, with the output carry from each full adder
connected to the input carry of the next full adder in the
chain.
• Addition of n-bit numbers requires a chain of n full adders.
• The 4-bit binary adder using full adder circuits is capable of
adding two 4-bit numbers resulting in a 4-bit sum and a
carry output .
• The augend bits of A and the addend bits of B are
designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bit.
• The carries are connected in a chain through the full
adders. The input carry to the adder is C0, and it ripples
through the full adders to the output carry C4.
• The S outputs generate the required sum 28
25. • Since all the bits of augend and addend are
fed into the adder circuits simultaneously and
the additions in each position are taking place
at the same time, this circuit is known as
parallel adder.
4-bit binary parallel Adder
25
26. • To demonstrate with a specific example,
consider the two binary numbers A = 1011
and B = 0011. Their sum S = 1110 is formed
with the four-bit adder as follows:
26
27. 27
Carry Propagation–Look-Ahead Carry Generator
• In Parallel adder, all the bits of the augend and
the addend are available for computation at
the same time.
• The carry output of each full-adder stage is
connected to the carry input of the next high-
order stage.
• Since each bit of the sum output depends on
the value of the input carry, time delay occurs
in the addition process.
• This time delay is called as carry propagation
delay.
28. 28
• For example, addition of two numbers (0011+ 0101) gives
the result as 1000.
• Addition of the LSB position produces a carry into the
second position. This carry when added to the bits of the
second position, produces a carry into the third position.
This carry when added to bits of the third position,
produces a carry into the last position.
• The sum bit generated in the last position (MSB) depends
on the carry that was generated by the addition in the
previous position. i.e., the adder will not produce correct
result until LSB carry has propagated through the
intermediate full-adders.
• This represents a time delay that depends on the
propagation delay produced in an each full-adder.
• For example, if each full adder is considered to have a
propagation delay of 30nsec, then S3 will not react its
correct value until 90 nsec after LSB is generated.
• Therefore total time required to perform addition is 90+ 30
= 120nsec.
29. • The method of speeding up this process by eliminating
inter stage carry delay is called look ahead-carry
addition.
• This method utilizes logic gates to look at the lower
order bits of the augend and addend to see if a higher-
order carry is to be generated. It uses two functions:
carry generate and carry propagate.
Full adder with P and G shown 33
30. • Consider the circuit of the full-adder.
• We define two functions: carry generate (Gi) and
carry propagate (Pi) as,
• Gi (carry generate), it produces a carry 1 when both Ai and
Bi are 1, regardless of the input carry Ci.
• Pi (carry propagate) because it is the term associated with
the propagation of the carry from Ci to Ci+1.
• The Boolean functions for the carry outputs of each stage
and substitute for each Ci its value from the previous
equation:
34
31. • Since the Boolean function for each output carry is
expressed in sum of products, each function can be
implemented with one level of AND gates followed by
an OR gate.
• The three Boolean functions for C1, C2 and C3 are
implemented in the carry look-ahead generator.
• C3 does not have to wait for C2 and C1 to propagate;
in fact C3 is propagated at the same time as C1 and
C2. 35
34. Binary Subtractor (Parallel Subtractor)
• The subtraction A-B can be done by taking the 2’s
complement of B and adding it to A.
• The 2’s complement can be implemented with inverters
and a 1 can be added to the sum through the input carry.
• The circuit for subtracting A-B consists of an adder with
inverters placed between each data input B and the
corresponding input of the full adder. The input carry C0
must be equal to 1 when performing subtraction.
4-bit Parallel Subtractor 38
35. 35
Parallel Adder/ Subtractor
• The addition and subtraction operation can be
combined into one circuit with one common
binary adder. This is done by including an
exclusive-OR gate with each full adder.
• The mode input M controls the operation. When
M= 0, the circuit is an adder and when M=1, the
circuit becomes a Subtractor.
• Each exclusive-OR gate receives input M and one
of the inputs of B.
• When M=0, A + B
• When M=1, A + (B’ + 1) The circuit performs the
operation A plus the 2’s complement of B.
37. 37
Decimal Adder
• The digital system handles the decimal number in the form
of binary coded decimal numbers (BCD). A BCD adder is a
circuit that adds two BCD bits and produces a sum digit also
in BCD.
• Consider the arithmetic addition of two decimal digits in
BCD, together with an input carry from a previous stage.
• Since each input digit does not exceed 9, the output sum
cannot be greater than 9+ 9+1 = 19; the 1 is the sum being
an input carry.
• The adder will form the sum in binary and produce a result
that ranges from 0 through 19.
• These binary numbers are labeled by symbols K, Z8, Z4, Z2,
Z1, K is the carry.
• The columns under the binary sum list the binary values
that appear in the outputs of the 4- bit binary adder.
• The output sum of the two decimal digits must be
represented in BCD.
39. • When the binary sum is equal to or less than 1001, BCD number
is identical, and therefore no conversion is needed.
• When the binary sum is greater than 9 (1001), is non-valid BCD
• The addition of binary 6 (0110) converts it to the correct BCD
• The logic circuit to detect sum greater than 9 can be determined
by simplifying the boolean expression of the given truth table.
39
40. To implement
BCD adder we
require:
• 4-bit binary
adder for initial
addition
• Logic circuit to
detect sum
greater than 9
and
• One more 4-bit
adder to add
01102 in the
sum if the sum
is greater than
9 or carry is 1.
Block diagram of BCD adder 44
41. Magnitude Comparator
• It compares two given numbers (A and B) and
determines whether one is equal to, less than
or greater than the other.
• The output is in the form of three binary
variables representing the conditions A = B,
A>B and A<B, if A and B are the two numbers
being compared.
Block diagram of magnitude comparator 54
45. • For comparison of two n-bit numbers,
the classical method to achieve
the Boolean
expressions requires a
entries and becomes
truth table of
22n too
lengthy
and
cumbersome.
• The algorithm is a direct application of the
procedure a person uses to compare the
relative magnitudes of two numbers.
• Consider two numbers, A and B , with four
digits each.
• Write the coefficients of the numbers in
descending order of significance
A = 5 6 7 4
B = 8 2 3 1
A = 4 6 8 2
B = 4 6 8 9 58
46. • It is observed from the bit contents of two numbers that A
= B when A3 = B3, A2 = B2, A1 = B1 and A0 = B0.
• The value is either 1 or 0, the equality of each pair can be
expressed logically with an exclusive-NOR function as
• where, Xi =1 only if the pair of bits in position i are equal
( both are 1 or both are 0).
• To satisfy the equality condition of two numbers A and B,
it is necessary that all Xi must be equal to logic 1.
• This indicates the AND operation of all Xi variables.
• Boolean expression for two equal 4-bit numbers.
• The binary variable (A=B) is equal to 1 only if all pairs of
digits of the two numbers are equal. 59
47. • To determine whether A is greater or less than B,
• Inspect the relative magnitudes of pairs of significant
digits, starting from the MSB.
• If the two digits of a pair are equal, compare the next lower
significant pair of digits.
• The comparison continues until a pair of unequal digits
is reached.
• If the corresponding digit of A is 1 and that of B is 0, conclude
that A > B.
• If the corresponding digit of A is 0 and that of B is 1, then A < B.
• The sequential comparison can be expressed logically by the
two Boolean functions
(A>B) = A3B3′ +X3A2B2′ +X3X2A1B1′ +X3X2X1A0B0′
(A<B) = A3′B3 +X3A2′B2 +X3X2A1′B1 +X3X2X1A0′B0
• The symbols (A > B) and (A < B) are binary output variables that
are equal to 1 when A > B and A < B, respectively.
60
49. Decoders
• A decoder is a combinational circuit that converts
binary information from n input lines to a maximum of
2n unique output lines.
• The general structure of decoder circuit is –
• The 2n output values are from 0 through 2n-1.
• A decoder is provided with enable inputs to
activate decoded output based on data inputs. 49
51. 2-to-4 Line decoder
Here the 2 inputs are decoded into 4 outputs,
each output representing one of the minterms
of the two input variables.
51
52. 3-to-8 Line Decoder
• A 3-to-8 line decoder has three inputs (A, B, C) and
eight outputs (Y0- Y7). Based on the 3 inputs one of
the eight outputs is selected.
• The three inputs are decoded into eight outputs, each
output representing one of the minterms of the 3-
input variables.
• This decoder is used for binary-to-octal conversion.
52
54. • Decoders with enable inputs can be connected together to
form a larger decoder circuit.
• Two 3-to-8-line decoders with enable inputs connected to
form a 4-to-16-line decoder.
• When w = 0, the top decoder is enabled and the other is
disabled. The bottom decoder outputs are all 0’s, and the
top eight outputs generate minterms 0000 to 0111.
• When w = 1, the enable conditions are reversed: The
bottom decoder outputs generate minterms 1000 to 1111,
while the outputs of the top decoder are all 0’s.
4 * 16 decoder
constructed
with two
3 * 8 decoders
54
55. Combinational Logic Implementation
• A decoder provides
the
2n minterms of n
input
variables.
• Any combinational circuit with n inputs and m outputs
can be implemented with an n-to-2n-line decoder
and m OR gates.
• S(x, y, z) = ∑m(1, 2, 4, 7)
• C(x, y, z) = ∑m(3, 5, 6, 7)
Implementation of
a full adder with a
decoder
55
56. Encoders
• An encoder is a digital circuit that performs the inverse
operation of a decoder.
• An encoder is a combinational circuit that converts binary
information from 2n input lines to a maximum of n unique
output lines.
• The general structure of encoder circuit is
• It has 2n input lines, only
one which 1 is active at any
time and n output lines.
• It encodes one of the active
inputs to a coded binary
output with n bits.
• In an encoder, the number
of outputs is less than the
number of inputs. 56
57. Octal-to-Binary Encoder
• It has eight inputs (one for each of the octal digits) and
the three outputs that generate the corresponding
binary number.
• It is assumed that only one input has a value of 1 at any
given time.
57
58. Logic Diagram of Octal-to-Binary Encoder
• Output with all 0’s is generated when all the inputs are
0; this output is same as when D0 is equal to 1.
• The discrepancy can be resolved by providing one
more output to indicate that at least one input is equal
to 1.
58
59. Priority Encoder
• If two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence.
• In addition to the two outputs x and y, the circuit has a third output, V
(valid bit indicator).
• It is set to 1 when one or more inputs are equal to 1.
• If all inputs are 0, there is no valid input and V is equal to 0.
• The higher the subscript number, higher the priority of the input.
• D3, has the highest priority. So, regardless of the values of the other
inputs, when D3 is 1, the output for xy is 11.
• D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0.
• The output for D1 is generated only if higher priority inputs are 0, and
so on down the priority levels.
59
61. Multiplexers
• A multiplexer or MUX, is a combinational circuit with
more than one input line, one output line and more
than one selection line.
• A multiplexer selects binary information present from
one of many input lines, depending upon the logic
status of the selection inputs, and routes it to the
output line.
• Normally, there
are
2n
input lines and n selection
lines whose
bit combinations
determine which input is
selected.
• A multiplexer is also called
a data selector, since it
selects one of many inputs
and steers the binary
Block diagram of Multiplexer
information to the output
line. 95
62. 2-to-1- line Multiplexer
• The circuit has two data input lines, one output line and
one selection line, S.
• When S= 0, the upper AND gate is enabled and I0
has a path to the output.
• When S=1, the lower AND gate is enabled and I1 has a path
to the output.
• The multiplexer acts like an electronic switch that selects
one of the two sources.
Function table
62
63. 63
4-to-1-line Multiplexer
• A 4-to-1-line multiplexer has four (2n) input lines,
two (n) select lines and one output line.
• It is the multiplexer consisting of four input
channels and information of one of the channels
can be selected and transmitted to an output line
according to the select inputs combinations.
• Selection of one of the four input channel is
possible by two selection inputs.
• Each of the four inputs I0 through I3, is applied to
one input of AND gate.
• Selection lines S1 and S0 are decoded to select a
particular AND gate.
• The outputs of the AND gate are applied to
a single OR gate that provides the 1-line
output.
64. Function table
• The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1‘S0‘.
• The data output is equal to I1 only if S1= 0 and S0= 1; Y= I1S1‘S0.
• The data output is equal to I2 only if S1= 1 and S0= 0; Y= I2S1S0‘.
• The data output is equal to I3 only if S1= 1 and S0= 1; Y= I3S1S0.
• When these terms are ORed, the total expression for the data
output is,
Y= I0S1’S0’ + I1S1’S0 + I2S1S0’+ I3S1S0.
98
65. 65
Quadruple 2-to-1 Line Multiplexer
• This circuit has four multiplexers, each capable of selecting one of
two input lines.
• Output Y0 can be selected to come from either A0 or B0.
• Similarly, output Y1 may have the value of A1 or B1, and so on.
• Input selection line, S selects one of the lines in each of the four
multiplexers.
• The enable input E must be active for normal operation.
• Although the circuit contains four 2-to-1-Line multiplexers,
it is
viewed as a circuit that selects one of two 4-bit sets of data lines.
• The unit is enabled when E= 0. Then if S= 0, the four A inputs have
a path to the four outputs.
• On the other hand, if S=1, the four B inputs are applied to the
outputs.
• The outputs have all 0‘s when E= 1, regardless of the value of S.
67. 67
Application of Multiplexers
• Various ranges of applications in
data communication.
• Signal routing and data communication
are the important applications of a
multiplexer.
• It is used for connecting two or more sources
to guide to a
computer units
single destination
among and it
is useful for
constructing a common bus system.
• One of the general properties of a multiplexer
is that Boolean functions can be implemented
by this device.
68. 102
Implementation of Boolean Function using
MUX
• If a Boolean expression has (n+1) variables, then
n of these variables can be connected to the
select lines of the multiplexer.
• The remaining single variable along with
constants 1 and 0 is used as the input of the
multiplexer.
• For example, if C is the single variable, then the
inputs of the multiplexers are C, C‘, 1 and 0.
• In general, a Boolean expression of (n+1)
variables can be implemented using a multiplexer
with 2n inputs.
69. 69
• Implement the following Boolean function using 4: 1
multiplexer, F (A, B, C) = Σm (1, 3, 5, 6)
Solution:
Variables, n= 3 (A, B, C)
Select lines= n-1 = 2 (S1, S0)
2n-1 to MUX i.e., 22 to 1 = 4 to 1 MUX
Input lines= 2n-1 = 22 = 4 (D0, D1, D2, D3)
Implementation table
Apply variables A and B to the select
lines.
The procedures for implementing the
function are
i. List the input of the multiplexer
70. 70
• The first half of the minterms is associated with
C’ and the second half with C.
• The given function is implemented by circling the
minterms of the function and applying the
following rules to find the values for the inputs of
the multiplexer.
1. If both the minterms in the column are
not circled, apply 0 to the corresponding input.
2. If both the minterms in the column are
circled, apply 1 to the corresponding input.
3. If the bottom minterm is circled and the top
is not circled, apply C to the input.
4. If the top minterm is circled and the bottom
is not circled, apply C’ to the input.
71. D0 D1 D2 D3
C' 0 1 2 3
C 4 5 6 7
0 1 C C'
F (A, B, C) = Σm (1, 3, 5, 6)
Multiplexer Implementation
105
C’
0
1
A
B
Y
S1 S2
D2
D3
D1
D0 4 : 1
Mux
A and B to the select lines
C is the single variable
C
Implementation table
72. F (x, y, z) = Σm (1, 2, 6, 7)
Implementation table
72
Multiplexer Implementation
73. F ( A, B, C) = Σm (1, 2, 4, 5)
Implementation table
Multiplexer Implementation
73
75. Implement the Boolean function using 8: 1 and
also using 4:1 multiplexer
F (A, B, C, D) = Σm (0, 1, 2, 4, 6, 9, 12, 14)
Implementation table
Multiplexer Implementation Using 8: 1 MUX
75
78. 78
Implement the Boolean function using 8: 1
multiplexer.
F (A, B, C, D) = A’BD’ + ACD + B’CD + A’C’D
Implement the Boolean function using 8: 1
multiplexer.
F (A, B, C, D) = AB’D + A’C’D + B’CD’ + AC’D
Implement the Boolean function using 8: 1 and also
using 4:1 multiplexer
F (w, x, y, z) = Σm (1, 2, 3, 6, 7, 8, 11, 12, 14)
79. Implement the Boolean function using 8: 1
multiplexer
F (A, B, C, D) = Σm (0, 2, 6, 10, 11, 12, 13) + d (3, 8, 14)
Implementation table
Multiplexer Implementation
79
80. DEMULTIPLEXER
• Demultiplex means one into many.
• Demultiplexing is the process of taking information
from one input and transmitting the same over one of
several outputs.
• A demultiplexer is a combinational logic circuit that
receives information on a single input and transmits
the same information over one of several (2n) output
lines.
The demultiplexer is also
called a data distributer or a
serial-to-parallel converter .
80
81. 1-to-4 Demultiplexer
• A 1-to-4 demultiplexer has a single input, Din,
four outputs Y0 to Y3 and two select inputs S1 and
S0
Enable S1 S0 Din Y0 Y1 Y2 Y3
0 x x x 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0
1 0 1 0 0 0 0 0
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 0
1 1 1 0 0 0 0 0
1 1 1 1 0 0 0 1
Truth table of 1-to-4 demultiplexer
Logic Symbol
115
87. 87
Three-State Gates
• A multiplexer can be constructed with three-state gates
- digital circuits that exhibit three states.
• Two of the states are signals equivalent to logic 1 and
logic 0 as in a conventional gate.
• The third state is a high-impedance state in which
(1) the logic behaves like an open circuit, which means
that the output appears to be disconnected
(2) the circuit has no logic significance, and
(3) the circuit connected to the output of the three-state
gate is not affected by the inputs to the gate.
• Three-state gates may perform any conventional logic,
such as AND or NAND. However, the one most
commonly used is the buffer gate.
88. Graphic symbol for a
three-state buffer
2-to-1-line mux
88
4-to-1-line mux
![Borrow, Bout = A’B+ Bin (A’B+AB’)’ *(x‘y+xy‘)‘= (xy+x‘y‘)+
= A‘B+ Bin (AB+A‘B‘)
= A‘B+ ABBin+ A‘B‘Bin
= A‘B (Bin+1) + ABBin+ A‘B‘Bin
= A‘BBin+ A‘B+ ABBin+ A‘B‘Bin
= A‘B+ BBin (A+A‘) + A‘B‘Bin
= A‘B+ BBin+ A‘B‘Bin
= A‘B (Bin+1) + BBin+ A‘B‘Bin
= A‘BBin+ A‘B+ BBin+ A‘B‘Bin
= A‘B+ BBin+ A‘Bin (B +B‘)
= A‘B+ BBin+ A‘Bin
*Cin+1=
1+
*A+A‘=
1+
[Cin+1= 1]
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