![Load and store instructions
• Load-Store instructions are used to transfer
the Values between registers and memory.
– LDRB and STRB load and store bytes rather than
whole words, while LDRH and SDRH operate on
half-words and LDRSH extends the sign bit on
loading.
For example: LDR r0,[r1],STR r0,[r1]
• The following load and store instructions are
available:
– Load and Store Register
– Load and Store Multiple registers on page
– Load and Store Register Exclusive on page.
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EC8791 ARM Processor and Peripherals.pptx
- 1. EC8791- EMBEDDED AND REAL TIME SYSTEMS (R2017) UNIT-2 ARM PROCESSOR AND PERIPHERALS 1
- 2. SYLLABUS ARM Architecture Versions – ARM Architecture – Instruction Set – Stacks and Subroutines – Features of the LPC 214X Family – Peripherals – The Timer Unit – Pulse Width Modulation Unit – UART – Block Diagram of ARM9 and ARM Cortex M3 MCU. 2
- 3. ARM INTRODUCTION • ARM is actually a family of RISC architectures that have been developed over many years. • ARM does not manufacture its own VLSI devices; rather, it licenses its architecture to companies who either manufacture the CPU itself or integrate the ARM processor into a larger system. • The textual description of instructions, as opposed to their binary representation, is called an assembly language. • ARM instructions are written one per line, starting after the first column. 3
- 4. ARM ARCHITECTURE VERSIONS • The ARM architecture has evolved significantly and will continue to be developed in the future. • Six major versions of the instruction set have been defined to date, denoted by the version numbers from 1 to 6. – Of these, the first three versions including the original 26-bit architecture (the 32-bit architecture was introduced at ARMv3) are now OBSOLETE. – Other versions are Version 4, version 5 and version6.Versions can be qualified with variant letters to specify collections of additional instructions that are included as an architecture extension. 4
- 5. Version 4 and Introduction toThumb (T variant) • The Thumb instruction set is a re-encoded subset of the ARM instruction set. • Thumb instructions execute in their own processor state, with the architecture defining the mechanisms required to transition between ARM and Thumb states. • The key difference is that Thumb instructions are half the size of ARM instructions (16 bits compared with 32 bits). 5
- 6. Version 5T • Improved efficiency of ARM/Thumb interworking. • Count leading zeros (ARM only) and software breakpoint (ARM and Thumb) instructions added • Additional options for coprocessor designers (coprocessor support is ARM only) • Tighter definition of flag setting on multiplies (ARM and Thumb). 6
- 7. Version 6 • CPS, SRS and RFE instructions for improved exception handling • REV, REV16 and REVSH byte reversal instructions • SETEND for a revised endian (memory) model LDREX and STREX exclusive access instructions 7
- 8. Version 6 • SXTB, SXTH,UXTB, UXTH byte/half word extend instructions • A set of Single Instruction Multiple Data (SIMD) media instructions • Additional forms of multiply instructions with accumulation into a 64-bit result. 8
- 9. ARM Architecture (ARM7 TDMI): • T: Thumb, 16-bit instruction set • D: on-chip Debug support, enabling the processor to halt in response to a debug request • M: enhanced Multiplier, yield a full 64-bit result, high performance • I: Embedded ICE hardware The ARM architecture supports two basic types of data: – The standard ARM word is 32 bits long. – The word may be divided into four 8-bit bytes. 9
- 10. Architecture of ARM7 Processor 10
- 11. ARM Registers • ARM has 31 general-purpose 32-bit registers. • At any one time, 16 of these registers are visible. • The other registers are used to speed up exception processing. • All the register specifies in ARM instructions can address any of the 16 visible registers. • The main bank of 16 registers is used by all unprivileged code. • These are the User mode registers. 11
- 12. Status registers • All processor state other than the general- purpose register contents is held in status registers. • Current program status register (CPSR) is the register which is set automatically during every arithmetic, logical, or shifting operation. • The top four bits of the CPSR hold the following useful information about the results of that arithmetic/logical operation. 12
- 13. CISC Vs RISC • Complex instruction set computers (CISC) provides a variety of instructions that may perform very complex tasks, such as string searching; • Reduced instruction set computers (RISC) tends to provide somewhat fewer and simpler instructions. • The instructions were also chosen so that they could be efficiently executed in pipelined processors. • RISC techniques can also use efficiently to execute at least a common subset of CISC instruction sets. 13
- 14. CISC Vs RISC 14
- 15. ARM Instruction Set Branch instructions Data-processing instructions on page Status register transfer instructions on page Load and store instructions on page Coprocessor instructions on page Exception-generating instructions on page. 15
- 16. Branch Instructions • The B (branch) instruction is the basic mechanism in ARM for changing the flow of control. • The address that is the destination of the branch is often called the branch target. • Branches are PC-relative—the branch specifies the offset from the current PC value to the branch target. • The offset is in words, but because the ARM is byte addressable, the offset is multiplied by four (shifted left two bits, actually) to form a byte address. • Thus, the instruction B #400 will add 400 to the current PC value. 16
- 17. Data-processing instructions on page • The data-processing instructions perform calculations on the general-purpose registers. • There are five types of data-processing instructions: Arithmetic/logic instructions Comparison instructions Single Instruction Multiple Data (SIMD) instructions Multiply instructions on page Miscellaneous Data Processing instructions on page. 17
- 18. Status register transfer instructions • The status register transfer instructions transfer the contents of the CPSR or an SPSR to or from a general-purpose register. Writing to the CPSR can: Set the values of the condition code flags Set the values of the interrupt enable bits Set the processor mode and state Alter the endianness of Load and Store operations. 18
- 19. Load and store instructions • Load-Store instructions are used to transfer the Values between registers and memory. – LDRB and STRB load and store bytes rather than whole words, while LDRH and SDRH operate on half-words and LDRSH extends the sign bit on loading. For example: LDR r0,[r1],STR r0,[r1] • The following load and store instructions are available: – Load and Store Register – Load and Store Multiple registers on page – Load and Store Register Exclusive on page. 19
- 20. Coprocessor instructions There are three types of coprocessor instructions: Data-processing instructions • These start a coprocessor-specific internal operation. Data transfer instructions • These transfer coprocessor data to or from memory. The address of the transfer is calculated by the ARM processor. Register transfer instructions • These allow a coprocessor value to be transferred to or from an ARM register, or a pair of ARM registers. 20
- 21. Exception-generating instructions Two types of instruction are designed to cause specific exceptions to occur. Software interrupt instructions • SWI instructions cause a software interrupt exception to occur. • These are normally used to make calls to an operating system, to request an OS-defined service. • The exception entry caused by a SWI instruction also changes to a privileged processor mode. • This allows an unprivileged task to gain access to privileged functions, but only in ways permitted by the OS. 21
- 22. Exception-generating instructions Software breakpoint instructions • BKPT instructions cause an abort exception to occur. • If suitable debugger software is installed on the abort vector, an abort exception generated in this fashion is treated as a breakpoint. • If debug hardware is present in the system, it can instead treat a BKPT instruction directly as a breakpoint, preventing the abort exception from occurring. 22
- 23. Stacks and Subroutines Stack: • The stack is an area of memory identified by the programmer for temporary storage of information. • The stack is a LIFO (Last in First Out.) structure. • The stack normally grows backwards into memory. • In other words, the programmer defines the bottom of the stack and the stack grows up into reducing address range. 23
- 24. Stacks and Subroutines • A subroutine is a group of instructions that will be used repeatedly in different locations of the program. • Rather than repeat the same instructions several times, they can be grouped into a subroutine that is called from the different locations. • In Assembly language, a subroutine can exist anywhere in the code. • However, it is customary to place subroutines separately from the main program. 24
- 25. Stacks and Subroutines • The 8085 has two instructions for dealing with subroutines. • The CALL instruction is used to redirect program execution to the subroutine. • The RTE instruction is used to return the execution to the calling routine. 25
- 26. Features of the LPC 214X Family • The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combines the microcontroller with embedded high speed flash memory ranging from 32 kB to 512 kB. • A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. • Various 32-bit timers, single or dual 10-bit ADC(s), 10- bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 26
- 27. Features • 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. • 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory. • 128 bit wide interface/accelerator enables high speed 60 MHz operation. • In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software. • Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms. • Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real Monitor software and high speed tracing of instruction execution. 27
- 28. Architecture of the LPC 214X Family 28
- 29. Peripherals – The Timer Unit LPC214x Timer Features: • Timer/Counter0 and Timer/Counter1 are functionally identical except for the peripheral base address. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. • Counter or Timer operation 29
- 30. LPC214x Timer Features: Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when inputs signal transitions. A capture event may also optionally generate an interrupt. Four 32-bit match registers that allow: • Continuous operation with optional interrupt generation on match. • Stop timer on match with optional interrupt generation. • Reset timer on match with optional interrupt generation. 30
- 32. LPC214x Pulse Width Modulation • Seven match registers allow up to 6 single edge controlled or 3 double edge Controlled PWM outputs, or a mix of both types. • The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. 32
- 33. LPC214x Pulse Width Modulation • Supports single edge controlled and/or double edge controlled PWM outputs. • Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. • Double edge controlled PWM outputs can have either edge occur at any position within a cycle. • This allows for both positive going and negative going pulses. 33
- 34. Architecture of the LPC214x PWM 34
- 35. LPC214x UART0 35
- 36. LPC214x UART1 36
- 37. Block Diagram of ARM9 37
- 38. ARM Cortex M3 MCU 38