Ethos_cdnliveIsrael
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This document provides a 3-sentence summary of an Ethernet Over Ethernet presentation: The presentation discusses Ethos Networks' 240Gbps platform and cards for providing Ethernet services over Ethernet networks, including their system architecture, design flow using Concept HDL for layout and routing with Allegro tools, and FPGA design using Incisive Enterprise verification. The Ethos platform supports IPTV, mobile backhauling, and video on demand over one network while guaranteeing service level agreements for hundreds of services.
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Ethos_cdnliveIsrael
- 1. Template PresentationSubtitle Ethernet Over Ethernet It can be as simple as that Rafie Grinvald HW & FPGA Manager
- 2. Agenda • Ethos Networks Architecture • Ethos 240Gbps Platform & Cards • Design Flow using Concept • Layout and Routing with Allegro Tools • FPGAs Incisive Enterprise Verification
- 3. IPTVMobile Backhauling VoD One network Hundreds of SLAs Ethos Architecture
- 4. System View 10/100/ 1000 Mbps L2/L3 Services Provisioning Optimization Management EXAMPLE TRANSPARENT LAN SERVICE
- 5. 1. Traffic admission is controlled at network edge… 2. … in real-time, based on traffic conditions across the network 3. Every edge holds an updated topology 4. Every edge holds per- flow service profiles 5. Edges communicate transmission intentions to each other every x ms… 6. ..and perform concerted Admissions Control to ensure that SLAs are met How does it work? Dynamic TE
- 6. Comprehensive Transport Solution Connection-Oriented Ethernet , PBT QoS guaranties per millions of flows Ethernet efficiency, TDM reliability Network capacity tripled Ethos Solution
- 7. System Architecture FE 200 )1( FE 200 )2( FE 200 (n) NP1 PHY's 10x1G Fabric Interface FABRIC )1( FABRIC )2( FABRIC (3) ELIC20 - #1 ECSF1 ECSF2 FPGA1 DynTM NP2 PHY's 10x1G FPGA2 DynTM SFP O/E SFP O/E SFP O/E SFP O/E NP1 PHY's 10x1G Fabric Egress ELIC20 - #2 FPGA1 DynTM NP2 PHY's 10x1G FPGA2 DynTM SFP O/E SFP O/E SFP O/E SFP O/E CONTROL CPU CONTROL CPU CONTROL PLANE DATA PLANE DATA PLANE CONTROL PLANECONTROL SWITCH CONTROL CPU L2 CONTROL SWITCH L2 CONTROL SWITCH RJ45 SER RJ45 SER RJ45 SER CONTROL PLANE DATA PLANE
- 8. IPTVMobile Backhauling VoD One network Hundreds of SLAs Ethos Platform
- 9. Ethos Platforms Ethos E-60 Ethos E-240 60 Gpbs switching 3 x 20 Gbps slots High-density GE and 10GE AC/DC power Ethos E-20 1-2 service slots 1-2 x 20 Gbps slots High-density GE and 10GE AC/DC power 280 Gbps switching 12 x 20 Gbps slots High-density GE and 10GE 2 systems per rack
- 10. Chassis Architecture Ethos Line Interface Cards (ELIC) 1..6 Ethos Line Interface Cards (ELIC) 7..12 Central Switch Fabric (ECSF) 1..2 Fan Tray & Thermal Protection Shelf managers 240Gbps backplane Non-Blocking All-Ethernet Architecture
- 11. ECSF 240G 240G fabric 24G control switch 160Watt Power supplies ATCA 5ms CAPs
- 12. ECSF 240G Features • Switch fabric with 240Gbps capacity • Base fabric 24Gpbs control switch (for Ethos management) • 160Watt power dissipation • Ethos front panel management • Centralized CPU unit • Serial interfaces from front panel for debug and control • Support ATCA Shelf Manager • Complies to ATCA PICMG3.0
- 13. ESCF240G Electrical Features • 160 Watt per Line Card • 280mm x 300mm ATCA card • 22 Layers of PCB, Merix USA • PCB thickness of 3.1mm • ~10,000 Via’s • ~3,000 components • 3 FBGA’s with more than 1300 ball grid pins • 80% of card is high speed differential signals • 20% of card is high speed single ended signals • 288 pairs of serial links at 3.125Gbps Allegro 16.0 Free Physical Viewer
- 14. ELIC 20 Fabric Access NP’s FPGA’s 10 SFP ports 1Gbps 1 XFP port 10Gbps CPU Piggy
- 15. ELIC20 Features • 20Gbps line card with inline Network Processors • 10 x 1Gb SFP copper (1000Base-T) or fiber interfaces • 1 x 10Gb XFP fiber interface • 20Gb fabric interface • 10/100/1000Base-T in front panel for OOB (Out Of Band) management (standalone) • Serial interface from front panel • Complies to ATCA PICMG3.0 • Ethos IP fully aware
- 16. ELIC20 Electrical Features • 200 Watt per line card • 280mm x 300mm ATCA card • 26 Layers of PCB with cutting edge laser technology ,Merix USA • PCB thickness of 3.2mm • ~49,000 Via’s • ~7,000 components • 48Gbit DDR2 @ 667Mbps components • 5 FBGA’s with more than 1300 ball grid pins • 20% of card is high speed differential signals • 80% of card is high speed single ended signals Allegro 16.0 Free Physical Viewer
- 17. IPTVMobile Backhauling VoD One network Hundreds of SLAs Ethos Design flow with Concept HDL
- 18. Design Flow with Concept HDL Card Architecture: • Basic card architecture was ready after 2 months from green light • All major components passed test benches prior to choosing IC vendors • Physical placement tests were done after choosing IC vendors • Physical placement led to thermal simulations tests Thermal simulationsplacement test
- 19. Design Flow with Concept HDL Concept HDL CAD Library: • Building around 150 different components • All components include issues of layout and simulation aspects • CAD library is in Excel format and can be imported to any operation database
- 20. Design Flow with Concept HDL Design Hierarchy: • Top down hierarchy design • Design comprised of over 100 pages • Database of 500MB (in HDL format) Concept HDL 15.5.1 Hierarchy Tree Top down Hierarchy
- 21. Design Flow with Concept HDL Drawing Blocks: • Design of ~7,000 components around 3 months • ~25,000 nets over the ELIC card drawn • Design with layout consideration: – Designing power planes – Adding constrains – EMC considerations – Mechanical issues
- 22. Design Flow with Concept HDL Integration Hierarchy: • The use of block instantiations reduced drawing cycle • BOM (Bill Of Material) issues: – All components marked with N/A tag – BOM variants tool was implemented (including multiple assemblies) – BOM can be easily exported to excel and to any operational data base
- 23. Design Flow with Concept HDL Simulations: • Only major items were tested at simulation phase (DDRII, differential lines) • SigXplorer simulation suite was used • IBIS up to 1GHz or SPICE models can be used SigXplorer Testing example
- 24. Design Flow with Concept HDL Netlist Checking: • Only major components were tested • DRC (Design Rule Check) running is recommended before Netlist checking • No software application can test logical insights • Bug fixing is done at drawing blocks phase • Netlist checking takes around 1 month in parallel to routing (25,000 nets) • All nets should include routing name Netlist checking with proprietary scripts
- 25. Concept HDL Summary Advantages: • Works well with large schemes (~500M) • HDL/ASCII engine enables easy reading and block checking • High integration with simulation and layout Software Possible Improvements: • Support of team work • ConceptHDL unstable under Linux • Limitations on back annotation from Layout tool to ConceptHDL with instantiations
- 26. IPTVMobile Backhauling VoD One network Hundreds of SLAs Ethos Card layout with Allegro
- 27. Layout Flow with Allegro Card Netlist Ready: • Netlist passed with bugs, but with full components count • First Netlist draft passed after 3 months of scheme drawings • Support of technologist engineer begins from netlist to fabrication portfolio
- 28. Layout Flow with Allegro Components Building: • All datasheets should be ready before passing netlist • All components were built with control of Ethos and checked to fit datasheets and part numbers FBGA ~1500 FBGA ~500 Ethernet transformer CAP 0603 Resistor 0402 * Layout pics courtesy of Oranit-PCB LLD
- 29. Layout Flow with Allegro Card Placement: • DXF should be ready prior to placement • Placement according to thermal simulations • Final placement to be confirmed by thermal, mechanical & technological engineers ELIC20 CS ELIC20 PS
- 30. Layout Flow with Allegro Technology: • Stack-up should be ready before routing starts (including power planes and EMC issues) • All library components checked by technologist to confirm pad size, etc… • Simulation of microstrip, or stripline done for single ended and differential pairs of each layer. • All technology aspects confirmed by PCB manufacturer and card assembly factory * Technology support by Invitech, Mr Victor Shimoni
- 31. Layout Flow with Allegro Routing: • 25,000 nets routed manually ~ 3 months • Routing starts at fan-out of all components at placement phase • Routing takes into account netlist bugs Allegro 15.5.1
- 32. Layout Flow with Allegro Routing & Constrains: • Around ~1,000 constrains made at schemes drawing phase • Constrains help to control & find bugs at routing phase • Fixing routing according to constrains can take around 3 weeks Constraint manager
- 33. Layout Flow with Allegro Back Annotation & Silk: • Silk & refdes should be back annotated to design Concept HDL • Small areas of layout can be back annotated • All 0402 components were removed from silk (hard to debug)
- 34. Layout Flow with Allegro DFM (Design For Manufacturing): • All cards routing passed Valor manufacturing tests (net-to-via proximity, etc…) • Around 12,000 errors where discovered & fixed DFA (Design For Assembly): • All cards passed Valor assembly checking for placement problems • BGA keeps 2.5mm from all sides for possible conflicts at work around
- 35. Layout Flow with Allegro Fabrication Portfolio Ready: • All DFA, DFM, Thermal, Mechanics, Technology aspects tested and checked • Gerbers, ODB databases sent to PCB and assembly manufactures • Standard PCB (through VIA’s) delivered within 5 working days • Laser 1-2 ,1-3 PCB (HDI technology) delivered within 10-12 working days
- 36. Allegro Summary Advantages: • Team sharing and integration (at peak time up to 8 layout designers worked together) Possible Improvements: • At final stages of layout ,large files were hard to manage • Back annotation to Concept need to have better support of instantiations blocks
- 37. IPTVMobile Backhauling VoD One network Hundreds of SLAs Ethos FPGA Design with Incisive Enterprise
- 38. FPGA Design with Incisive Enterprise DynTE TM (Dynamic Traffic Engineering) FPGA : • 10Gbps full duplex SPI4.2 based interfaces • 5 x DDRII @ 667Mbps interfaces • 3 x QDRII @ 250MHz • 800 functional I/O’s • Equivalent of 4Mgates of ASIC • All components written in Ethos and Ethos-IP • Verification under Linux RH enterprise 4.0 x64bit version • Incisive Enterprise 5.8 edition
- 39. FPGA Design with Incisive Enterprise Block Functional Specification : • Functional specs were written for each block • All blocks are part of TOP functional spec HLD (High Level Design) Documents : • HLD is written for each block • From HLD each team writes the LLD LLD (Low Level Design) Documents: • LLD is detailed down to logical gates before code writing starts • E-coding referring to block HLD only High Level Design Low Level Design Verilog coding debug Block Func spec TOP Block integration Low Level modeling E-coding coding Debug / Verilog fixing Debug / e fixing
- 40. FPGA Design with Incisive Enterprise High Level Design Low Level Design Verilog coding debug Block Func spec TOP Block integration Low Level modeling E-coding coding Debug / Verilog fixing Debug / e fixing E-coding: • E-code coded at Eclipse Open-source environment • E-code is version controlled within SVN open source tool • eRM methodology reduces coding time (interfaces, chip level reuse) Eclipse environment Support e-language color coding
- 41. FPGA Design with Incisive Enterprise Debug: • E-code and V-code are prepared prior to debug phase • Bugs are documented in Bugzilla Open-source tool • Debug of each block includes coverage function High Level Design Low Level Design Verilog coding debug Block Func spec TOP Block integration Low Level modeling E-coding coding Debug / Verilog fixing Debug / e fixing Specman environment Packet inspection Debug runtime with breakpoints
- 42. FPGA Design with Incisive Enterprise Debug: • Integrated environment of ncVerilog & Specman helps reduce simulations cycles • Full chip logical simulation run for 8 hours High Level Design Low Level Design Verilog coding debug Block Func spec TOP Block integration Low Level modeling E-coding coding Debug / Verilog fixing Debug / e fixing SimVision environment wave forms
- 43. FPGA Design with Incisive Enterprise Advantages: • Bugs found by verification reduce the lab debug cycle • eRM writing methodology reduce coding time • VR_AD of CPU (great model !!) reduced time and coding of CPU interface (register and memory model package) • IE enable excellent team work methodology Possible Improvements: • Integration of IE tools will reduce time at simulation stage • Support of IC (DDR, QDR etc..) models to improve simulation time
- 44. Ethos - es [NL, fr. GK ēthos] character, sentiment, the guiding beliefs, standards, the spirit that motivates the ideas