Floating point arithmetic operations (1)
- 2. • 2 parts – Mantissa->signed fixed point number – exponent->the position of the decimal(binary) point – Eg:6132.739 – +06132739->fraction – 4-> exponent – Similar to +0.6132739*10^+4 • General form M*r^e – M->mantissa – r->radix – E->exponent
- 3. • For binary fp; – Similar to fp decimal point, but uses radix 2 – Eg:+1001.11 – 01001110(mantssa) – 000100(exponent)
- 4. Normalization • A floating point no. is said to be normalized if the most significant digit of the mantissa is nonzero. • Eg:350->normalized – 00035-> not normalized. – Can be normalized by shifting it 3 positions to the left and discarding the leading zeros.(10^3) • Zero cannot be normalized bcoz it doesnot have a nonzero digit. – Denoted by all zeros at mantissa and exponenet.
- 5. • Operations on fp numbers requires complex hardware and takes more time. • Addition or subtraction requires: – Alignment of radix point(exponents must be equal). – Done by shifting mantissa and adjust exponent accordingly. – Eg: 0.5372400*10^2+ 0.1580000*10^-1
- 6. • Either shift the 1st no 3 positions to the left or shift the 2nd by 3 position to the right. • 2nd method is more preferable. – So, .5272400*10^2+ .0001580*10^2 .5373980 *10^2 Normalized addition will cause an overflow and can be corrected by shifting the sum once to the right and incrementing the exponent.
- 7. • Underflow – Floating point number has a 0 in the MSB of the mantissa. – Shift the mantissa to the left and decrement the exponent(normalization) • Multiplication and division doesnot require alignment. – Result(multiply mantissa and add the exponent for multiplication) – Divide the mantissa and subtract the exponent for division
- 8. • The operation performed with exponent are: – Compare &increment(align mantissa) – Add &subtract(multiplication and division) – Decrement(nomalization) • Exponent representation – Signed magnitude – Signed 2’s complement – Signed 1’s complement – Biased exponent
- 9. • In biased exponent – Sign bit is not taken as separate entity. – Is a +ve number that is added to each exponent as the floating point number is formed. – Internally all exponents are +ve. – the bias, is subtracted from the field to get the true exponent value. • Bias=(2k-1-1), where k is the number of bits in the binary exponent.
- 10. • Advantages – They contain only positive numbers(easy to compare) – The smallest possible biased exponent contains all zeros
- 13. IEEE Standard for Binary Floating- Point Representation • IEEE 754 in 1985. • developed to facilitate the portability of • programs from one processor to another and to encourage the development of sophisticated, numerically oriented programs.
- 14. IEEE 754 Formats
- 15. Parameter List
- 16. Register Configuration • The same registers & adders are in the case of fixed point arithmetic are used for processing mantissa. • Differs the way in which exponents are handled
- 18. • BR,AC,QR(divided into 2 parts). • Mantissa is stored in B,A and Q registers • Exponent in b,a,q registers. – Mantissa in signed magnitude in A and sign in As and MSB in A1. – Biased exponent in a. – A1->1 if the no. Has to be normalized – Similarly for other registers
- 19. • 2Parallel adders – 1 ,Adds two mantissas and sum stores in A,Carry to E. – 2nd adds the exponents(don’t have distinct sign bit,but taken as +ve). • Exponent overflow is neglected. • Exponents are connected to comparator that provides 3 binary outputs to indicate their relative magnitude.
- 20. • The number in the mantissa is taken as a fraction, so binary point resides to the left of the magnitude part. • Numbers are normalized both during initial and after the operation.
- 21. A floating point operation may produce:
- 22. Addition and Subtraction • 1. Check for zeros. • 2. Align the mantissas. • 3. Add or subtract the mantissas. • 4. Normalize the result.
- 24. Multiplication • multiply the mantissas and add the exponents. • No comparison of exponents or alignment of mantissas is necessary.
- 25. • Four components: 1. Check for zeros. 2. Add the exponents. 3. Multiply the mantissas. 4. Normalize the product.
- 28. Division • Floating-point division requires that the exponents be subtracted and the mantissas divided. • The mantissa division is done as in fixed-point except that the dividend has a single-precision mantissa that is placed in the AC.
- 29. • Check for zeros. • Initialize registers and evaluate the sign • Align the dividend(divide overflow check in fixp). • Subtract the exponents. • Divide the mantissas.
- 32. Decimal Arithmetic Unit • is a digital function that performs decimal • microoperations. • can add or subtract decimal numbers, usually by forming the 9's or 10's complement of the subtrahend. • The unit accepts coded decimal numbers and generates results in the same adopted binary code.
- 33. • A single-stage decimal arithmetic unit consists of: – nine binary input variables – five binary output variables – ( since a minimum of four bits is required to represent each coded decimal digit) • Each stage must have four inputs for the augend digit, four inputs for the addend digit, and an input-carry.
- 34. • The outputs include four terminals for the sum digit and one for the output-carry.
- 35. Once cell of Decimal additiom
- 37. Addition and Subtraction • Addition – Parallel decimal adder – Digit-serial. Bit-parallel decimal addition – All serial decimal addition
- 40. All serial decimal addition
- 41. Multiplication
- 42. Registers for decimal arithmetic multiplication and division
- 43. • Ae- to accommodate overflow(adding the multiplicand to the partial product) • Be-to form the 9’s complement of the divisor when subtracted from the partial remainder.
- 45. Division
- 46. Arithmetic and Logic Unit • Is a multioperation, combinational logic digital function. • Perform – a set of basic arithmetic operations – Set of logical operations • No. Of selection lines(to select a particular operation). • K selection variables->2k distinct operations.
- 47. 4 bit ALU
- 48. • Design of ALU will be carried out in 3stages: – Design of arithmetic section – Design of logic section – The arithmetic section will be modified so that it can perform both arithmetic and logic operations.
- 49. Design of Arithmetic unit
- 53. Design of LogiC Circuit
- 54. Combining Logic & Arithmetic Circuits
- 55. Function Table
- 57. Design of Arithmetic & Logic Circuit
- 58. Design of Arithmetic & Logic Circuit
- 59. • When S2=0
- 60. • When s2=1
- 61. Function Table