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PRESENTATION BY:-
 ASHUTOSH SHARMA
 UTKARSH DE
 SHRAWAN RAWAT
 LALIT KUMAR
 SHUBHAM SHARMA
INTRODUCTION
TRAFFIC LIGHTS
HISTORY
VERILOG
FOUR WAY TLC
TRAFFIC LIGHT STATE DIAGRAM
OUR TRAFFIC LIGHT
STATE TABLE
STATE DIAGRAM
WAVEFORM
CODING OVERVIEW
FUTURE SCOPE
CONCLUSION
 HISTORY
 Traffic light which is one of the vital
public facilities that plays an important
role to the road users. Traffic lights
were first installed in 1868 in London,
United Kingdom, outside the British
Houses of Parliament in London, by the
railway engineer J. P. Knight and
constructed by the railway signal
engineers of Saxby & Farmer.
 The design combined three semaphore arms with
red and green gas lamps for night-time use, on a
pillar, operated by a police constable. The gas
lantern was turned with a lever at its base so that
the appropriate light faced traffic. Although it
was said to be successful at controlling traffic, its
operational life was brief. It exploded on 2
January 1869, as a result of a leak in one of the
gas lines underneath the pavement, injuring and
killing the policeman who was operating it. With
doubts about its safety, the concept was
abandoned until electric signals became available
.
 Traffic lights, also known as traffic signals,
traffic lamps, signal lights, stop lights and
also known technically as traffic control
signals are signalling devices positioned at
road intersections, pedestrian crossings and
other locations to control competing flows of
traffic.
 Traffic lights alternate the right of
way accorded to road users by
displaying lights of a standard color
(red, yellow, and green) following a
universal color code.
 The typical sequence of color phases
are as follows:
 GREEN:- Allows traffic to proceed in
the direction denoted.
 YELLOW:- Provides warning that the
signal will be changing from
green to red.
 RED:- Prohibits any traffic from
proceeding.
 1. Safe and efficient traffic light flow
 2. Assign right of way to maximize
capacity, minimize and reduce
collision and conflict
 Verilog HDL is one of the two most common
Hardware Description Languages (HDL)
used by integrated circuit
 (IC) designers. The other one is VHDL.
 HDL’s allows the design to be simulated
earlier in the design cycle in order to
correct errors or experiment with different
architectures. Designs described in HDL are
technology-independent, easy to design
and debug, and are
 usually more readable than schematics, particularly
for large circuits.
 Verilog can be used to describe designs at four
levels of abstraction:
 (i) Algorithmic level (much like c code with if, case
and loop statements).
 (ii) Register transfer level (RTL uses registers
connected by Boolean equations).
 (iii) Gate level (interconnected AND, NOR etc.).
 (iv) Switch level (the switches are MOS transistors
inside gates).
 It is often useful to be able to
sequence through an arbitrary
number of states , staying in each
state an arbitrary amount of time.
 Consider the set of traffic lights
shown in Figure.
Four way traffic light conrol using Verilog
 The lights are assumed to be at a
four-way intersection with one
street going north-south and the
other road going east-west.
Four way traffic light conrol using Verilog
 To simulate these traffic lights we will use the
red, yellow, and green LEDs which cycle
through the six states shown in Table .
Four way traffic light conrol using Verilog
 A state diagram for controlling these traffic
lights is shown in Fig.
Four way traffic light conrol using Verilog
 If we use a 3 Hz clock to drive this state
diagram then a delay of 1 second is
achieved by staying in a state for three
clock cycles.
 Similarly, a delay of 5 second is achieved by
staying in a state for fifteen clock cycles.
 The count variable in fig will be
reset to zero when moving to the
next state after a timeout.
 case(state)
 S0: if(count < SEC5)
◦ begin
 state <= S0;
 count <= count + 1;
◦ end
 else
◦ begin
 state <= S1;
 count <= 0;
◦ end
 S1: if(count < SEC1)
◦ begin
 state <= S1;
 count <= count + 1;
◦ end
 else
◦ begin
 state <= S2;
 count <= 0;
◦ end
 :
 Development of Software of Intelligent Traffic Light
Control and Monitoring System :
Assembler
 Assembler is used to convert the assembly
language code to machine code. A51
assembler is used for this purpose.
Following Figure shows the A51 assembler
GUI.
Four way traffic light conrol using Verilog
 The modern ways of multi-way traffic
management improves the traffic condition
up to a large extent. Advanced signaling
controllers contribute to the improvement
of the urban traffic which is proportional to
the complexity of the controller. These
more complex controllers can be well
handled using states machines. Methods to
reduce the states in the state machine also
help in reducing the required hardware
leading to low power and area efficient
design. In addition to the general procedure
the Chip Scope Pro & VIO of Xilinx tool
gives the flexibility in verification for the
design with large number of inputs &
outputs, also used for easy implementation
of the design into the FPGA.
Four way traffic light conrol using Verilog

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Four way traffic light conrol using Verilog

  • 1. PRESENTATION BY:-  ASHUTOSH SHARMA  UTKARSH DE  SHRAWAN RAWAT  LALIT KUMAR  SHUBHAM SHARMA
  • 2. INTRODUCTION TRAFFIC LIGHTS HISTORY VERILOG FOUR WAY TLC TRAFFIC LIGHT STATE DIAGRAM OUR TRAFFIC LIGHT STATE TABLE STATE DIAGRAM WAVEFORM CODING OVERVIEW FUTURE SCOPE CONCLUSION
  • 3.  HISTORY  Traffic light which is one of the vital public facilities that plays an important role to the road users. Traffic lights were first installed in 1868 in London, United Kingdom, outside the British Houses of Parliament in London, by the railway engineer J. P. Knight and constructed by the railway signal engineers of Saxby & Farmer.
  • 4.  The design combined three semaphore arms with red and green gas lamps for night-time use, on a pillar, operated by a police constable. The gas lantern was turned with a lever at its base so that the appropriate light faced traffic. Although it was said to be successful at controlling traffic, its operational life was brief. It exploded on 2 January 1869, as a result of a leak in one of the gas lines underneath the pavement, injuring and killing the policeman who was operating it. With doubts about its safety, the concept was abandoned until electric signals became available .
  • 5.  Traffic lights, also known as traffic signals, traffic lamps, signal lights, stop lights and also known technically as traffic control signals are signalling devices positioned at road intersections, pedestrian crossings and other locations to control competing flows of traffic.
  • 6.  Traffic lights alternate the right of way accorded to road users by displaying lights of a standard color (red, yellow, and green) following a universal color code.  The typical sequence of color phases are as follows:
  • 7.  GREEN:- Allows traffic to proceed in the direction denoted.  YELLOW:- Provides warning that the signal will be changing from green to red.  RED:- Prohibits any traffic from proceeding.
  • 8.  1. Safe and efficient traffic light flow  2. Assign right of way to maximize capacity, minimize and reduce collision and conflict
  • 9.  Verilog HDL is one of the two most common Hardware Description Languages (HDL) used by integrated circuit  (IC) designers. The other one is VHDL.  HDL’s allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology-independent, easy to design and debug, and are
  • 10.  usually more readable than schematics, particularly for large circuits.  Verilog can be used to describe designs at four levels of abstraction:  (i) Algorithmic level (much like c code with if, case and loop statements).  (ii) Register transfer level (RTL uses registers connected by Boolean equations).  (iii) Gate level (interconnected AND, NOR etc.).  (iv) Switch level (the switches are MOS transistors inside gates).
  • 11.  It is often useful to be able to sequence through an arbitrary number of states , staying in each state an arbitrary amount of time.  Consider the set of traffic lights shown in Figure.
  • 13.  The lights are assumed to be at a four-way intersection with one street going north-south and the other road going east-west.
  • 15.  To simulate these traffic lights we will use the red, yellow, and green LEDs which cycle through the six states shown in Table .
  • 17.  A state diagram for controlling these traffic lights is shown in Fig.
  • 19.  If we use a 3 Hz clock to drive this state diagram then a delay of 1 second is achieved by staying in a state for three clock cycles.  Similarly, a delay of 5 second is achieved by staying in a state for fifteen clock cycles.
  • 20.  The count variable in fig will be reset to zero when moving to the next state after a timeout.
  • 21.  case(state)  S0: if(count < SEC5) ◦ begin  state <= S0;  count <= count + 1; ◦ end
  • 22.  else ◦ begin  state <= S1;  count <= 0; ◦ end
  • 23.  S1: if(count < SEC1) ◦ begin  state <= S1;  count <= count + 1; ◦ end
  • 24.  else ◦ begin  state <= S2;  count <= 0; ◦ end
  • 25.  :
  • 26.  Development of Software of Intelligent Traffic Light Control and Monitoring System : Assembler  Assembler is used to convert the assembly language code to machine code. A51 assembler is used for this purpose. Following Figure shows the A51 assembler GUI.
  • 28.  The modern ways of multi-way traffic management improves the traffic condition up to a large extent. Advanced signaling controllers contribute to the improvement of the urban traffic which is proportional to the complexity of the controller. These more complex controllers can be well handled using states machines. Methods to reduce the states in the state machine also help in reducing the required hardware
  • 29. leading to low power and area efficient design. In addition to the general procedure the Chip Scope Pro & VIO of Xilinx tool gives the flexibility in verification for the design with large number of inputs & outputs, also used for easy implementation of the design into the FPGA.