fpga1 - What is.pptx

CS295: Modern Systems
What Are FPGAs
and Why Should You Care
Sang-Woo Jun
Spring, 2019

What Are FPGAs
 Field-Programmable Gate Array
 Can be configured to act like any circuit – More later!
 Can do many things, but we focus on computation acceleration

FPGAs Come In Many Forms
PCIe-Attached
CPU Integrated In-Network
In-Storage

How Is It Different From CPU/GPUs
 GPU – The other major accelerator
 CPU/GPU hardware is fixed
o “General purpose”
o we write programs (sequence of instructions) for them
 FPGA hardware is not fixed
o “Special purpose”
o Hardware can be whatever we want
o Will our hardware require/support software? Maybe!
 Optimized hardware is very efficient
o GPU-level performance**
o 10x power efficiency (300 W vs 30 W)

Analogy
“The Z-Berry”
“Experimental Investigations on Radiation Characteristics of IC Chips”
benryves.com “Z80 Computer”
CPU/GPU comes with fixed circuits FPGA gives you a big bag of components
To build whatever
Shadi Soundation: Homebrew 4 bit CPU
Could be a CPU/GPU!

Fine-Grained Parallelism of
Special-Purpose Circuits
 Example -- Calculating gravitational force:
𝐺×𝑚1×𝑚2
(𝑥1−𝑥2)2+(𝑦1−𝑦2)2
 8 instructions on a CPU → 8 cycles**
 Much fewer cycles on a special purpose circuit
A = G × m1
B = A × m2
C = x1 - x2
D = C2
E = y1 - y2
F = E2
G = D + F
Ret = B / G
A = G × m1 × m2 B = (x1 -x2)2 C = (y1 -y2)2
D = B + C
Ret = B / G
4 cycles with basic operations
3 cycles with compound operations
Ret = (G × m1 × m2) / ((x1 - x2)2 + (y1 -y2)2)
1 cycle with even further compound operations
May slow down clock

Coarse-Grained Parallelism of
Special-Purpose Circuits
 Typical unit of parallelism for general-purpose units are threads ~= cores
 Special-purpose processing units can also be replicated for parallelism
o Large, complex processing units: Few can fit in chip
o Small, simple processing units: Many can fit in chip
 Only generates hardware useful for the application
o Instruction? Decoding? Cache? Coherence?

How Is It Different From ASICs
 ASIC (Application-Specific Integrated Circuit)
o Special chip purpose-built for an application
o E.g., ASIC bitcoin miner, Intel neural network accelerator
o Function cannot be changed once expensively built
 + FPGAs can be field-programmed
o Function can be changed completely whenever
o FPGA fabric emulates custom circuits
 - Emulated circuits are not as efficient as bare-metal
o ~10x performance (larger circuits, faster clock)
o ~10x power efficiency

Basic FPGA Architecture
“Configurable logic block (CLB)”
Programmable interconnect
I/O block
6-Input
Look-Up
Table
FF
Latch
Programmable
Input 1 Input 2 Output
0 0 0
0 1 0
1 0 0
1 1 1
Ex) 2-LUT for “AND”
~
Sequential circuit
construction

Basic FPGA Architecture – DSP Blocks
 CLBs act as gates – Many needed to
implement high-level logic
 Arithmetic operation provided as
efficient ALU blocks
o “Digital Signal Processing (DSP) blocks”
o Each block provides an adder + multiplier
“DSP block”
× +/-

Basic FPGA Architecture – Block RAM
 CLB can act as flip-flops
o (~1 bit/block) – tiny!
 Some on-chip SRAM provided as blocks
o ~18/36 Kbit/block, MBs per chip
o Massively parallel access to data → multi-
TB/s bandwidth
“Block RAM”

Basic FPGA Architecture – Hard Cores
 Some functions are provided as
efficient, non-configurable “hard cores”
o Multi-core ARM cores (“Zynq” series)
o Multi-Gigabit Transceivers
o PCIe/Ethernet PHY
o Memory controllers
o …
ARM PCIe
Ethernet
Memory

Example Accelerator Card Architecture
PCIe
FPGA
DRAM
DRAM
1GbE
FMC
40GbE
 “FPGA Mezzanine Card” Expansion
o Network Ports, Memory, Storage, PCIe, …
General-Purpose I/O Pins Multi-Gigabit Transceivers

Example Accelerator Card (VCU108)

Programming FPGAs
 Languages and tools overlap with ASIC/VLSI design
 FPGAs for acceleration typically done with either
o Hardware Description Languages (HDL): Register-Transfer Level (RTL) languages
o High-Level Synthesis: Compiler translates software programming languages to RTL
 RTL models a circuit using:
o Registers (state), and
o Combinational logic (computation)

Hardware Description Language
 Software programming languages: Describes process
 Hardware description languages: Describes structure
FIFO#(Float) input_queue <- mkFIFO;
FIFO#(Float) output_queue <- mkFIFO;
Reg#(Float) factor <- mkReg;
FloatMultIfc mult <- mkFloatMult;
rule in;
mult.enq(factor, input_queue.first);
input_queue.deq;
endrule
rule out;
ret <- mult.result;
output_queue.enq(ret);
endrule
std::queue<float> input_queue;
std::queue<float> output_queue;
float factor;
while (true) {
if ( !input_queue.empty() ) {
ret = input_queue.front() * factor;
output_queue.push(ret)
input_queue.pop();
}
}
Exists in memory Exists on chip
Creates
circuits
Instructions
For CPU

Major Hardware Description Languages
 Verilog: Most widely used in industry
o Relatively low-level language supported by everyone
 Chisel – Compiles to Verilog
o Relatively high-level language from Berkeley
o Embedded in the Scala programming language
o Prominently used in RISC-V development (Rocket core, etc)
 Bluespec – Compiles to Verilog
o Relatively high-level language from MIT
o Supports types, interfaces, etc
o Also active RISC-V development (Piccolo, etc)

High-Level Synthesis
 Compiler translates software programming languages to RTL
 High-Level Synthesis compiler from Xilinx, Altera/Intel
o Compiles C/C++, annotated with #pragma’s into RTL
o Theory/history behind it is a complex can of worms we won’t go into
o Personal experience: needs to be HEAVILY annotated to get performance
o Anecdote: Naïve RISC-V in Vivado HLS achieves IPC of 0.0002 [1], 0.04 after
optimizations [2]
 OpenCL
o Inherently parallel language more efficiently translated to hardware
o Stable software interface
[1] http://msyksphinz.hatenablog.com/entry/2019/02/20/040000
[2] http://msyksphinz.hatenablog.com/entry/2019/02/27/040000

FPGA Compilation Toolchain
High-Level
HDL Code
Language
Compiler
Verilog/
VHDL Synthesize Netlist
Map/
Place/
Route
Bitfile
High-level language vendor tool
FPGA Vendor toolchain (Few open source)
Constraint
File
“Which transceiver instance should
top_transceiver_01 map to?”
And so, so much more…
Cycle-level
Simulation
Functional
Simulation

Programming/Using an FPGA Accelerator
 Bitfile is programmed to FPGA over “JTAG” interface
o Typically used over USB cable
o Supports FPGA programming, limited debugging access, etc
 PCIe-attached FPGA accelerator card is typically used similarly to GPUs
o Program FPGA, execute software
o Software copies data to FPGA board, notify FPGA
-> FPGA logic performs computations
-> Software copies data back from FPGA
 FPGA flexibility gives immense freedom of usage patterns
o Streaming, coherent memory, …

Partial Reconfiguration
FPGA
Sub-components  Parts of the FPGA can be
swapped out dynamically
without turning off FPGA
o Physical area is drawn on chip
 Used in Amazon F1, etc
 Toolchain support for
isolation

FPGAs In The Cloud
 Amazon EC2 F1 instance (1 – 4 FPGAs)
 Microsoft Azure, etc…

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