2. Pipelining – Basic 5-stage and
deeper pipelines
• Breaks instruction execution into stages (Fetch, Decode, Execute, Memory,
Write-back) to increase throughput.
3. Pipelining – Handling hazards:
data, control, structural
• Techniques to resolve conflicts when multiple instructions compete for
resources or depend on each other.
4. Pipelining – Forwarding, stalling,
flushing
• Mechanisms to handle hazards: data forwarding to bypass results, stalls to
delay execution, and flushes on branch mispredicts.
5. Superscalar Execution – Multiple
instructions per cycle
• Allows the processor to issue and execute more than one instruction per
clock cycle.
6. Superscalar Execution – Issue
width and dispatch logic
• Defines how many instructions can be issued per cycle and how they are
dispatched to execution units.
7. Out-of-Order Execution (OoO) -
Dynamic Scheduling – Instruction
window
• A buffer holding instructions waiting to be issued out-of-order.
8. Out-of-Order Execution (OoO) -
Dynamic Scheduling – Reorder
Buffer (ROB)
• Ensures instructions retire in-order for correct program behavior.
9. Out-of-Order Execution (OoO) -
Dynamic Scheduling – Reservation
Stations
• Hold instructions until their operands are ready, enabling dynamic
scheduling.
11. Scoreboarding – Dependency
tracking without renaming
• Tracks instruction status to decide when it can execute, managing hazards
without renaming.
12. Tomasulo’s Algorithm – Dynamic
scheduling with register renaming
and hazard resolution
• A classic algorithm that combines renaming and reservation stations for
out-of-order execution.
13. Speculative Execution – Control
speculation
• Executes instructions before knowing if a branch is taken.
14. Speculative Execution – Value
speculation
• Guesses values of operands to execute dependent instructions early.
15. Branch Prediction – Static and
dynamic prediction
• Static uses fixed strategies; dynamic learns patterns during execution.
17. Software Pipelining – Compiler-
level ILP for loops
• Rearranges loop iterations so multiple steps from different iterations
execute in parallel.
18. Software Pipelining – Delayed
Branch
• A technique where the instruction after a branch is always executed, used
to reduce control hazards.
19. Loop Unrolling – Expose more
parallelism to hardware
• Duplicates loop body to reduce overhead and reveal more instructions for
parallel execution.
20. VLIW (Very Long Instruction Word)
– Compiler-managed ILP
• Relies on compiler to pack independent instructions into a single wide
instruction.
21. VLIW (Very Long Instruction Word)
– EPIC (Intel Itanium)
• An advanced form of VLIW with explicit parallelism hints in the instruction.
22. Instruction Fusion & Micro-op
Fusion – Combine related
operations (e.g., compare+branch)
• Combines multiple operations into a single micro-op to save cycles and
resources.
23. Control Independence – Execute
instructions beyond unresolved
branches
• Speculatively executes instructions not affected by branch outcome.
