Implementation of Carry Skip Adder using PTL
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The document proposes a design and implementation of a carry skip adder using pass transistor logic to improve performance over a conventional carry skip adder. It describes the structures of a conventional carry skip adder and the proposed pass transistor logic carry skip adder. Simulation results show that the proposed design reduces the number of transistors, area, delay, and average power compared to the conventional carry skip adder.
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
© 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 2202
Fig -2: General Pass Tansistor
4. PROPOSED CSKA
The proposed carry skip adder architecture is
constructed using pass transistors. Here only the full
adder and multiplexer are constructed using PTL and
propagate block is similar to that of the conventional
CSKA. The proposed CSKA requires 472 transistors to
construct and the working principal is exactly similar to
the conventional CSKA, only difference is the internal
structures, which can be shown in figures 3 and 4.
Fig -3: Internal Structure of FA using PTL [9]
Fig - 4: Internal structure of 2:1 MUX using PTL
5. SIMULATION AND COMPARISION
Simulation of both proposed and conventional
carry skip adder is carried out in Cadence Virtuoso 6.1.4
software in 90nm technology and the results are
compared. Results and comparison is shown below,
Fig -5: Schematic of proposed CSKA
Fig -6: Test Bench of proposed CSKA
Fig -7: Output showing from S0 to S5 of proposed CSKA](https://image.slidesharecdn.com/irjet-v4i8397-170926091552/85/Implementation-of-Carry-Skip-Adder-using-PTL-2-320.jpg)
![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072
© 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 2203
Fig -8: Output showing from S6 to S11 of proposed CSKA
Fig -9: Output showing from S12 to S15 and Cout of proposed
CSKA
Table -1: Comparison of Conventional CSKA and Proposed
CSKA
Factors Conventional
CSKA
Proposed CSKA
Number of
Transistors 920 472
Area 782 µm2 272 µm2
Delay 136.8 ps 38.61 ps
Average Power 494.1 mW 351.2 mW
6. CONCLUSION AND FUTURE SCOPE
The proposed CSKA using pass transistor logic has
achieved major enhancement compared to that of the
conventional CSKA. From the Table 1 we can see that
transistor count, area, delay and average power, are nearly
halved compared to the conventional CSKA. Thus the
proposed CSKA is a good competitor for low power and
high speed electronic applications. In future, the proposed
CSKA can be enhanced as there is voltage drop since PTL
cannot output the same voltage level of the input voltage.
REFERENCES
[1] Jasmine Saini and Somya Agarwal, “Performance,
Analysis and comparison of Digital Adders”, 2015.
[2] Jigyasa and Kumar Saurabh, “Analysis of modified
hybrid Full Adder with high speed”, 2013.
[3] Jasbir Kaur and Lalit Sood, “Comparison between
various types of adder topologies”, 2015.
[4] Adoni Shiva Pradeep and S. Feroz Shah Ahmed, “A
novel high speed carry skip adder with AOI and OAI
logic using verilog HDL”, 2016.
[5] Khushbu Nagori and Suman Nehra, “Design of a high
speed and low power 4 Bit Carry Skip Adder”, March
2017.
[6] Pooja Singh and Rajesh Mehra, “Design Analysis of
XOR Gates Using CMOS & Pass Transistor Logic”, July
2014.
[7] D. Markovic, B. Nikolic and V.G. Oklobdzija, “A general
method in synthesis of pass-transistor circuits”, 2000.
[8] Min Cha and Earl E. Swartzlander, “Modified Carry
Skip Adder for reducing first block delay”, 2000.
[9] J.Princy Joice, M.Anitha and Mrs.I.Rexlin Sheeba,
“Design of carry save adder using transmission gate
logic”, Jan 2015.
[10] Pournima Pankaj Patil and Archana Arvind Hatkar “A
Comparative analysis of 8-bit carry skip adder using
CMOS and PTL techniques with conventional MOSFET
at 32nm regime”, 2016.](https://image.slidesharecdn.com/irjet-v4i8397-170926091552/85/Implementation-of-Carry-Skip-Adder-using-PTL-3-320.jpg)
Implementation of Carry Skip Adder using PTL
- 1. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 2201 IMPLEMENTATION OF CARRY SKIP ADDER USING PTL Advit Arun Nayak1, Sridevi S2 1PG Student (Digital Electronics), Department of ECE, CMRIT, Karnataka, India 2Assistant Professor, Department of ECE, CMRIT, Karnataka, India ---------------------------------------------------------------------***--------------------------------------------------------------------- Abstract - In majority of electronics applications, performance of devices are taken into consideration. Adder is considered as one of the important operations in these devices. So the performances such as area, power and delay should be enhanced. This paper presents the design and implementation of Carry Skip Adder which uses pass transistor logic to enhance the performance parameters.. Here comparison is done between conventional CSKA and Proposed CSKA in-terms of power, delay, area and number of transistors used in the design. Schematic and implementation of complete project is done in Cadence Virtuoso 6.1.4 software at 90nm technology. Key Words: VLSI, CSKA, PTL, ALU, RCA, FA, HA 1. INTRODUCTION TO ADDERS The demand for electronics devices is increasing day by day which requires the use of power efficient VLSI circuits. Thus these circuit computation speed needs to be increased by enhancing the performance parameters such as area, power and delay. Number of transistors is the primary concern in the complex devices as it affects the area, power and delay. Adders are one of the essential blocks of most of the digital applications. In many of the arithmetic applications and other applications, adders are used in Arithmetic logic unit and most of the processors. Addition is utmost vital operations and it will result in sum bit and carry bit. There are two forms of adder, they are binary adder and multi-bit adder. Binary adders are full adder (FA) and half adder (HA). Multi-bit adder or complex adder architectures are constructed from the binary adders. Binary adder is the basic building block of any adder design. In this paper, CSKA implementation using pass transistor logic is done. Pass transistor logic has the advantage that it uses less gates compared to CMOS logic. 2. CONVENTIONAL CSKA Conventional carry skip adder is constructed by placing full adders in parallel to form a Ripple carry adder and for carry propagation it uses 2:1 mux and propagate block. In the conventional carry skip adder, carry is skipped to ith bit position without waiting for the rippling. This is done by using the skip logic, which is nothing but the 2:1 multiplexer. The working principle of CSKA is that it operates in 2 stage, they are generating sum bits from the Ripple Carry Adder block and the carry propagation block. Propagation block uses EXOR gates to generate the propagate bitts and the generated bits are fed to the AND gates. The result of propagation block is given to the selection line of multiplexer, which selects the carry. In order to construct a 16 bit conventional Carry skip adder, it requires a total of 920 transistors. This can be divided as 608 transistors for RCA, 232 transistors for propagate block and 80 transistors for 2:1 multiplexer. The conventional 16-bit Carry Skip Adder is shown as below, Fig -1: Conventional 16-bit CSKA 3. PASS TRANSISTOR LOGIC Pass transistor logic forms one of the essential logic families in integrated circuit design. Pass transistor acts as a switch to pass the signals from input to the output. Pass transistors are used in most of the application as it reduces the transistor count in the circuit design, also they are faster and consumes less power compared to the CMOS logic. There are two types of PTL they are PMOS type and NMOS type. PMOS type transmits strong 1’s and weak 0’s. NMOS type transmits strong 0’s and weak 1’s. In this paper, NMOS type is used for the design. The output voltage is given by VG-VTH. Pass transistor is shown as shown in figure below,
- 2. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 2202 Fig -2: General Pass Tansistor 4. PROPOSED CSKA The proposed carry skip adder architecture is constructed using pass transistors. Here only the full adder and multiplexer are constructed using PTL and propagate block is similar to that of the conventional CSKA. The proposed CSKA requires 472 transistors to construct and the working principal is exactly similar to the conventional CSKA, only difference is the internal structures, which can be shown in figures 3 and 4. Fig -3: Internal Structure of FA using PTL [9] Fig - 4: Internal structure of 2:1 MUX using PTL 5. SIMULATION AND COMPARISION Simulation of both proposed and conventional carry skip adder is carried out in Cadence Virtuoso 6.1.4 software in 90nm technology and the results are compared. Results and comparison is shown below, Fig -5: Schematic of proposed CSKA Fig -6: Test Bench of proposed CSKA Fig -7: Output showing from S0 to S5 of proposed CSKA
- 3. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 04 Issue: 08 | Aug -2017 www.irjet.net p-ISSN: 2395-0072 © 2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 2203 Fig -8: Output showing from S6 to S11 of proposed CSKA Fig -9: Output showing from S12 to S15 and Cout of proposed CSKA Table -1: Comparison of Conventional CSKA and Proposed CSKA Factors Conventional CSKA Proposed CSKA Number of Transistors 920 472 Area 782 µm2 272 µm2 Delay 136.8 ps 38.61 ps Average Power 494.1 mW 351.2 mW 6. CONCLUSION AND FUTURE SCOPE The proposed CSKA using pass transistor logic has achieved major enhancement compared to that of the conventional CSKA. From the Table 1 we can see that transistor count, area, delay and average power, are nearly halved compared to the conventional CSKA. Thus the proposed CSKA is a good competitor for low power and high speed electronic applications. In future, the proposed CSKA can be enhanced as there is voltage drop since PTL cannot output the same voltage level of the input voltage. REFERENCES [1] Jasmine Saini and Somya Agarwal, “Performance, Analysis and comparison of Digital Adders”, 2015. [2] Jigyasa and Kumar Saurabh, “Analysis of modified hybrid Full Adder with high speed”, 2013. [3] Jasbir Kaur and Lalit Sood, “Comparison between various types of adder topologies”, 2015. [4] Adoni Shiva Pradeep and S. Feroz Shah Ahmed, “A novel high speed carry skip adder with AOI and OAI logic using verilog HDL”, 2016. [5] Khushbu Nagori and Suman Nehra, “Design of a high speed and low power 4 Bit Carry Skip Adder”, March 2017. [6] Pooja Singh and Rajesh Mehra, “Design Analysis of XOR Gates Using CMOS & Pass Transistor Logic”, July 2014. [7] D. Markovic, B. Nikolic and V.G. Oklobdzija, “A general method in synthesis of pass-transistor circuits”, 2000. [8] Min Cha and Earl E. Swartzlander, “Modified Carry Skip Adder for reducing first block delay”, 2000. [9] J.Princy Joice, M.Anitha and Mrs.I.Rexlin Sheeba, “Design of carry save adder using transmission gate logic”, Jan 2015. [10] Pournima Pankaj Patil and Archana Arvind Hatkar “A Comparative analysis of 8-bit carry skip adder using CMOS and PTL techniques with conventional MOSFET at 32nm regime”, 2016.