Input output organisation
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The document discusses input-output organization between a CPU and peripherals. It notes that signal conversion and synchronization may be required due to differences in data rates and formats. Special interface hardware is used to supervise and synchronize input and output transfers. The document also discusses asynchronous and synchronous data transfer methods and the use of I/O buses versus memory buses for communication with peripherals.
Input output organisation
- 2. InterfaceA conversion of signal values may be required » CPU(Electronics) / HDD(Electromechanical and Electromagnet)A synchronization mechanism may be needed » The data transfer rate of peripherals is usually slower than the transfer rate of the CPUData codes and formats in peripherals differ from the word format in the CPU and Memory
- 3. The operating modes of peripherals are different from each other : 4 modes » Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPUSpecial hardware components between the CPU and peripherals
- 4. Supervise and Synchronize all input and output transfersI/O Bus and Interface Modules
- 5. I/O Bus versus Memory BusComputer buses can be used to communicate with memory and I/OUse two separate buses, one for memory and the other for I/O I/O Processor : separate memory bus and I/O bus2) Use one common bus for both memory and I/O but have separate control lines for each : Isolated I/O or I/O Mapped I/OIN, OUT : I/O Instruction
- 6. MOV or LD : Memory read/write Instruction3) Use one common bus for memory and I/O with common control lines : MemoryMapped I/OMOV or LD : I/O and Memory read/write Instruction4 I/O port : Data port A, Data port B, Control,Status8255 PIO ( port A, B, C, Control/Status )Address Decode : CS, RS1, RS0Example:
- 7. Example of I/o interface
- 8. Asynchronous Data TransferSynchronous Data TransferAll data transfers occur simultaneously during the occurrence of a clock pulse
- 9. Registers in the interface share a common clock with CPU registers Asynchronous Data TransferInternal timing in each unit (CPU and Interface) is independent
- 10. Each unit uses its own private clock for internal registersAsynchronous Data TransferSource-initiated strobeDestination-initiated strobeStrobe : Control signal to indicate the time at which data is being transmitted1) Source-initiated strobe 2) Destination-initiated strobe
- 11. Asynchronous Serial TransferSynchronous transmission :» The two unit share a common clock frequency» Bits are transmitted continuously at the rate dictated by the clock pulses Asynchronous transmission :» Special bits are inserted at both ends of the character code» Each character consists of three parts : 1) start bit : always “0”, indicate the beginning of a character 2) character bits : data 3) stop bit : always “1”
- 12. Asynchronous transmission rules : no parity» When a character is not being sent, the line is kept in the 1-state»The initiation of a character transmission is detected from the start bit, which isalways “0”»The character bits always follow the start bit» After the last bit of the character is transmitted, a stop bit is detected when the linereturns to the 1-state for at least one bit time (stop bits : 1, 1.5, 2)
- 13. Thank you. . . . .