Int 1010 Tcp Offload
- 1. TCP Offload Engine- SoftCore IP INT-1010 TCP Offload Engine Product brief, features and benefits summary Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx or Altera FPGAs INT-1010 is highly flexible that is customizable for layer-3, layer- 4, layer-5 network infrastructure and network security systems applications. It is recommended for use in, among others, high performance Servers, NICs, SAN/NAS and data center applications. It provides the key IP building block for a single high performance Giga bit Ethernet ASIC/ASSP/FPGA. INT-1010 provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others INT-1010 can process TCP/IP, for in-line network security appliances, sessions in both directions, simultaneously, at full G-bit rate. This relieves the host CPU from costly TCP/IP buffer stack execution and maintenance tasks. INT-1010 can process TCP/IP sessions and has the capability to process other relevant protocols such as FTP, UDP, ICMP, TFTP etc on all inbound as well as outbound traffic simultaneously without compromising performance at sustained Gigabit speeds. • Ideal for high performance • Scalable MAC Rx FIFOs and Tx and mid performance FIFOs make it ideal for specialized, differentiable optimizing system performance. ASICs or FPGAs for Network security or Network • Hardware implementation of infrastructure applications TCP/IP stacks’ control plane and data plane. • Less than 4000 Xilinx slices, Altera ALMs or 150,000 • Hardware implementation of ASIC gates + on-chip memory ARP protocol. • Fully integrated 100 M ARP table creation, deletion bit/1-G bit high performance management (optional) EMAC. Intelop Corporation www.intelop.com 4800 Great America Pkwy. Ste-231 Santa Clara, CA. 95054. Ph: 408-496-0333, Fax: 408-496-0444
- 2. TCP Offload Engine- SoftCore IP • Customizable for IP-protocol live TCP sessions. only. Customizable, depending upon on-chip memory availability. • On-chip DDR or SSRAM memory controller which can address • Extendable to 256K TCP from 4K Bytes to 4 MB Bytes on sessions. Internal Memory chip or 256 MB off chip dependent. memories (User customizable, optional) • Wire-speed 2Gbps performance at full duplex • Many trade-offs for some functions performed in • Can process up to 256K hardware or software connections per second • Configurable Packet buffers, • TCP + IP check sum session table buffers On-chip generation and check performed or Off-chip memories, attached in hardware in less than 6 DDR I/II interface. Depending clks (30 ns at 200 MHz) vs 1-2 on system, performance, us by typical software TCP- ASIC/FPGA size requirements-> stack User Customizable, (optional) • Connection set up and tear • Interfaces directly to GMII, down/termination RGMII, MII external 10/100/ 1000 Mbit Phy interfaces • User programmable Session table parameters • Architecture can be scaled up to 10-G bits • Dedicated set of hardware Timers for each TCP/IP session • Customizable to handle jumbo or customizable for sharing frames stale sessions. • Generic bus interface for • Multiple ‘slot storage’ for Local Processor control. ARM, fragmented packets. More slots PPC, MIPS and other CPU allocated when more On-chip interfaces available Memory available. Self- checking available memory • User programmable/ logic. (optional) prioritize-able interrupts • Out of sequence packet • Performs connection/session detection/storage and management Reassembly/Segmentation (optional) • Monitors, Stores, Maintains and processes more than 4024 • RDMA- Direct Data placement in Applications buffer at full Intelop Corporation www.intelop.com 4800 Great America Pkwy. Ste-231 Santa Clara, CA. 95054. Ph: 408-496-0333, Fax: 408-496-0444
- 3. TCP Offload Engine- SoftCore IP wire speed without CPU-> • Accommodates future reduces CPU’s buffer copy time Specifications changes. and utilization by 95% • Basic mini API available for • Future Proof- Flexible PPC architecture. Others implementation of TCP Offload OSs/CPUs also available. Simplified Block Diagram Intelop Corporation www.intelop.com 4800 Great America Pkwy. Ste-231 Santa Clara, CA. 95054. Ph: 408-496-0333, Fax: 408-496-0444
- 4. TCP Offload Engine- SoftCore IP Specifications brief: • Functionality Proven in multiple IDS/IPS appliances • Complete header and flag processing of TCP/IP sessions in hardware accelerates by 10 x – 50 x • TCP Offload Engine- 2G b/s Wire-speed performance • Scalable to 10 G b/s • TCP + IP check sum- hardware • TCP segmentation/reassembly in hardware • Multiple ‘slot storage’ for fragmented packets • Out of sequence packet detection/storage/Reassembly • Accelerate security processing, Storage Networking- TCP • RDMA- Data placement in Applications buffer -> reduces CPU utilization by 90 % • Future Proof- Flexible implementation of TCP Offload • Accommodates future Specifications changes. • TOE MS-chimney architecture compatible • Customizable. Source code; Verilog • Detailed specs available under NDA Intelop Corporation www.intelop.com 4800 Great America Pkwy. Ste-231 Santa Clara, CA. 95054. Ph: 408-496-0333, Fax: 408-496-0444
- 5. TCP Offload Engine- SoftCore IP Xilinx Altera iTOE - FPGA Altera Stratix III, IV, V Stratix - 2 /ALMs ~2256 ~3256 ~1256 16- 256 Alter-vqm, Verilog Verilog /Altera Quartus 8.1 Quartus 8.1 Intelop Corporation www.intelop.com 4800 Great America Pkwy. Ste-231 Santa Clara, CA. 95054. Ph: 408-496-0333, Fax: 408-496-0444