Introduction to CMOS VLSI Design for Low Power

Introduction to
CMOS VLSI
Design
Design for Low Power

CMOS VLSI Design
Design for Low Power Slide 2
Outline
 Power and Energy
 Dynamic Power
 Static Power
 Low Power Design

CMOS VLSI Design
Power and Energy
 Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.
 Instantaneous Power:
 Energy:
 Average Power:
( ) ( )
DD DD
P t i t V

0 0
( ) ( )
T T
DD DD
E P t dt i t V dt
 
 
avg
0
1
( )
T
DD DD
E
P i t V dt
T T
  

CMOS VLSI Design
Dynamic Power
 Dynamic power is required to charge and discharge
load capacitances when transistors switch.
 One cycle involves a rising and falling output.
 On rising output, charge Q = CVDD is required
 On falling output, charge is dumped to GND
 This repeats Tfsw times
over an interval of T
C
fsw
iDD
(t)
VDD

CMOS VLSI Design
Dynamic Power Cont.
C
fsw
iDD
(t)
VDD
dynamic
P 

CMOS VLSI Design
Dynamic Power Cont.
C
fsw
iDD
(t)
VDD
 
dynamic
0
0
sw
2
sw
1
( )
( )
T
DD DD
T
DD
DD
DD
DD
DD
P i t V dt
T
V
i t dt
T
V
Tf CV
T
CV f







CMOS VLSI Design
Activity Factor
 Suppose the system clock frequency = f
 Let fsw = af, where a = activity factor
– If the signal is a clock, a = 1
– If the signal switches once per cycle, a = ½
– Dynamic gates:
• Switch either 0 or 2 times per cycle, a = ½
– Static gates:
• Depends on design, but typically a = 0.1
 Dynamic power:
2
dynamic DD
P CV f
a


CMOS VLSI Design
Short Circuit Current
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are
comparable for input and output

CMOS VLSI Design
Example
 200 Mtransistor chip
– 20M logic transistors
• Average width: 12 l
– 180M memory transistors
• Average width: 4 l
– 1.2 V 100 nm process
– Cg = 2 fF/mm

CMOS VLSI Design
Dynamic Example
 Static CMOS logic gates: activity factor = 0.1
 Memory arrays: activity factor = 0.05 (many banks!)
 Estimate dynamic power consumption per MHz.
Neglect wire capacitance and short-circuit current.

CMOS VLSI Design
Dynamic Example
 Static CMOS logic gates: activity factor = 0.1
 Memory arrays: activity factor = 0.05 (many banks!)
 Estimate dynamic power consumption per MHz.
Neglect wire capacitance.
    
    
 
6
logic
6
mem
2
dynamic logic mem
20 10 12 0.05 / 2 / 24
180 10 4 0.05 / 2 / 72
0.1 0.05 1.2 8.6 mW/MHz
C m fF m nF
C m fF m nF
P C C f
l m l m
l m l m
  
  
 
  
 

CMOS VLSI Design
Static Power
 Static power is consumed even when chip is
quiescent.
– Ratioed circuits burn power in fight between ON
transistors
– Leakage draws power from nominally OFF
devices
0 1
gs t ds
T T
V V V
nv v
ds ds
I I e e
 
 
 
 
 
 
 
0
t t ds s sb s
V V V V
   
    

CMOS VLSI Design
Ratio Example
 The chip contains a 32 word x 48 bit ROM
– Uses pseudo-nMOS decoder and bitline pullups
– On average, one wordline and 24 bitlines are high
 Find static power drawn by the ROM
– b = 75 mA/V2
– Vtp = -0.4V

CMOS VLSI Design
Ratio Example
 The chip contains a 32 word x 48 bit ROM
– Uses pseudo-nMOS decoder and bitline pullups
– On average, one wordline and 24 bitlines are high
 Find static power drawn by the ROM
– b = 75 mA/V2
– Vtp = -0.4V
 Solution:  
2
pull-up
pull-up pull-up
static pull-up
24μA
2
29μW
(31 24) 1.6 mW
DD tp
DD
V V
I
P V I
P P
b

 
 
  

CMOS VLSI Design
Leakage Example
 The process has two threshold voltages and two
oxide thicknesses.
 Subthreshold leakage:
– 20 nA/mm for low Vt
– 0.02 nA/mm for high Vt
 Gate leakage:
– 3 nA/mm for thin oxide
– 0.002 nA/mm for thick oxide
 Memories use low-leakage transistors everywhere
 Gates use low-leakage transistors on 80% of logic

CMOS VLSI Design
Leakage Example Cont.
 Estimate static power:

CMOS VLSI Design
– High leakage:
– Low leakage:
    
6 6
20 10 0.2 12 0.05 / 2.4 10
m m
l m l m
  
    
   
6
6 6
20 10 0.8 12 0.05 /
180 10 4 0.05 / 45.6 10
m
m m
l m l
l m l m
 
  
     
     
6
6
2.4 10 20 / / 2 3 /
45.6 10 0.02 / / 2 0.002 /
32
38
static
static static DD
I m nA m nA m
m nA m nA m
mA
P I V mW
m m m
m m m
   
 
 
 
 
 

 

CMOS VLSI Design
– High leakage:
– Low leakage:
 If no low leakage devices, Pstatic = 749 mW (!)
    
6 6
20 10 0.2 12 0.05 / 2.4 10
m m
l m l m
  
    
   
6
6 6
20 10 0.8 12 0.05 /
180 10 4 0.05 / 45.6 10
m
m m
l m l
l m l m
 
  
     
     
6
6
2.4 10 20 / / 2 3 /
45.6 10 0.02 / / 2 0.002 /
32
38
static
static static DD
I m nA m nA m
m nA m nA m
mA
P I V mW
m m m
m m m
   
 
 
 
 
 

 

CMOS VLSI Design
Low Power Design
 Reduce dynamic power
– a:
– C:
– VDD:
– f:
 Reduce static power

CMOS VLSI Design
Low Power Design
– a: clock gating, sleep mode
– C:
– VDD:
– f:

CMOS VLSI Design
Low Power Design
– C: small transistors (esp. on clock), short wires
– VDD:
– f:

CMOS VLSI Design
Low Power Design
– VDD: lowest suitable voltage
– f:

CMOS VLSI Design
Low Power Design
– f: lowest suitable frequency

CMOS VLSI Design
Low Power Design
– f: lowest suitable frequency
– Selectively use ratioed circuits
– Selectively use low Vt devices
– Leakage reduction:
stacked devices, body bias, low temperature

Introduction to CMOS VLSI Design for Low Power

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