Ju2416921695

Mr. M.Venkatavinod, Mr. K.Sreenivasarao / International Journal of Engineering Research
and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 3, May-Jun 2012, pp.1692-1695

FPGA Implementation of low power multiserial to Ethernet
gateway for Unmanned Aerial Vehicle (UAV) data acquisition
systems
Mr. M.Venkatavinod Mr. K.Sreenivasarao, M.Tech
M.Tech., VLSI Systems Design, Associate Professor, Dept of ECE,
AITS, Rajampet, Kadapa(DT). AITS, Rajampet, Kadapa(DT).

Abstract-
The Unmanned Aerial Vehicle (UAV) from Ethernet, it first unpacks the frame and
data link is a combination of ground control determines the port number to transfer data to its
station and airborne data terminal. The buffer and adds the synchronous heads.
computers on the ground need control and In this project we use Hardwired TCP/IP
check more than ten assemblies, containing Embedded Ethernet Controller chip will be
main and sub remote control transmitters, interfaced to FPGA[2] [3] to provide Ethernet
telemetry receivers, image decompression interface. Various digital signals will be captured
board, ground positioning receiver and radio by FPGA and will be sent on a serial line. The
location tracking servo system etc. The FPGA implements all the necessary logic to read
communication between them is asynchronous the data from these sensors and store the data in it.
serial form and at present, the serial ports are On FPGA logic also will be implemented to read
expanded by typical serial control card, which data from multiple number of serial ports. The
are used for interfacing with different types of Ethernet module takes data from serial port and
sensors and separate microprocessor sends to PC in Ethernet form. In PC application
/microcontroller is used for Ethernet will be developed to read data from Ethernet and
connectivity which increases cost,space and store it on PC harddisk. .
power consumption .
To resolve these problems, a method of II. Multiserial to Ethernet gateway
multi-serials to Ethernet Gateway based on the A.LM35 (Precision Centigrade Temperature
field programmable gate array (FPGA) Sensors) The LM35 is an integrated circuit
+network interface chip is implemented in this temperature sensor that can be used to measure
project. The Ethernet Gateway will send data as temperature with an electrical output proportional
Ethernet frame format after receiving serial to the temperature (in oC).The LM35 operates over
data, indirectly achieves multi-serials a range of −55° to +150°C temperature range.
communication, simplifies cabinet wiring and LM35 draws only 60 micro amps from its supply
improves CPU’s efficiency. and possesses a low self-heating capability and
generates a higher output voltage .The block
Keywords- Ethernet, FPGA, Gateway, diagram of data acquisition system with Ethernet
UAV,UART, Multiserial module is shown below.
I . Introduction
The data is acquired from multiple serial
digital modules and are transmitted to the Ethernet
module, and is received by ground station, by the
TCP/IP protocol. The Gateway[1] consists of
FPGA and Ethernet module .Using a flexible
FPGA programming feature, a UART [1] can be
designed in it. If several UARTs are in it, the
system has the capacity of communication with
multiple serial ports. The Ethernet module provides
Ethernet communication and is configured at the
time of initialization. The Gateway‟s function is
to achieve communication between the serial
devices and Ethernet.
When Gateway receives data from
devices, it will choose useful data from serial data
frame following the communication protocol, and Fig1. Data acquisition system with Ethernet
send data after packaged. When it receives data gateway block diagram

1692 | P a g e

B.Analog to digital converter conversion between serial and parallel forms. Serial
An analog-to-digital converter (abbreviated ADC, transmission of digital information (bits) is cost
A/D or A to D) is a device that converts a effective than parallel transmission .
continuous quantity to a discrete time digital
representation. UART BLOCK
The UART is a serial interface with a
The ADC internal diagram is shown below.It frame format of start bit of active low „0‟at
consists of 4 bit up counter and 12 bit left shift beginning of frame and 8 bit of information with a
register. stop bit of active high„1‟ signal at the end. The
operation of UART is controlled by Clock signal
which is fed from external crystal. The UART
serial data format is shown in fig. 3.

Fig 3. UART serial data format

UART Receiver
The uart receiver diagram is shown below
in fig .4 Itconsists of baud generator and receiver
Fig2. ADC internal diagram section module .The receiver section module in
turn consists of a receiver.
Above module is a single ADC interface
block. When reset is given for 4 bit up counter and
12 bit left shift register, it will clear the data and
make initially zero‟s in all bits. When Reset is
active low then counter will start counting, this
count is given to a comparator (it will be active
high when count is more than reference i.e x‟3‟).
The comparator output is referred as enable signal
and is given to the shift register .when enable is
active high it will shift the register values from
right to left by one bit. The count bits are given to
Fig 4. UART receiver diagram
an And gate and that will be active high, when the
counter having maximum count and that will be As shown in above figure Receiver section
taken as output to CS(chip select) signal. This is a combination of a baud generator and receiver
signal is given to shift counter as clk, when clk is section module, each module has been explained
present, shift register will give parallel output data below in detail.
as pdata.
Baud Generator
C. ADC Interface Module Baud generation section is a clock divider
The interface module is ADCS7476A is a circuit, FPGA board clock runs at 50MHz, but
high speed, low power, 12-bit serial A/D converter UART transfers data at predefined standards that
that interfaces easily to FPGAs. The A/D interface had to be maintained, in present system it is
adapter (AD1_PMOD) is implemented within the designed for a rate of 9600 bits/sec(i.e 50x10 6 is
FPGA. scaled down for 9600). It generates 9600 pluses per
sec; this implies the speed of UART is 9600 bits
D.UART Module per sec. Another clock is with a 16 times faster than
A universal asynchronous receiver/transmitter, required, and it is given to the receiver section, so
abbreviated UART is a microchip with that the data will not be corrupted.
programming features that translates data between Receiver Section UART receiver handles reception
parallel and serial forms. of data from RS232 port. Main functions of
The Universal Asynchronous Receiver/Transmitter receiver block are to convert the serial data to
(UART) takes bytes of data and transmits the parallel data, and check the correctness of data
individual bits in a sequential manner. At the from parity and store the received data. UART
destination, an another UART re-assembles the bits receiver state machine is shown in Figure . The
into complete bytes. Each UART contains a shift receiver is in IDLE state by default. When the
register which is the fundamental method of serial data pin goes low, indicating the start bit, the

1693 | P a g e

state machine enters DATA0 state. The data is
received, one bit at a time from LSB to MSB in
states DATA0 to DATA7.

Fig 6. Data collection module internal diagram

In_Data is stored in the ROM (i.e it
Fig 5. UART receiver state machine contains 2048 memory locations) memory
according to address given by the wr_address that
UART receiver state machine is shown in is generated by input address counter, when rd_wr
Figure 5. If parity is enabled, the state machine signal is at logic high value with raising edge of the
checks the parity bit received against the parity clk.
obtained from received data. If the data received is
fine, the data_rx (data_rx_done) bit is set to „1‟ Data is forced on to output line data
and the receiver goes back to IDLE state again. according to rd_address that is generated by output
address counter ,whenever rd_wr signal is at logic
E. Transmitter high with falling edge of the clk. When reset is at
In this project Transmission operation is active high then the module will clear the data .If it
simpler since it is under the control of the is in active low ,then module will be working in
transmitting system. As soon as data is normal operation.
accumulated in the shift register after completion of
the previous character, the UART hardware G. Serial to Ethernet module:
generates a start bit, shifts the required number of The serial to Ethernet module [1] is shown in
data bits, generates and add the parity bit (if used), below fig.7 The Serial to Ethernet converters
and the stop bits. Since transmission of a single transmit RS232, RS422 or RS485 data across an IP
character may take a long time , the UART will network.
maintain a flag showing busy status so that the host
system does not allow a new character for
transmission until the previous one has been
completed; this may also be done with an interrupt.
Transmitting and receiving UARTs must be
synchronized for the same bit speed, character
length, parity, and stop bits for proper operation.

F.Data collection module
Adc_in, UART „s input1,input2 and
input3 are the inputs for this block .These input‟s
are selected with select lines that are generated
from input address counter .Rd_address, Fig 7.serial to Ethernet module
wr_address, data, clk and rd_wr are inputs to
connection memory module and data(q) is the Features:
output. The diagram for data collection module is The S2E module is a simple add-on
shown in below fig. product to existing systems to provide network
connectivity. It consists of all the necessary
hardware to quickly evaluate the module
capabilities. The S2E module possess the
following features:

1694 | P a g e

1. LM3S6432 Stellaris microcontroller with
96 kB of Flash memory and 32 kB of
SRAM.
2. 10/100 Mbit Ethernet port.
3. Two serial ports
I.PORT0 is an asynchronous serial port with
RS232 levels
 Data rates up to 230,400 bits/sec.
 Includes RTS/CTS for flow control.
II .PORT1 has 4 CMOS/TTL level signals that can
be configured several ways
 Data rates up to 1 Mbit/sec. Fig 9chipscope results
 As an asynchronous serial port with The power analysis can be done by using xpower
RTS/CTS flow control or with 2 analyzer.In this project the total power obtained is
GPIOs. 87.66 milliwatts(mw).
 As 4 GPIOs.
 As a synchronous serial port (master or
slave) with support for SPI and other
synchronous protocols.
4. RDK is USB-powered, no additional
power supply required.
5. Ethernet boot loader for firmware
upgrades.
6. JTAG 10-pin debug header.

III. Simulation Results
Fig inputs are adc(sdata1),rd1,rd2,rd3.These inputs
are selected based on selection signal. The data_in
is the output signal .According to selection signal,
the input is received by the UART and it
transmitted to the Ethernet module which acts as a
transmitter section and which can be seen outputs Fig 10. Xpower analyzer
on the pc.In this project the selection signal is 00.
V. Conclusion
The results of test denote that using this
method, we can simplify the communication
between pc and port devices and it improves the
efficiency of CPU and ensure the processing of
system in real time .FPGA programming features
provide lot of scope for adding additional
functionality for further upgrade of system.This
design could be used in the domain of industrial
automation and data acquisition systems.

References
[1] FPGA-based for Implementation of Multi-
Serials to Ethernet Gateway Tong by
Fig 8 simulation results for selection signal 00 YAO, Yonghong HU, Lu DING IEEE
2010
IV. CHIPSCOPE PRO RESULTS [2] Ding Wang, Jiadong Xu, Rugui Yao,
The chipscope result is shown below. The Ruifeng Miao, “Simulation system of
Temp_data is a data received from the temperature telemetering and telecontrol for unmanned
sensor module, and Data_LED1, Data_LED2, aerial vehicle,” IEEE, 2006,
Data_LED3 represents the received input data from [3] Shouqian Yu, Lili Yi, Weihai Chen,
their respective UART modules. According to the Zhaojin Wen, “Implementation of a Multi-
selection line input, the respective UART module channel UART Controller Based on FIFO
data is displayed on the output_data. Technique and FPGA,” 2007

1695 | P a g e

Ju2416921695

More Related Content

What's hot (16)

Viewers also liked (20)

Similar to Ju2416921695 (20)

Ju2416921695