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LIC-Unit-IV-PLL.pptx
- 1. UNIT IV - SPECIAL ICs Functional block, characteristics & application circuits with 565-phase lock loop IC
- 2. Phase Locked Loops • Is an important building block of linear system • Application • This technique for electronic frequency control is used today in – Satellite communication system – Air borne navigational system – FM communication systems – Computers, etc.,
- 3. Phase Locked Loops - Basic Principle
- 4. Phase Locked Loops - Basic Principle • PLL system consists – Phase detector / Comparator – A Low Pass Filter – An error Amplifier – A Voltage Controlled Oscillator(VCO) • VCO is a • free running multivibrator and • operates at a set frequency f0 called free running frequency, depends of capacitance and resistance (externally) • It can also be shifted to either side by applying a dc control voltage VC • Frequency deviation depends on VC (dc), hence it is called “Voltage Controlled Oscillator”.
- 5. Phase Locked Loops - Operation • If the input signal VS , fS is applied to PLL. 1) Phase detector (Basically multiplier) compares phase, frequency of VS & V0 2) Ve – error voltage is generated 3) Phase detector produces sum (fS + f0), difference (fS - f0) 4) (fS + f0) is removed by LPF & (fS - f0) is amplified and applied as VC to VCO
- 6. Phase Locked Loops - Operation 5) VC shifts the VCO frequency in tern to reduce the difference (ie., fS - f0), When this process starts the signal is in “Capture Range” 6) The VCO change frequency continues till fS = f0, then this is called “Locked”, Now fS = f0 but phase difference φ exists 7) Phase difference generates, VC to shift VCO frequency to maintain Lock 8) If Locked PLL tracks the input signal.
- 7. Phase Locked Loops - Basic Principle • Three stages of PLL are, – Free running – Capture. – Locked (or) Tracking Important Definitions •Lock-In Range •The range of frequencies over which the PLL can maintain lock with input is called lock-in range (or) tracking range. •Expressed as percentage of f0. •Capture Range •The range of frequencies over which the PLL can acquire lock with input is called capture range. •Also expressed as percentage of f0. •Pull-in time •Total time taken by the PLL to establish lock is called pull-in time.
- 8. Phase Locked Loops – Analog Phase Detector • Phase Detector / Comparator – Most important part of PLL – Types are analog and digital • Analog Phase Detector • The principle of analog phase detection using switch type phase detector is shown in figure • Electronic switch S is opened and closed by VCO input (square wave) • The input signal chopped at a repetition rate (determined by VCO frequency)
- 9. • Figure c). Shows the input VS is in phase with V0 , ϕ=00. • Switch S closed when V0 is +ve, so output Ve will be half sinusoidal • For ϕ=900, ϕ=1800 shown in figure (c), (d) • This type is called half wave detector Phase Locked Loops – Analog Phase Detector
- 10. • The output of LPF gives error signal, which is average value of output as shown in dotted line • From output waveform for perfect lock the VCO output should be 900 out of phase with respect to the input signal. • Closed loop analysis • Phase comparator is basically a multiplier, so, output – K is the gain of the phase comparator (or) attenuation constant – φ is the phase shift between input (VS) and VCO output (V0) Phase Locked Loops – Analog Phase Detector
- 11. • At lock fs = f0 • It contains two terms – Double frequency term – DC term – Both are function of φ • Double frequency term is eliminated by LPF Phase Locked Loops – Analog Phase Detector
- 12. • DC signal is input to VCO, in perfect locked state • fS = f0, phase shift 900 (i.e., cos900 = 0), to get error signal ve = 0 • Problem with switch type are – ve is proportional to amplitude of supply voltage – ve is proportional to cosφ (non linear) • Both can be eliminated by limiting the amplitude of input • (converting constant amplitude square wave) Phase Locked Loops – Analog Phase Detector
- 13. • Figure shows a digital type XOR phase detector • The output of XOR gate is high when only one of the input signals fS (or) f0 is high. • This type can be used when both input are square waves • At fS = f0 is shown in figure(b), fs is leading f0 by φ • DC output with φ is shown in figure(c) • The slope of curve gives the conversion ratio Kφ of the phase detector. – Kφ for VCC = 5V is Kφ = 5/π = 1.59 V/rad Phase Locked Loops – Digital Phase Detector
- 14. • Another digital phase detector is an edge triggered phase detector • Circuit is an R-S Flip-Flop mode. • This circuit is useful when both input f0, fS should be square waveform and duty cycle <50% • this type of detector has better capture tracking and locking characteristics as output voltage is linear up to 3600 Phase Locked Loops – Digital Phase Detector
- 15. • Common type VCO in IC form is NE/SE566. • Timing capacitor CT is linearly charged (or) discharged by constant current source / link • The current can be controlled by VC applied at pin 5 (or) changing the timing resistor RT • The voltage at pin6 is held at same voltage as pin 5 to reduce the charging current. PLL – Voltage Controlled Oscillator (VCO)
- 16. • The voltage across CT is applied to the inverter input terminal – Schmitt trigger A2 via buffer amplifier A1 – Output of Schmitt trigger varies from VCC and 0.5 VCC • If Ra = Rb voltage at input A2 varies from 0.5 VCC to 0.25 VCC PLL – Voltage Controlled Oscillator (VCO)
- 17. • When voltage on CT > 0.5VCC (during charging) the output of A2 goes low (0.5 VCC) • The capacitor now discharges and when at 0.25 VCC, output of A2 goes HIGH (VCC) – Since the source and sink currents are equal, – Capacitor charges and discharges for the same amount of time • Triangular wave form across CT, available at pin 4 PLL – Voltage Controlled Oscillator (VCO)
- 18. • Output of A2 is inverted by A3 is available in pin3 • The f0 can be calculated as voltage on C changes from 0.25VCC to 0.5VCC ΔV = 0.25 VCC • C charges with constant current source • For triangular waveform T = 2Δt PLL – Voltage Controlled Oscillator (VCO)
- 19. • But • VC , control voltage at pin 5 • Output frequency of VCO (f0) can be changed by (1). RT, (2). CT, (3). VC at modulating input pin 5 • VC can be varied by R1, R2 as shown in figure. • RT, CT first selected, so that f0 lies in centre of operating frequency range, then VC is varies. PLL – Voltage Controlled Oscillator (VCO)
- 20. Voltage to Frequency Conversion Factor (KV) • Important parameter of VCO – Where, ΔVC is the modulation voltage required to produce frequency shift Δf0 • Assume original frequency = f0, New frequency = f1, Δf0 = f1 – f0
- 21. • LPF not only removes the high frequency components and noise, but also controls the dynamic characteristics of the PLL. • Dynamic characteristics – Capture and lock range – Band-width – Transient response • If BW reduced, – response time increased. – but also reduces the capture range. PLL – Low Pass Filter(LPF)
- 22. • The charge on filter C gives a short time memory to PLL • If signal < noise for few cycles. – Vdc on C shift the frequency of VCO up to pick up • This produces high noise immunity and locking stability. PLL – Low Pass Filter(LPF)
- 23. • PLL are available as independent IC packages and are externally interconnected to make PLL , IC PLL 565 is the most commonly used PLL Is available in 14pin DIP package and 10pin metal can package • The output frequency f0 of VCO (both inputs 2,3 are grounded) is – Where, RT, CT are external resistance and capacitance connected to pin 8, 9 – RT – recommended value is between 2KΩ to 20KΩ. Monolithic Phase Locked Loop - IC PLL 565
- 24. • The VCO free running frequency is adjusted with RT, CT. • A short circuit between pin4 and 5 connects VCO output to the phase comparator. • A capacitor connected between pin7 & 10 to make LPF with Rinternal (3.6KΩ) Monolithic Phase Locked Loop - IC PLL 565
- 25. • The output from a PLL system can be obtained as either voltage signal VC(t) (ve at FB), or frequency signal (VCO output) • Voltage output used in frequency discriminator applications • Frequency output in – Signal conditioning – Frequency synthesis – Clock recovery applications. PLLApplications
- 26. • A divide by ‘N’ network is inserted between VCO output and phase comparator input. • In locked state f0=Nfs • Multiplication factor can be obtained by selecting a proper scaling factor ‘N’ of the counter PLLApplications - Frequency Multiplication / Division
- 27. – VCO can directly locked to the n-th harmonic of the input signal. – But n should be <10 • The same circuit can be used for frequency division, since the VCO output is rich in harmonics, it is possible to lock the mth harmonic of VCO output with fs, f0 = fs / m. PLLApplications - Frequency Multiplication / Division • Frequency multiplication can also be obtained by PLL in harmonic locking mode. • If input is rich in harmonics example, square wave , pulse train etc.,
- 28. • A multiplier / mixer & LPF are connected externally to the PLL • Input fs (has to be shifted) & f0 are applied as input to mixer, • Output contains sum and difference of fs & f0 – but output of LPF contains only (f0-fs). PLLApplications - Frequency Translation
- 29. • The translation (or) offset frequency f1 (f1 <<fs) is applied to the phase comparator. • When PLL is in locked state f0 – fs = f1 → f0 = fs + f1 • We can shift an incoming frequency fs by f1 PLLApplications - Frequency Translation
- 30. • PLL is locked to the carrier frequency of the incoming AM signal. • The VCO output has – Same frequency as carrier – Unmodulated (fed to multiplier) – Always 900 out of phase • AM input signal also 900 phase shift before multiplier, So in multiplier both are in same phase PLLApplications - AM Detection
- 31. • Output of multiplier contains both the sum and the difference signals • High frequency components are filtered by LPF • Since PLL responds only to carrier frequency which are very close to VCO output, PLLAM detector exhibits a high degree of selectivity and noise immunity PLLApplications - AM Detection
- 32. • If PLL is locked to a FM signal – the VCO tracks the instantaneous frequency of the input signal • The filtered error voltage – which controls the VCO and – maintains lock with input signal is the demodulated output. PLLApplications - FM Demodulation
- 33. • In digital data communication etc,. binary data is transmitted by means of carrier frequency, this is shifted between two preset frequency.This type of data transmission is called FSK technique. • The binary data can be retrieved using a FSK demodulator at receiving end. PLLApplications - Frequency Shift Keying (FSK) Demodulator
- 34. • The figure shows FSK demodulator using PLL for tele typewriter signals of 1070Hz and 1270Hz • When signal appears at input loop – Locks to the input frequency – Tracks it between the two frequency • A three stage filter removes the carrier component and output signal is made logic compatible by a voltage comparator. PLLApplications - Frequency Shift Keying (FSK) Demodulator