Low power & area efficient carry select adder
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This document proposes a modified carry select adder design to reduce area and power consumption compared to a regular carry select adder. A carry select adder uses two ripple carry adders and a multiplexer to perform addition. The proposed design replaces one of the ripple carry adders with a binary-excess-1 converter to reduce the number of full adders. Simulation results show the modified design reduces area by reducing the gate count and also lowers power consumption compared to a regular carry select adder design. The modified design has applications in arithmetic logic units, high-speed multiplications, and advanced microprocessor designs due to its lower area and power.
![REFERENCES
[1] B. Ramkumar, Harish M Kittur “Low power and Area efficient carry select adder,”IEEE
Trans,Vol.20,Feb 2012.
[2] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron.
Lett., vol. 34, no. 22, pp. 2101–2103, Oct. 1998.
[3] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,” Electron. Lett., vol.
37, no. 10, pp. 614–615, May 2001.
[4] J. M. Rabaey, Digtal Integrated Circuits—A Design Perspective.Upper Saddle River, NJ:
Prentice-Hall, 2001.
[5] Samir Palnitkar, “Verilog Hdl: A Guide to Digital Design and Synthesis”2005,2nd
Edition.](https://image.slidesharecdn.com/low-powerareaefficientcarryselectadder-140326094912-phpapp02/85/Low-power-area-efficient-carry-select-adder-21-320.jpg)
Low power & area efficient carry select adder
- 1. Low-Power and Area-Efficient Carry Select Adder Presented by P. SAI VARA PRASAD M.Tech ,ECE DSCE, Under the guidance of Dr.M.Suryanarayana Professor & HOD, Dept. of ECE
- 2. CONTENTS ABSTRACT INTRODUCTION EXISTING SYSTEM PROBLEMS IN EXISTING SYSTEM PROPOSED SYSTEM SOLUTION OF THE PROBLEM SIMULATION RESULTS OF REGULAR CSLA ADVANTAGES & APPLICATIONS CONCLUSION
- 3. ABSTRACT Carry Select Adder (CSLA) is one of the fastest adders used in many data- processing processors to perform fast arithmetic functions. By gate level modification of CSLA architecture we can reduce area and power. Based on this modification 16-b square-root CSLA (SQRT CSLA) architecture have been developed. The proposed design has reduced area and power as compared with the regular SQRT CSLA . This work evaluates the performance of the proposed designs in terms of area, power by hand with logical effort and through Xilinx ISE 14.2(Verilog HDL) and this will be implemented in FPGA (Sparton 6).
- 4. INTRODUCTION In electronics, an adder or summer is a digital circuit that performs addition of numbers. Adders can be constructed for many numerical representations, such as BCD or Excess-3, the most common adders operate on binary numbers. Adders plays Major role in Multiplications and other advanced processers designs
- 5. EXISTING SYSTEM The carry-select adder generally consists of two Ripple Carry Adders (RCA) and a Multiplexer . Adding two n-bit numbers with a carry-select adder is done with two adders (therefore two RCA). In order to perform the calculation twice, one time with the assumption of the carry being zero and the other assuming one.
- 6. REGULAR 16BIT SQRT CSLA
- 7. AREA EVALUATION METHODOLOGY OF REGULAR 16-b SQRT CSLA Gate count= 57(HA+FA+MUX) FA=39(3*13) HA=6(1*6) MUX=12(3*4)
- 8. PROBLEMS IN EXISTING SYSTEM The problem in CSLA design is the number of full adders are increased then the circuit complexity also increases. The number of full adder cells are more thereby power consumption of the design also increases Number of full adder cells doubles the area of the design also increased.
- 9. SOLUTION OF THE PROBLEM The parallel RCA with Cin=1 is replaced with Binary-Excess 1 converter( BEC). four-bit BEC
- 10. Modified CLSA Basic function of CLSA is obtained by using the 4-bit BEC together with the mux.
- 12. In this system we use the BEC to reduce the RCA circuits Here based on the carry input the MUX will be select corresponding input In this design we give the MUX inputs are RCA output and BEC output Compare to regular design the area of the design is less Contd…
- 13. AREA EVALUATION METHODOLOGY OF MODIFIED 16-b SQRT CSLA GATE COUNT= 43(HA+FA+MUX+BEC) (13+6+12+1+1+10)
- 14. COMPARISION GROUP REGULAR MODIFIED GROUP 2 57 43 GROUP 3 84 61 GROUP 4 117 84 GROUP 5 147 107
- 15. RTL SCHEMATIC
- 17. TOOL USED Programming language: VERILOG HDL Tool : Xilinx ISE (10.2)
- 18. ADVANTAGES Low power consumption Less area (less complexity) More speed compare regular CSLA
- 19. APPLICATIONS Arithmetic logic units High Speed multiplications Advanced microprocessor design Digital signal process
- 20. CONCLUSION A simple approach is proposed in this paper to reduce the area and power of SQRT CSLA architecture. The reduced number of gates of this work offers the great advantage in the reduction of area and also the power. The modified CSLA architecture is therefore, low area, low power, simple and efficient for VLSI hardware implementation.
- 21. REFERENCES [1] B. Ramkumar, Harish M Kittur “Low power and Area efficient carry select adder,”IEEE Trans,Vol.20,Feb 2012. [2] T. Y. Ceiang and M. J. Hsiao, “Carry-select adder using single ripple carry adder,” Electron. Lett., vol. 34, no. 22, pp. 2101–2103, Oct. 1998. [3] Y. Kim and L.-S. Kim, “64-bit carry-select adder with reduced area,” Electron. Lett., vol. 37, no. 10, pp. 614–615, May 2001. [4] J. M. Rabaey, Digtal Integrated Circuits—A Design Perspective.Upper Saddle River, NJ: Prentice-Hall, 2001. [5] Samir Palnitkar, “Verilog Hdl: A Guide to Digital Design and Synthesis”2005,2nd Edition.