![Design and Simulation of Five Level Cascaded Inverter using Multilevel Sinusoidal Pulse
Width Modulation Strategies
V.Manimala
PG Student/EEE Department
Mepco Schlenk Engineering College
Sivakasi,Tamilnadu,India
E-mail:malajan22@gmail.com
Mrs.N.Geetha M.E.,
Asst Professor/EEE Department
Mepco Schlenk Engineering College
Sivakasi,Tamilnadu,India
Email:geethanatarajan04@gmail.com
Dr.P.Renuga
Asso Professor/EEE Department
Thiagarajar College of Engineering
Madurai-15,Tamilnadu,India
E-mail:preee@tce.edu.in
Abstract-This paper proposes design and simulation of single
phase cascaded five level inverter. The inverter can produce five
different output voltage levels across the load. The multilevel
sinusoidal pulse width modulation switching strategy was used
and THD value for every scheme was analyzed. The main
advantage of this technique is the ability to reduce harmonics.
MATLAB/SIMULINK software was used for simulation and
verification of the proposed circuit for implementing FPGA
based five level cascaded inverter. The proposed circuit produces
high output voltage without use of transformers and lower
electromagnetic interference.
Keywords- multilevel inverter, multilevel Sinusoidal pulse
width modulation, five level inverter, total harmonic distortion
I. INTRODUCTION
Recently the multilevel inverter topology has drawn
tremendous interest in the power industry since it can easily
provide the high power required for high power
applications such as static VAR compensation, active filters
so that large motors can be controlled by high power
adjustable frequency drives. The unique structure of
multilevel voltage source inverters allows them to reach
high voltages with low harmonics without the use of
transformers or series connected synchronized switching
devices. There are three main topologies of multilevel
inverter, they are diode clamped, flying capacitor and
cascaded inverters [1]-[3].
Field-Programmable Gate Arrays (FPGA) are standard
integrated circuits that can be programmed by the user to
perform a variety of complex logic functions. The high
level of integration available with these devices are
currently upto 500,000 gates.
PWM is a common control strategy used in many
different applications. This technique is the heart of the
inverter control signal. Several modulation control
strategies have been proposed or adopted for multilevel
inverters including the following: multilevel sinusoidal
pulse width modulation, multilevel selective harmonic
elimination, and space-vector modulation. In this paper
multilevel sinusoidal pulse width modulation for five level
cascaded inverter is developed. To develop the model of
five level cascaded multilevel inverter, simulation is done
based on MATLAB/SIMULINK software.
II. CASCADED MULTILEVEL INVERTER
A cascaded multilevel inverter consists of a series of H-
Bridge (single phase full bridge) inverter units. The general
function of this multilevel inverter is to synthesize a desired
voltage from several separate dc sources (SDCSs), which
may be obtained from batteries, fuel cells or solar cells
[1],[8]. The number of H-Bridge module (M), depends on
the number of levels (N) and can be written as
M = (N-1)/2
For example, a 5-level cascaded inverter has two full
bridges. The structure of single phase cascaded five level
inverter is shown in the figure 1. By different combinations
of the four switches S1-S4, each inverter level can generate
three different voltage outputs, +Vdc, -Vdc, and zero. The
AC output of each of the different levels of inverters are
connected in series such that the synthesized voltage
waveform is the sum of the inverter outputs.
Advantages:
• Elimination of excessively large number of bulky
transformers required by the multi-phase inverters.
• Avoidance of extra clamping diodes and flying
capacitors which are required by diode clamped
and flying capacitors multilevel inverters.
• Simple and modular configuration.
• Flexibility in extending to higher number of levels.
III. MULTILEVEL SINUSODIAL PULSE WIDTH
MODULATION
The advent of the transformer less multilevel inverter
topology has brought various pulse width modulation
schemes to control the switching of the active devices in
each of the multiple voltage levels in the inverter.
Multilevel inverter is based on classical two levels
sinusoidal pulse width modulation (SPWM) with triangular
carrier and reference waveform. Only difference between
two level SPWM and multilevel SPWM [4]-[7] is the
number of carriers used. For N level inverter N-1 carriers
are used. For example for constructing five level we need
four carriers. Carriers have the same frequency fc and the
peak–peak amplitude Ac and are disposed so that the bands
they occupy are contiguous. The zero reference is placed in
the middle of the carrier set. The modulating signal is a
sinusoidal waveform of frequency fr and amplitude Ar. At
every instant each carrier is compared with the modulating
280
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] Carrara G. et
Analysis", Tr
] Zhou, K., an
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] B.P McGrath,
Multilevel In
VOL. 49, NO
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PWM Method
Sept.-Oct. 19
] Keith A. Corz
“Control of
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nd Wang, D.:
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EE Trans. Ind. E
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99.
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Cascaded Mult
vol. 19, no. 3, Ma
ERENCES
Multilevel conver
ns. Ind. Appl., v
miliant, “A new c
Power Electron.,
F. Z. Peng, “M
s, and applicatio
24–738, Aug. 200
ultilevel PWM M
ower Electronics
‘Relationship B
Carrier-based PW
lectron., vol 49,n
mes," Multicarri
Transactions on
2.
vel Multilevel I
nd. Applicat., Vo
Wielebski , Fang Z
ilevel Inverter”,
ay 2004
rters—A new bre
ol. 32, no. 3, pp
cascaded multilev
vol. 17, pp. 125
Multilevel inverte
ons,” IEEE Trans
02.
Method: A Theo
, vol. 7,no 3.July
Between Space-V
WM: A Compreh
no 1,feb2002
er PWM strategi
industrial electr
Inverter Carrier-
o1.35, pp. 1098.
Z. Peng and Jin W
, IEEE Trans. P
eed of
. 509–
vel H-
5–131,
ers: A
s. Ind.
retical
y1992
Vector
ensive
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ronics,
-Based
1 107,
Wang,
Power
283](https://image.slidesharecdn.com/manimala2011r4-170816060904/85/Manimala2011-r4-4-320.jpg)
Manimala2011 r4
- 1. Design and Simulation of Five Level Cascaded Inverter using Multilevel Sinusoidal Pulse Width Modulation Strategies V.Manimala PG Student/EEE Department Mepco Schlenk Engineering College Sivakasi,Tamilnadu,India E-mail:[email protected] Mrs.N.Geetha M.E., Asst Professor/EEE Department Mepco Schlenk Engineering College Sivakasi,Tamilnadu,India Email:[email protected] Dr.P.Renuga Asso Professor/EEE Department Thiagarajar College of Engineering Madurai-15,Tamilnadu,India E-mail:[email protected] Abstract-This paper proposes design and simulation of single phase cascaded five level inverter. The inverter can produce five different output voltage levels across the load. The multilevel sinusoidal pulse width modulation switching strategy was used and THD value for every scheme was analyzed. The main advantage of this technique is the ability to reduce harmonics. MATLAB/SIMULINK software was used for simulation and verification of the proposed circuit for implementing FPGA based five level cascaded inverter. The proposed circuit produces high output voltage without use of transformers and lower electromagnetic interference. Keywords- multilevel inverter, multilevel Sinusoidal pulse width modulation, five level inverter, total harmonic distortion I. INTRODUCTION Recently the multilevel inverter topology has drawn tremendous interest in the power industry since it can easily provide the high power required for high power applications such as static VAR compensation, active filters so that large motors can be controlled by high power adjustable frequency drives. The unique structure of multilevel voltage source inverters allows them to reach high voltages with low harmonics without the use of transformers or series connected synchronized switching devices. There are three main topologies of multilevel inverter, they are diode clamped, flying capacitor and cascaded inverters [1]-[3]. Field-Programmable Gate Arrays (FPGA) are standard integrated circuits that can be programmed by the user to perform a variety of complex logic functions. The high level of integration available with these devices are currently upto 500,000 gates. PWM is a common control strategy used in many different applications. This technique is the heart of the inverter control signal. Several modulation control strategies have been proposed or adopted for multilevel inverters including the following: multilevel sinusoidal pulse width modulation, multilevel selective harmonic elimination, and space-vector modulation. In this paper multilevel sinusoidal pulse width modulation for five level cascaded inverter is developed. To develop the model of five level cascaded multilevel inverter, simulation is done based on MATLAB/SIMULINK software. II. CASCADED MULTILEVEL INVERTER A cascaded multilevel inverter consists of a series of H- Bridge (single phase full bridge) inverter units. The general function of this multilevel inverter is to synthesize a desired voltage from several separate dc sources (SDCSs), which may be obtained from batteries, fuel cells or solar cells [1],[8]. The number of H-Bridge module (M), depends on the number of levels (N) and can be written as M = (N-1)/2 For example, a 5-level cascaded inverter has two full bridges. The structure of single phase cascaded five level inverter is shown in the figure 1. By different combinations of the four switches S1-S4, each inverter level can generate three different voltage outputs, +Vdc, -Vdc, and zero. The AC output of each of the different levels of inverters are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. Advantages: • Elimination of excessively large number of bulky transformers required by the multi-phase inverters. • Avoidance of extra clamping diodes and flying capacitors which are required by diode clamped and flying capacitors multilevel inverters. • Simple and modular configuration. • Flexibility in extending to higher number of levels. III. MULTILEVEL SINUSODIAL PULSE WIDTH MODULATION The advent of the transformer less multilevel inverter topology has brought various pulse width modulation schemes to control the switching of the active devices in each of the multiple voltage levels in the inverter. Multilevel inverter is based on classical two levels sinusoidal pulse width modulation (SPWM) with triangular carrier and reference waveform. Only difference between two level SPWM and multilevel SPWM [4]-[7] is the number of carriers used. For N level inverter N-1 carriers are used. For example for constructing five level we need four carriers. Carriers have the same frequency fc and the peak–peak amplitude Ac and are disposed so that the bands they occupy are contiguous. The zero reference is placed in the middle of the carrier set. The modulating signal is a sinusoidal waveform of frequency fr and amplitude Ar. At every instant each carrier is compared with the modulating 280 ___________________________________ 978-1-4244-8679-3/11/$26.00 ©2011 IEEE
- 2. A signal. Each c signal is grea the first o period ,otherw the voltage le the inverters. pulse width m TABLE I SWITC Switches S11 S21 S31 S41 S12 S22 S32 S42 A. Alternative All the c shown in the frequency an shifted by 180 Fig comparison g ater than or lo r second wise it is zer evel, which is The differe modulation (M Figure 1. T CHING STRATEGY s +2Vdc ON OFF OFF ON ON OFF OFF ON e Phase Oppo arriers are al figure 2. In th nd the same a 0º with its adj gure 2. PWM W gives +1 or ower than the half of ro. The result required at th ent types of m MSPWM) is sh Types of MSPWM Y FOR FIVE LEVE Load Voltag +Vdc 0 ON ON OFF ON OFF OFF ON OFF ON ON ON ON OFF OFF OFF OFF osition Dispos lternatively in his method ca amplitude; the jacent carriers Waveform for APO -1 if the mod triangular car the funda ts are added t he output term multilevel sinu hown in the fi M L CASCADED INV ge -Vdc -2Vd OFF OFF ON ON ON ON OFF OFF OFF OFF OFF ON ON ON ON OFF sition (APOD) n position wh arriers have th e carriers are s. OD scheme dulating rrier in amental to give minal of usoidal figure 1. VERTER dc F F F F ) PWM hich is he same e phase B. sa re th C. lin D. th sa an Phase Oppos In this meth ame amplitude eference are in hose below wh Figu . Phase Dispo All the ne are in phas Fig . Phase shifte In this meth he case of ca ame frequency n angle 90º as Fig sition Disposi hod carriers h e. But all the n phase amon hich is shown ure 3. PWM Wav osition(PD) P carriers abov e which is sho gure 4. PWM Wa ed (PS) PWM hod there are arrier disposit y, same ampl shown in the gure 5. PWM wa ition(POD) P have the same e carriers abo ng them but i in the figure veform for POD WM ve and below own in the fig aveform for PD s e two carriers tion PWM .T litude and are figure 5. aveform for PS s WM frequency an ove the zero v in opposition 3. scheme the zero refer gure 4. scheme per module The carriers e phase shifte cheme nd the value with rence as in have ed by 281
- 3. Modulation P The am of MSPWM t Modulation index Ma Where N N- numbe Frequency IV. SIMUL The sing various PWM technique ar R2007a.For f needed for sim the each brid output. MOSF reducing the h proposed cir modulation t technique. F techniques, si in the simul voltages are analysis for a Figure 6. Simu Parameters mplitude modu techniques are TABLE II M APOD A A c r N ' ’ is given by N’ er of levels in y modulation M LATION CIRCUI IN gle phase cas M techniques re simulated five level casc mulation as sh dge is added FET switches harmonics in rcuit uses mu technique tha For all the imulations are ation circuit noted. Tota all the PWM te ulation circuit of ulation indice e shown in the MODULATION IND POD A A c r N ' N = (N-1)/2 the inverter ratio is given Mf = fr /fc IT FOR CASCA NVERTER scaded five l s and Switch with the caded inverte hown in the f in series to o s are used as p the output vo ultilevel sinu an the switch e configurati e done by var and their co al Harmonic echniques are f five level cascad es for differen e table. DEX PD P A A c r N ' A A n by ADED FIVE LE level inverter hing angle va use of MA er two H-bridg figure. The ou obtain the fiv power switch oltage wavefor usoidal pulse hing angle va ions of MS rying the sub orresponding Distortion e done. ded multilevel in nt types PS A A c r VEL r using ariation ATLAB ges are utput of e level hes. For rm, the width ariation SPWM system output (THD) nverter Figure 7. Outpu Figure 8. Figure 9. Figure 1 ut voltage wavefo tec Output Voltage w . Output Voltage 0. Output Voltag orm using switch chnique waveform using A waveform using ge waveform usin hing angle variatio APOD PWM POD PWM ng PD PWM on 282
- 4. Figur THD valu same and it variation tech various modu are analyzed modulation i Comparing a harmonics for Figure This wor sinusoidal pu five level inv waveform ca different conf modulation t opposition dis the others. Th appropriate m can reduce ha re 11. Output volt ue for all the is reduced 1 hnique with ulation indice as shown in indices resul all the types o r POD PWM t 12. THD analysi V. C rk proposed ulse width m verter. The h an be reduce figuration of m techniques. T sposition PW he harmonics modulation ind armonics in th tage waveform us MSPWM te 18 percent fro THD value es for every M n figure 12. T lts in reduct of PWM we than the other s for different typ ONCLUSION the simula modulation sc harmonics in ed significant multilevel sin he harmonic WM contains lo s can be reduc dices. By incr he output volta sing PS PWM echniques are om switching of 45%. TH MSPWM tech The increase tion of harm have slightly rs. pes of MSPWM ation of mu cheme for ca the output v tly by utilizi nusoidal pulse contents for ower harmoni ced by selecti reasing the lev age waveform nearly g angle HD for hniques in the monics. y lower ltilevel ascaded voltage ng the e width r phase cs than ing the vels we m. [1] [2] [3] [4] [5] [6] [7] [8] ] J. S. Lai and power conver 517, May/Jun ] K. A. Corzine bridge drive,” Jan. 2002. ] J. Rodriguez, survey of top Electron.,vol. ] Carrara G. et Analysis", Tr ] Zhou, K., an Modulation a Analysis’, IEE ] B.P McGrath, Multilevel In VOL. 49, NO ] Leon M. Tal PWM Method Sept.-Oct. 19 ] Keith A. Corz “Control of Electronics v REFE F. Z. Peng, “M rters,” IEEE Tran n. 1996. e and Y. L. Fam ” IEEE Trans. P J. S. Lai, and pologies, controls . 49, no. 4, pp. 72 al., "A New Mu ranscations on Po nd Wang, D.: and Three-phase C EE Trans. Ind. E ,D.Grahame Holm nverters", IEEE T O. 4, August 2002 lben et al. “Nov d, lEEE Trans. I 99. zine, Mike W. W Cascaded Mult vol. 19, no. 3, Ma ERENCES Multilevel conver ns. Ind. Appl., v miliant, “A new c Power Electron., F. Z. Peng, “M s, and applicatio 24–738, Aug. 200 ultilevel PWM M ower Electronics ‘Relationship B Carrier-based PW lectron., vol 49,n mes," Multicarri Transactions on 2. vel Multilevel I nd. Applicat., Vo Wielebski , Fang Z ilevel Inverter”, ay 2004 rters—A new bre ol. 32, no. 3, pp cascaded multilev vol. 17, pp. 125 Multilevel inverte ons,” IEEE Trans 02. Method: A Theo , vol. 7,no 3.July Between Space-V WM: A Compreh no 1,feb2002 er PWM strategi industrial electr Inverter Carrier- o1.35, pp. 1098. Z. Peng and Jin W , IEEE Trans. P eed of . 509– vel H- 5–131, ers: A s. Ind. retical y1992 Vector ensive ies for ronics, -Based 1 107, Wang, Power 283