![Chapter 1
Introduction
As one of the fastest changing and evolving fields today, the research in microelec-
tronics and MEMS technology is constantly looking for new and innovative ways to
increase the performance and reduce the size of their devices. For many decades,
the driving force behind this technological progress was the so-called Moore’s Law,
predicting an exponential miniaturisation and performance increase of electronic
components. Due to physical limitations, this evolution is slowly coming to a fore-
seeable halt. In order to keep up the advancement of technology, innovations in the
domain of functional diversity, the so-called more-than-Moore domain, are needed.
Figure 1.1 shows a graphical depiction of this development. One key aspect, thereof,
lies in hybrid integration of electronics and MEMS-based transducers in one single
device. During the past decades, mainly two-dimensional side-by-side integration
concepts, such as Multi Chip Modules (MCM) and System on Chip (SoC), have
been explored and applied. Lately, in an effort to further reduce the size of these
devices, a strong trend towards three-dimensional integration has emerged. [1]
Figure 1.1: The foreseeable halt of Moore’s Law has to be compensated for to keep
up the technological advancement. Therefore, a dual trend of traditional miniatur-
isation and functional diversification (More than Moore) has emerged, combining
logic and non-logic content, such as sensors and actuators. [2]
8](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-12-320.jpg)
![Both CMOS and MEMS processing technologies, respectively, are well estab-
lished and typically provide short develpoment times, low fabrication costs, and
high yields. The integration of separately fabricated CMOS and MEMS chips to
a System in Package (SiP) is, thus, regarded a very versatile and cost-effective
solution. Especially combined with the general trend towards three-dimensional
integration, the SiP solution provides a lot of advantages.
The most obvious benefit of vertical stacking of single chips is the reduction of
footprint. As a result, the package size as well as the overall volume and weight
of the device decreases. Since area equals money, this directly translates to a cost
reduction. An additional advantage of this compact integration is an improvement
of the system performance. 3D integration provides the possibility for shorter sig-
nal lengths which in turn enhances the transmission speed and lowers the parasitic
capacitances as well as the power consumption. Especially for demanding applica-
tions, such as stacked DDR memory, these improvements bear a high significance
and push the advancement of electronic devices.
Figure 1.2: An overview of TSV aspect ratio domains for different applications.
With an aspect ratio over 8 (via height = 350 µm, = 42 µm) the TSV tech-
nology, presented in this work, lies high in the upper left corner of the graph. [3]
However, to achieve the aforesaid improvements, the three-dimensional integra-
tion technology relies on vertical interconnections that ensure the electrical contact
of the functional layers of the stacked chips. In order to fully establish vertically
stacked SiP systems, reliable and cost-efficient Through Silicon Via (TSV) tech-
nologies are necessary. Strong development efforts are being made in this direction.
Already a variety of commercially available products exist that utilize vertically
stacked SiP systems with TSV interconnections. In figure 1.2, an overview of TSV
9](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-13-320.jpg)
![1 Introduction
technologies for different fields of application is shown. The applications range
from very short and dense TSVs, as used in logic 3D SoC/SiP, to long vias with
low density, applied e.g. for MEMS and sensors. A very important parameter for
TSVs is the aspect ratio which is defined as the quotient of via length and width.
1.1 Project Definition & Goals
The aim of this project is to develop and fabricate a novel type of RF-capable TSV.
The focus of this thesis is twofold. It lies, firstly, in the elaboration of a new TSV
technology to increase the RF conductibility, and secondly, in the construction and
implementation of a fully automated tool for the assembly process of TSV metal
cores.
The TSV technology is based on a research project, performed at the microsys-
tem technology lab at KTH Stockholm [1]. It consists of the magnetic assembly
of pre-fabricated nickel conductors into etched via holes. The assembly was con-
ducted by a manual process. Within this master thesis project, it was the main
goal to convert the proposed manually conducted assembly into a fully automated
process. In order to reach this goal, the design and construction of an assembly
tool, which incorporates high precision wafer handling robotics, will form the main
task throughout this thesis work.
Furthermore, as a second focus, this project aims to develop a novel TSV tech-
nology with enhanced high-frequency signal transmission properties. By means of
applying a thin gold layer on the perimeter of the nickel conductors, the RF con-
ductibility of the TSVs is increased. Because of the skin effect, which causes the
current in a conductor to flow close to its surface, all the current will be confined
to the gold layer. This effect assures an optimal improvement of the RF charac-
teristics. As a concluding task, the newly developed assembly tool will be used to
assemble the novel via conductors and manufacture test devices for the evaluation
of the RF capability of these TSVs.
10](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-14-320.jpg)
![2 Background
2.1.1 Via Structure and Fabrication
The fabrication of via holes is typically the first process step in the formation of
TSVs. For the most part, it already determines the overall shape and functionality
of the TSV. The most important characteristics of a TSV are the via diameter,
the via depth, the aspect ratio, plus the shape of the sidewalls. Typically, the via
diameters vary between 5 to 150 µm and the via depths typically range from 20 to
200 µm. Typical aspect ratios are above 1 but rarely exceed 10. The basic shapes
of the sidewalls are either straight or tapered (see fig. 2.1). Specific applications,
though, have shown that the topology of the sidewalls have a profound impact on
the via performance and manufacturability. Rough surfaces pose a big challenge for
electroplating steps and are often cause for high conductive losses in high-frequency
signals. Special care is therefore taken to ensure a smooth profile. In addition, the
overall design of the via hole tends to take much more elaborate shapes in order to
optimise its performance for specific applications.
The state-of-the-art fabrication techniques used to process via holes can gener-
ally be divided into three categories. The most common of which is a dry etching
technique called Deep Reactive Ion Echting (DRIE) [4, 5, 6, 7, 8, 9, 10, 11] while
the other two are wet etching [6] and drilling processes [12].
A dielectric layer between the core and the sidewall is necessary to insulate
the via from the substrate. There are two main types of insulation concepts. One
is Chemical Vapour Deposition (CVD) of silicon dioxide, silicon nitride, or other
inorganic dielectric materials while the other utilizes organic dielectrics. Because of
its CMOS compatibility and its convenient operation, CVD of SiO2 or Si3N4 are the
most commonly used insulation methods for TSVs [4, 5, 7, 13]. For the insulation
with organic dielectrics [8], various materials such as Bisbenzocyclobutene (BCB)
[9, 14], SU8 [10], epoxy [9], silicone [9], or parylene [11] are being applied. In
many regards, the organic dielectrics outperform their inorganic counterpart. Low
k values of polymer-based dielectrics provide superior electrical properties [10] and
due to their low Young’s modulus, a layer of organic dielectric can absorb thermo-
mechanical stresses, induced by mismatch of the coefficient of thermal expansion
(CTE).
One of the biggest issue with TSVs today is the filling of the conductive core. It
is the most restricting factor in both processability and via dimensions, as it limits
the achievable aspect ratio. As conductive material for the core mainly copper
[6, 7, 9, 10, 11, 15], tungsten [13], polysilicon [5, 13], or low-resistivity silicon [8] are
used. The most widespread process for the metallisation step is the electroplating
of copper. Electroplating methods pose a big challenge, though, since it is very
difficult to fill high-aspect ratio TSVs with a void-free metal core. In search for a
better and more reliable way of filling TSVs, many alternative approaches to the
problem are being explored. These include the filling of TSV holes with conductive
metal pastes [4], the usage of solder balls [16], or the forming of wire-bonded gold
cores [14].
12](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-16-320.jpg)
![2 Background
include sticktion problems, the fragility of the structures, and the sheer number of
components which has a tendency to increase as the scale drops.
The concept of self-assembly in a generic sense describes the autonomous or-
ganisation of a number of components into ordered patterns or the spontaneous
construction of a feature out of its constituent parts without human intervention
[17]. Ultimately this means that the components organise themselves automat-
ically and unguided by external manipulation to exact predetermined locations.
But the real strength of self-assembly lies in the parallelisation, meaning that all
components are being assembled simultaneously in stead of subsequently. Thus,
a much higher throughput and efficiency than conventional pick-and-place can be
achieved.
Self-assembly methods for components ranging from milli- to nanoscale exist in
various forms and are based on different physical principles. These are e.g. shape
matching with the exploitation of the gravitational force [18, 19, 20], capillary
effects [21, 22, 23], electric fields [24], and magnetic forces [25, 26]. While all of the
mentioned principles possess unique fields of application and individual strengths
and weaknesses, this work focusses on the utilisation of magnetic forces. A thorough
review of other self-assembly technologies is given in [17].
Figure 2.3: Behaviour of nickel wires in a magnetic field: a) Approx. 300 straight
nickel wires ( = 35 µm, = 350 µm) without an applied field. b) A magnetic
field of 1.1 T is applied from below. The nickel wires stand perpendicular on the
surface, as they align themselves along the field lines. Courtesy of A. C. Fischer,
KTH Stockholm
Self-assembly by magnetic force offers a very versatile range of applications
and shows distinctive possibilities as well a s a few disadvantages. Namely, this
method offers long-distance forces that are, other than e.g. electric fields, rela-
tively insensitive to the surrounding medium and independent of surface chemistry.
Furthermore, it exhibits a very high energy density and favourable down-scaling
characteristics [27, 28]. Since magnetic force can act either attractive or repellent
it offers a potent process control. In figure 2.3, an example of such a long-distance
magnetic force effect is presented. A limitation of such applications, though, is that
the components need to have permanent magnetic or ferromagnetic functionality
in order to be manipulated.
16](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-20-320.jpg)
![2.3 Self-Assembly in Microtechnology
While very few of these methods have yet been successfully adapted for in-
dustrial use, many concepts are being investigated. Examples are the assembly of
magnetised nanopills directly into electronics chips using CoPt and nickel [25] or
the combination of shape matching and magnetic assembly to align a large number
of chips to predetermined positions on wafer scale using NdFeB magnets [29]. A
further example is the programmable magnetic self-assembly of micro sized electric
components with Ni anchors [30].
2.3.1 Magnetic Assembly of TSV Conductor Material
The concept of utilizing a contact-free magnetic self-assembly process to fabri-
cate high aspect ratio void-free TSVs has been devised in previous work at the
Microsystem Technology Lab at KTH [1]. Since this master thesis includes the
automation of this process, this section provides an explanatory overview of this
assembly process.
Figure 2.4: Via assembly process: a) DRIE process to fabricate via holes b) mag-
netic assembly of nickel wires into the via holes c) filling and curing of BCB that
acts as an insulation layer between the via core and the substrate. Courtesy of A.
C. Fischer, KTH Stockholm
As the schematic depiction in figure 2.4 shows, the assembly process consists of
three main steps. First, there is the formation of the via holes by DRIE etching.
The etch is done through the entire height of the silicon substrate (350 µm) and
stops at the back-side silicon oxide (see figure 2.4 a). Secondly, the magnetic
assembly of the nickel conductors into the via holes is performed (see figure 2.4
b). By the application of a magnetic field from the back-side of the wafer, the
conductor wires align themselves normal to the surface (compare figure 2.3) and
can be assembled into the holes. Lastly, the gap between the sidewall of the via hole
and the assembled conductor has to be filled with a dielectric material. Therefore
BCB is applied in liquid form and cured on a vacuum hotplate to ensure a void-free
enclosure of the nickel rods.
17](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-21-320.jpg)
![4.1 Wire Preparation
Nickel was chosen as conductive material for the cores for its ferromagnetic
properties. Since nickel is commercially available in form of wires with diameters
down to 10 µm, there is a cost-efficient supply of core resources available. The pre-
fabrication of nickel cores consists of the deposition of gold on its circumference
and the cutting process to manufacture single rods out of long wires. These process
steps are described in the following sub-sections.
4.1.1 Gold Plating
As discussed in section 2.2, a good RF performance can be achieved by depositing
a gold layer on top of the nickel cores. The specifications suitable for broad band
RF capability dictate a gold layer thickness of 1.5 µm. Furthermore, the gold layer
thickness has to be uniform around the wire which puts a very high demand on the
depositioning process. As shown in previous research [31], electroplating is suited
for the deposition of metals on wire surfaces with micro scale diameters. In contrast
to electroless gold plating, electroplating shows a good process controllability and
a high plating rate. In figure 4.1, the result of this plating process is shown. An
ion beam milled recess in the wire reveals the thickness and the uniformity of the
gold layer.
Figure 4.2: Wire cutting: After the gold plating (a), the nickel wire are transferred
to a dummy wafer (b) and then spin-coated with photoresist (c). Embedded in this
protective layer of photoresist, the wires can be cut with a dicing tool (d), without
the risk of bending the wires. (e) shows the top and cross-sectional views of a cut
nickel wire, still embedded in photoresist. By dissolving the resist layer the wires
can then be released. (f) shows a single cut wire with clearly visible edges from the
cutting process (as discussed in 3.3).
29](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-33-320.jpg)
![4 Fabrication of RF-capable TSVs
an excess amount of wires was deposited on top of the wafer, as shown in figure
4.3 e). The application of a magnetic field from below the wafer causes the wires
to erect themselves perpendicular to the surface, as depicted in figure 4.3 f). Com-
puter controlled and completely autonomous, robotic movements of the magnet
then drag the metal rods into the via holes (figure 4.3 g).
4.4 Insulation Layer
The second part of the fabrication process is completed by the application of the in-
sulation layer. With the metal cores already in place, the insulating material is ap-
plied in liquid form rather than deposited (e.g. CVD), as it is most commonly done
in industrial applications. The challenge of this process step, therefore, presents
itself in the application of liquid polymer into the just 2 µm wide gap between
the metal core and the sidewalls of the substrate (figure 4.3 h). Subsequently, the
polymer is hard-cured and the excess BCB on top of the wafer is removed by a
grinding step to uncover the metal rods for the electrical contacting of the vias.
4.4.1 BCB Filling and Curing
The utilisation of organic dielectrics, such as BCB, provides three main features to
the TSV technology. Firstly, the BCB has to insure the total electrical insulation
of the metal core from the silicon substrate. The other two features are on the one
hand, the low k-values of the polymer which lowers the coupling to the substrate
and hence provides superior electrical characteristics. And on the ohter hand,
due to the low Young’s modulus, the polymer layer acts as a buffer for thermo-
mechanical stresses induced by CTE mismatch [1].
For these three features to take full effect it is crucial that the BCB layer is
void-free. In order to achieve this, special measures are taken. First of all, there
is the oxidation step, d) in figure 4.3. After the DRIE process, the sidewalls of
the via holes are covered with a thin passivation layer of C4F8 which shows teflon-
like, hydrophobic properties that would prevent BCB from entering the gap. The
subsequent oxidation process removes this passivation layer from the sidewalls and
leaves a hydrophilic SiO2 surface that, together with the hydrophilic wire surface,
creates a capillary effect that guides the BCB into the gap. To further aid the
filling process, the wafer was heated to 60 ◦C to lower the viscosity of the polymer.
After the manual application of BCB onto the TSV structures, the hard-curing
of the polymer can be conducted. The full polymerisation of BCB is then per-
formed by a temperature ramping cycle, according to the manufacturer’s standard
procedure (for details see appendix C.2). In order to achieve a total void-free insu-
lation layer, the entire curing process is carried out in a vacuum chamber at 0.02
mbar.
32](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-36-320.jpg)
![Chapter 5
Conclusion
This master thesis presents both the improvement of a new TSV technology as
well as the design and construction of an assembly tool which incorporates an
autonomous self-assembly process step for nickel-based via cores. A strong focus lies
thereby on the investigation of the interaction of an applied magnetic field and the
nickel rods. Although self-assembly technology is being explored in contemporary
research (e.g [25, 29]), there is a very low number of such processes that were
successfully transferred to an industrial application. The gap separating the two
domains is very wide which is partly due to the lack of a comprehensive work on
simulation and modelling in this field [17].
Naturally, the development methods and the fabrication restrictions of indus-
trial applications differ from those in an academic research environment, such as
the MST lab at KTH Stockholm. Attributes such as the implementation of non-
standard materials or the throughput of the fabrication process generally are of
minor significance in research, whereas in an industrial background these factors
are ultimately decisive for the realisation or dismissal of novel technologies. A fur-
ther aspect, which is important for industrial application, is the cost-effectiveness of
the overall fabrication process, low material expenses, and available infrastructure.
Typically, in an academic environment it is not feasible to develop a novel tech-
nology that already fulfils all the criteria relevant for industrial uses. However,
the closer a research project gets to these requirements the more realistic is the
crossover to industrial application. Because of its nature, this project manages to
propose not only a novel TSV technology but also a fabrication process that incor-
porates many close to industry-ready attributes. Thus, this project provides not
only the proof of concept but also works towards the development of an automated
fabrication tool. This approach allowes e.g. for the implementation of a highly par-
allelised self-assembly process of TSV cores with a high throughput. Furthermore,
only commercially available material resources are utilised such as BCB and nickel
wires to ensure a cost-effective fabrication.
37](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-41-320.jpg)
![5 Conclusion
5.1 Project Summary
In the beginning of this project, the scope of this master thesis work was determined
and specific goals were formulated. In the course of six months, the presented work
has been performed in pursuit of said goals. This section is therefore dedicated to
summarise the performed work and to evaluate the achievements this thesis aimed
for.
The basis for this project was laid by preceding research, conducted at the Mi-
crosystem Technology Lab of the KTH Royal Institute of Technology in Stockholm
[1]. In said work, the utilisation of pre-fabricated nickel rods as conductive via
cores which are magnetically assembled into the via holes is proposed. A proof
of concept of this novel approach was provided by a TSV filling test, executed by
an entirely manual process. As this process suffers from low controllability and
repeatability, it was the task of this project to devise and realise a reliable and
fully automated assembly process step.
As elaborated in chapter 3, a robotic assembly tool was designed and con-
structed to set the foundation for a fully autonomous TSV fabrication tool. The
construction of said tool contained the incorporation of the high-precision wafer
handler robot ISEL IWH-series as well as a considerable amount of custom-built
tools and structures. Furthermore, the development of said tool also contained the
implementation of a communication interface between a computer and the robot
as well as the programming of a control software for the assembly process. Thus
equipped, the resulting tool provides excellent controllability through the control
software and it is able to execute the magnetic assembly process as an automated
cassette-to-cassette process. A special focus was laid on the investigation of the
behaviour of nickel rods under the influence of a moving magnetic field. The gained
knowledge was then applied to the assembly process by an iterative optimisation
of the movement parameters. As shown in figure 3.6, it was, thus, accomplished
to devise a trajectory which ensures a repeated yield of 100% at a measured filling
rate of 100 wires per minute. Furthermore, the parallelised nature of this process
favours the assembly of large numbers of wires, as it would for example not take
10 seconds to assemble 1000 wires.
Moreover, a second task of this project was defined and initiated. Based upon
the TSV technology presented in [1], a novel approach to the pre-fabrication of
nickel conductors was to be devised in order to provide RF capabilities for TSVs
fabricated with this technology. While nickel possesses ferromagnetic properties
and is therefore well suited for magnetic self-assembly, its high-frequency signal
transmission properties, i.e. RF conductibility, are very poor, as indicated in fig-
ure 2.2. Non-ferromagnetic materials, e.g. gold, exhibit significantly better RF
conductibility. To improve the conductivity of the given concept of TSVs, a layer
of gold was applied to the perimeter of the nickel conductors. This addition of
a highly conductive material as an outer layer allowed for an excellent utilisation
of the skin effect which causes electric current to flow just below the surface of a
38](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-42-320.jpg)
![Bibliography
[1] A. C. Fischer, N. Roxhed, T. Haraldsson, N. Heinig, G. Stemme, and
F. Niklaus, “Fabrication of high aspect ratio through silicon vias (TSVs) by
magnetic assembly of nickel wires,” proc. MEMS, pp. 37–40, Jan. 2011.
[2] W. Arden, M. Brillou¨et, P. Cogez, M. Graef, B. Huizing, and R. Mahnkopf,
“More than Moore,” ITRS White Paper, 2009.
[3] Y. Development, “3D TSV Integration Webinar Presentation,” 2010.
[4] M. Motoyoshi, “Through-Silicon Via (TSV),” proc. IEEE, vol. 97, pp. 43–48,
Jan. 2009.
[5] D. S. Tezcan, K. De Munck, N. Pham, O. Luhn, A. Aarts, P. De Moor,
K. Baert, and C. Van Hoof, “Development of vertical and tapered via etch
for 3D through wafer interconnect technology,” proc. EPTC, pp. 22–28, Dec.
2006.
[6] P. Nilsson, A. Ljunggren, R. Thorslund, M. Hagstrom, and V. Lindskog,
“Novel through-silicon via technique for 2d/3d SiP and interposer in low-
resistance applications,” proc. ECTC, pp. 1796–1801, May 2009.
[7] M. J. Wolf, T. Dretschkow, B. Wunderle, N. Jurgensen, G. Engelmann,
O. Ehrmann, A. Uhlig, B. Michel, and H. Reichl, “High aspect ratio TSV
copper filling with different seed layers,” proc. ECTC, pp. 563–570, May 2008.
[8] M. Rimskog, “Through Wafer Via Technology for MEMS and 3D Integration,”
proc. IEMT, pp. 286–289, Oct. 2007.
[9] D. S. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan, and B. Swinnen,
“Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer
level packaging,” proc. ECTC, pp. 1159–1164, May 2009.
[10] S. W. Ho, S. W. Yoon, Q. Zhou, K. Pasad, V. Kripesh, and J. H. Lau, “High
RF performance TSV silicon carrier for high frequency application,” proc.
ECTC, pp. 1946–1952, May 2008.
[11] D. S. Tezcan, N. Pham, B. Majeed, P. De Moor, W. Ruythooren, and K. Baert,
“Sloped Through Wafer Vias for 3D Wafer Level Packaging,” proc. ECTC,
pp. 643–647, May 2007.
42](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-46-320.jpg)
![BIBLIOGRAPHY
[12] P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Integration Technology
and Application of 3D Integration Circuits. Wiley, KGaA, 2008.
[13] M. Koyanagi, T. Fukushima, and T. Tanaka, “High-Density Through Silicon
Vias for 3-D LSIs,” proc. IEEE, vol. 97, pp. 49–59, Jan. 2009.
[14] A. C. Fischer, N. Roxhed, G. Stemme, and F. Niklaus, “Low-cost through
silicon vias (TSVs) with wire-bonded metal cores and low capacitive substrate-
coupling,” proc. MEMS, pp. 480–483, Jan. 2010.
[15] K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, “Thermo-
mechanical reliability of 3-D ICs containing through silicon vias,” proc. ECTC,
pp. 630–634, May 2009.
[16] J. Gu, W. T. Pike, and W. J. Karl, “A novel vertical solder pump structure
for through-wafer interconnects,” proc. MEMS, pp. 500–503, Jan. 2010.
[17] M. Mastrangeli, S. Abbasi, C. Varel, C. Van Hoof, J. P. Celis, and
K. F. B¨ohringer, “Self-assembly from milli- to nanoscales: methods and
applications,” Journal of Micromechanics and Microengineering, vol. 19,
pp. 083001+, Aug. 2009.
[18] H. J. J. Yeh and J. S. Smith, “Fluidic self-assembly for the integration of GaAs
light-emitting diodes on Si substrates,” Photonics Technology Letters, IEEE,
vol. 6, pp. 706–708, June 1994.
[19] J. K. Tu, J. J. Talghader, M. A. Hadley, and J. S. Smith, “Fluidic self-assembly
of InGaAs vertical cavity surface emitting lasers onto silicon,” Electronics
Letters, vol. 31, pp. 1448–1449, Aug. 1995.
[20] I. Soga, S. Hayashi, Y. Ohno, S. Kishimoto, K. Maezawa, and T. Mizutani,
“Direct integration of GaAs HEMTs on AlN ceramic substrates using fluidic
self-assembly,” Electronics Letters, vol. 41, pp. 1275–1276, Nov. 2005.
[21] U. Srinivasan, M. A. Helmbrecht, C. Rembe, R. S. Muller, and R. T.
Howe, “Fluidic self-assembly of micromirrors onto microactuators usingcapil-
lary forces,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 8,
pp. 4–11, Jan. 2002.
[22] K. L. Scott, T. Hirano, H. Yang, H. Singh, R. T. Howe, and A. M. Nikne-
jad, “High-performance inductors using capillary based fluidic self-assembly,”
Journal of Microelectromechanical Systems, vol. 13, pp. 300–309, Apr. 2004.
[23] X. Xiong, Y. Hanein, J. Fang, Y. Wang, W. Wang, D. T. Schwartz, and K. F.
Bohringer, “Controlled multibatch self-assembly of microdevices,” Journal of
Microelectromechanical Systems, vol. 12, pp. 117–127, Apr. 2003.
[24] C. F. Edman, R. B. Swint, C. Gurtner, R. E. Formosa, S. D. Roh, K. E.
Lee, P. D. Swanson, D. E. Ackley, J. J. Coleman, and M. J. Heller, “Electric
43](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-47-320.jpg)
![BIBLIOGRAPHY
field directed assembly of an InGaAs LED onto silicon circuitry,” Photonics
Technology Letters, IEEE, vol. 12, pp. 1198–1200, Sept. 2000.
[25] C. Fonstad, “Magnetically-Assisted Statistical Assembly - a new heteroge-
neous integration technique,” tech. rep., MIT, 2002.
[26] E. Iwase and I. Shimoyama, “Multistep sequential batch assembly of three-
dimensional ferromagnetic microstructures with elastic hinges,” Journal of
Microelectromechanical Systems, vol. 14, pp. 1265–1271, Dec. 2005.
[27] J. S. Agashe and D. P. Arnold, “A study of scaling and geometry effects on
the forces between cuboidal and cylindrical magnets using analytical force
solutions,” Journal of Physics D: Applied Physics, vol. 41, pp. 105001+, May
2008.
[28] O. Cugat, J. Delamare, and G. Reyne, “Magnetic micro-actuators and systems
(MAGMAS),” IEEE Transactions on Magnetics, vol. 39, pp. 3607–3612, Nov.
2003.
[29] Q. Ramadan, Y. S. Uk, and K. Vaidyanathan, “Large scale microcomponents
assembly using an external magnetic array,” Applied Physics Letters, vol. 90,
pp. 172502–172502–3, Apr. 2007.
[30] J. H. Hoo, K. S. Park, R. Baskaran, and K. F. Bohringer, “Programmable self-
assembly for microsystem integration,” proc. TRANSDUCERS, pp. 848–853,
June 2011.
[31] S. Kaimori, T. Nonaka, and A. Mizoguchi, “The development of Cu bonding
wire with oxidation-resistant metal coating,” IEEE Transactions on Advanced
Packaging, vol. 29, pp. 227–231, May 2006.
44](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-48-320.jpg)
![Appendix B
Experimental Data for Filling Rates
Filling experiments were conducted in order to determine the capabilities of the
robotic assembly process and to find an effective and reliable movement strategy.
Multiple via hole arrays with of 10 × 10 holes were filled in the process. Below,
the gathered data is presented in its raw numerical form. For a graphical depiction
of the data, see figure 3.6.
Small Rectangles
The pattern called small rectangles is a pattern of advancing rectangles and is
implemented in the control software under the name Helix. The path length of
this pattern was set to d = 30 (See figure 3.5) and the movement parameters were
taken from the parameter set Slow2 (See appendix B.1).
Time [s] 0 10 20 30 40 80 120 160 200
Filled Holes [%] 0 15 17 20 22 49 73 82 90
Table B.1: Filling rate experiment for the pattern small rectangles with movement
parameter set Slow2
Spline
The spline movement pattern is implemented under the same name and was exe-
cuted with a path length of d = 200 (See figure 3.5). The movement parameter set
was again set to Slow2 (See appendix B.1).
Time [s] 0 5 10 15 20 25 30 40 50 60 80 100
Filled Holes [%] 0 15 25 36 46 51 57 74 78 82 92 96
Table B.2: Filling rate experiment for the pattern spline with movement parameter
set Slow2
48](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-52-320.jpg)
![B.1 Movement Parameter Sets
Slow Spline
The slow spline experiment was conducted with the pattern called spline and path
length of d = 200 (See figure 3.5). The movement parameters were set to re-
allySlow (See appendix B.1). Since this experiment achieved 100% filling yield, it
was repeated to verify its performance.
Time [s] 0 6 13 18 23 27 32 37 42 47 53 66 81
Filled Holes [%] 0 28 45 59 75 79 87 89 90 94 96 98 100
Table B.3: The first filling rate experiment for the pattern slow spline with move-
ment parameter set reallySlow
Time [s] 0 6.5 13 19.5 26 32.5 39 45.5 52 66
Filled Holes [%] 0 48 64 80 91 91 94 95 96 100
Table B.4: The second filling rate experiment for the pattern slow spline with move-
ment parameter set reallySlow
B.1 Movement Parameter Sets
The different movement parameter sets used for the filling rate experiments are
shown in this section. They comprise characteristic values for all three axes.
Slow2
Speed Acceleration Jerk
T 1200 1400 25
R 900 2000 25
Z 950 2000 25
Table B.5: Movement parameter set Slow2
reallySlow
Speed Acceleration Jerk
T 40 1400 25
R 400 2000 25
Z 450 2000 25
Table B.6: Movement parameter set reallySlow
49](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-53-320.jpg)
![Appendix C
Fabrication Specifications
C.1 Wafer Specifications
For the fabrication of RF-capable TSV structures special high resistivity wafers
were used to ensure good signal transmission performance. The exact specifications
of these wafers are given in table C.1.
Price
$/unit
Material Orient.
Diam.
[mm]
Thickn.
[µm]
Surf. Source
Resistivity
[Ωcm]
Comment
$86.60
p-type
Si:B
[100] 100 350 P/P ITME
FZ 5,000-
8,500
SEMI,
1Flat
Table C.1: Specifications of the high resistivity wafers
C.2 BCB Curing Procedure
The curing step of the insulation polymer BCB CYCLOTENER
3022-46 was car-
ried out on a hot plate inside a vacuum chamber at 0.02 mbar. A temperature
ramping procedure was performed according to the manufacturers specifications,
as shown in table C.2.
Step Full Cure
1 15 min ramp to 100 ◦C
2 15 min soak at 100 ◦C
3 15 min ramp to 150 ◦C
4 15 min soak at 150 ◦C
5 60 min ramp to 250 ◦C
6 60 min soak at 250 ◦C
7 cool to < 150 ◦C
Table C.2: Curing procedure for BCB CYCLOTENER
3022-46
50](https://image.slidesharecdn.com/cfd86dc8-e4ba-4890-9529-1c3964e807aa-161020121600/85/MasterThesis_Bleiker-54-320.jpg)
MasterThesis_Bleiker
- 1. Fabrication of Through Silicon Vias (TSVs) with RF Capability by Magnetic Assembly of Nickel Wires SIMON BLEIKER Master’s Degree Project Stockholm, Sweden October 2011 XR-EE-MST 2011:007
- 3. Fabrication of Through Silicon Vias (TSVs) with RF Capability by Magnetic Assembly of Nickel Wires Simon Bleiker Master’s Degree Project Supervisor: Andreas Fischer Examiner: Frank Niklaus October 2011 Microsystem Technology KTH Royal Institute of Technology Stockholm, Sweden
- 5. Abstract Within this master thesis work, a novel TSV technology with RF capabilities is presented. A major focus was laid on the design and the construction of a fully automated fabrication tool for the assembly of Ni TSV cores. The utilisation of the ferromagnetic properties of nickel allowed for a highly parallelised self-assembly process which was implemented in the automated fabrication. Furthermore, a special effort was made to improve the RF capabilities of this type of TSVs. In order to increase the RF conductibility, a novel type of metal conductor was devised and fabricated. The deposition of a thin gold layer on the perimeter of the conductor allowed for an optimal utilisation of the skin effect to enhance the RF performance. The above-mentioned newly developed assembly tool was then used to build RF transmission lines test structures.
- 7. Contents 1 Introduction 8 1.1 Project Definition & Goals . . . . . . . . . . . . . . . . . . . . . . . 10 2 Background 11 2.1 Through Silicon Via (TSV) . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 Via Structure and Fabrication . . . . . . . . . . . . . . . . . . 12 2.2 High-frequency Signal Transmission . . . . . . . . . . . . . . . . . . 13 2.2.1 Skin Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Self-Assembly in Microtechnology . . . . . . . . . . . . . . . . . . . . 15 2.3.1 Magnetic Assembly of TSV Conductor Material . . . . . . . . 17 3 Design and Construction of the Assembly Tool 19 3.1 Wafer Handling & Assembly Stage . . . . . . . . . . . . . . . . . . . 19 3.2 Automated Magnetic Assembly . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 Robot Control Software . . . . . . . . . . . . . . . . . . . . . 22 3.2.2 Movement Trajectories . . . . . . . . . . . . . . . . . . . . . . 23 3.3 Discussion and possible Improvements . . . . . . . . . . . . . . . . . 26 4 Fabrication of RF-capable TSVs 28 4.1 Wire Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.1 Gold Plating . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.2 Wire Cutting . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 Etching the Via Holes . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 Magnetic Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 Insulation Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4.1 BCB Filling and Curing . . . . . . . . . . . . . . . . . . . . . 32 4.4.2 Grinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 Front- and Back-side Metallisation . . . . . . . . . . . . . . . . . . . 33 4.5.1 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5.2 RF Test Structure Design . . . . . . . . . . . . . . . . . . . . 34 5 Conclusion 37 5.1 Project Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3
- 8. CONTENTS A ISEL Robot 45 A.1 ISEL Robot Specifications . . . . . . . . . . . . . . . . . . . . . . . . 45 A.2 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 B Experimental Data for Filling Rates 48 B.1 Movement Parameter Sets . . . . . . . . . . . . . . . . . . . . . . . . 49 C Fabrication Specifications 50 C.1 Wafer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 C.2 BCB Curing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 50 4
- 9. List of Figures 1.1 The foreseeable halt of Moore’s Law has to be compensated for to keep up the technological advancement. Therefore, a dual trend of traditional miniaturisation and functional diversification (More than Moore) has emerged, combining logic and non-logic content, such as sensors and actuators. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 An overview of TSV aspect ratio domains for different applications. With an aspect ratio over 8 (via height = 350 µm, = 42 µm) the TSV technology, presented in this work, lies high in the upper left corner of the graph. . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Cross sectional view of basic TSV designs. a) Solid metal filled TSV, b) annular metal-lined TSV and c) metallined TSV with tapered side wall profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Frequency dependent sheet resistances for various conductive mate- rials. The values for ferromagnetic materials, such as Iron, Nickel, and Cobalt are almost two orders of magnitude bigger than the val- ues for Tungsten, Aluminium, Gold, and Copper. . . . . . . . . . . . 14 2.3 Behaviour of nickel wires in a magnetic field: a) Approx. 300 straight nickel wires ( = 35 µm, = 350 µm) without an applied field. b) A magnetic field of 1.1 T is applied from below. The nickel wires stand perpendicular on the surface, as they align themselves along the field lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Via assembly process: a) DRIE process to fabricate via holes b) magnetic assembly of nickel wires into the via holes c) filling and curing of BCB that acts as an insulation layer between the via core and the substrate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Assembly Robot (ISEL IWH-series) with wafer handler gripper to the left, an LED-beam wafer scanner (Synx M-DW1) at the ”elbow“ joint in the front, and the custom built assembly arm to the right. The assembly arm consists of a permanent magnet mounted on an aluminium sheet and a camera above the magnet. . . . . . . . . . . . 20 5
- 10. LIST OF FIGURES 3.2 The whole assembly setup with the robot arm in the centre of the table, the wafer cassette station and the assembly stage to its right. The assembly process consists of four steps: 1. scanning the cassette for wafers, 2. picking a chosen one and placing it on the assembly stage, 3. positioning the assembly arm and carrying out the mag- netic assembly, 4. putting the wafer back into the cassette. . . . . . 21 3.3 User interface of the robot control software. It includes all necessary functions for the operation of the assembly tool, such as sending robot commands (including a response log), wafer handling opera- tions, positioning of the assembly arm, setting the assembly move- ment parameters, and a visual inspection. . . . . . . . . . . . . . . . 23 3.4 For the filling experiment a TSV array chip, consisting of 10 × 10 via holes ( = 42 µm, depth = 350 µm), was placed in a milled recess to hold it in place during the assembly. . . . . . . . . . . . . . 24 3.5 Robotic assembly trajectories: a) Small advancing rectangles with an edge length of d = 0.76 mm. b) Large spline movement of approx. d = 1.5 cm width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.6 Filling rates for the assembly of via arrays (10 × 10 holes). Two different movement patterns and two different speeds were tested. The slow spline pattern exhibited a yield of 100% and the highest filling rate. See appendix B for complete data. . . . . . . . . . . . . 26 4.1 The TSV metal conductors were pre-fabricated by deposition of a gold layer of 1.5 µm on top of a 35 µm thick nickel wire. . . . . . . . 28 4.2 Wire cutting: After the gold plating (a), the nickel wire are trans- ferred to a dummy wafer (b) and then spin-coated with photoresist (c). Embedded in this protective layer of photoresist, the wires can be cut with a dicing tool (d), without the risk of bending the wires. (e) shows the top and cross-sectional views of a cut nickel wire, still embedded in photoresist. By dissolving the resist layer the wires can then be released. (f) shows a single cut wire with clearly visible edges from the cutting process (as discussed in 3.3). . . . . . . . . . 29 4.3 The TSV fabrication: (a – d) Formation of via holes by DRIE etch- ing. (e – h) Autonomous magnetic assembly of gold coated nickel TSV cores and the application of BCB as an insulation layer. (i – k) Fabrication of the via contacts and transmission lines. . . . . . . . 31 4.4 Transmission line with RF TSVs: a) Cross-sectional and top view schematic of a transmission line with two incorporated TSV feed- throughs. b) Four different configurations of the RF feet-throughs are shown as well as a reference transmission line without TSVs. . . 35 4.5 Transmission line design of the RF test structures and the reference structures. Different lengths t (see table 4.2) were fabricated to deal with field coupling effects. . . . . . . . . . . . . . . . . . . . . . . . . 36 6
- 11. List of Tables 2.1 DC resistances for various conductive materials. . . . . . . . . . . . 13 2.2 RF Sheet Resistance for different conductive materials at f = 75 GHz. 14 4.1 Design specifications for the different TSV configurations. . . . . . . 35 4.2 Different lengths t of the back-side transmission line. . . . . . . . . 36 A.1 Environmental condition for operation of the wafer handler robot. . 45 A.2 Range of movement for the rotational axis T, the radial axis R, the and vertical axis Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 A.3 Maximum speed specification for all three axes. . . . . . . . . . . . . 46 A.4 Precision specification for all three axes. . . . . . . . . . . . . . . . . 46 A.5 Most frequently used commands for the assembly robot. . . . . . . . 47 B.1 Filling rate experiment for the pattern small rectangles with move- ment parameter set Slow2 . . . . . . . . . . . . . . . . . . . . . . . . 48 B.2 Filling rate experiment for the pattern spline with movement pa- rameter set Slow2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 B.3 The first filling rate experiment for the pattern slow spline with movement parameter set reallySlow . . . . . . . . . . . . . . . . . . . 49 B.4 The second filling rate experiment for the pattern slow spline with movement parameter set reallySlow . . . . . . . . . . . . . . . . . . . 49 B.5 Movement parameter set Slow2 . . . . . . . . . . . . . . . . . . . . . 49 B.6 Movement parameter set reallySlow . . . . . . . . . . . . . . . . . . 49 C.1 Specifications of the high resistivity wafers . . . . . . . . . . . . . . . 50 C.2 Curing procedure for BCB CYCLOTENER 3022-46 . . . . . . . . . 50 7
- 12. Chapter 1 Introduction As one of the fastest changing and evolving fields today, the research in microelec- tronics and MEMS technology is constantly looking for new and innovative ways to increase the performance and reduce the size of their devices. For many decades, the driving force behind this technological progress was the so-called Moore’s Law, predicting an exponential miniaturisation and performance increase of electronic components. Due to physical limitations, this evolution is slowly coming to a fore- seeable halt. In order to keep up the advancement of technology, innovations in the domain of functional diversity, the so-called more-than-Moore domain, are needed. Figure 1.1 shows a graphical depiction of this development. One key aspect, thereof, lies in hybrid integration of electronics and MEMS-based transducers in one single device. During the past decades, mainly two-dimensional side-by-side integration concepts, such as Multi Chip Modules (MCM) and System on Chip (SoC), have been explored and applied. Lately, in an effort to further reduce the size of these devices, a strong trend towards three-dimensional integration has emerged. [1] Figure 1.1: The foreseeable halt of Moore’s Law has to be compensated for to keep up the technological advancement. Therefore, a dual trend of traditional miniatur- isation and functional diversification (More than Moore) has emerged, combining logic and non-logic content, such as sensors and actuators. [2] 8
- 13. Both CMOS and MEMS processing technologies, respectively, are well estab- lished and typically provide short develpoment times, low fabrication costs, and high yields. The integration of separately fabricated CMOS and MEMS chips to a System in Package (SiP) is, thus, regarded a very versatile and cost-effective solution. Especially combined with the general trend towards three-dimensional integration, the SiP solution provides a lot of advantages. The most obvious benefit of vertical stacking of single chips is the reduction of footprint. As a result, the package size as well as the overall volume and weight of the device decreases. Since area equals money, this directly translates to a cost reduction. An additional advantage of this compact integration is an improvement of the system performance. 3D integration provides the possibility for shorter sig- nal lengths which in turn enhances the transmission speed and lowers the parasitic capacitances as well as the power consumption. Especially for demanding applica- tions, such as stacked DDR memory, these improvements bear a high significance and push the advancement of electronic devices. Figure 1.2: An overview of TSV aspect ratio domains for different applications. With an aspect ratio over 8 (via height = 350 µm, = 42 µm) the TSV tech- nology, presented in this work, lies high in the upper left corner of the graph. [3] However, to achieve the aforesaid improvements, the three-dimensional integra- tion technology relies on vertical interconnections that ensure the electrical contact of the functional layers of the stacked chips. In order to fully establish vertically stacked SiP systems, reliable and cost-efficient Through Silicon Via (TSV) tech- nologies are necessary. Strong development efforts are being made in this direction. Already a variety of commercially available products exist that utilize vertically stacked SiP systems with TSV interconnections. In figure 1.2, an overview of TSV 9
- 14. 1 Introduction technologies for different fields of application is shown. The applications range from very short and dense TSVs, as used in logic 3D SoC/SiP, to long vias with low density, applied e.g. for MEMS and sensors. A very important parameter for TSVs is the aspect ratio which is defined as the quotient of via length and width. 1.1 Project Definition & Goals The aim of this project is to develop and fabricate a novel type of RF-capable TSV. The focus of this thesis is twofold. It lies, firstly, in the elaboration of a new TSV technology to increase the RF conductibility, and secondly, in the construction and implementation of a fully automated tool for the assembly process of TSV metal cores. The TSV technology is based on a research project, performed at the microsys- tem technology lab at KTH Stockholm [1]. It consists of the magnetic assembly of pre-fabricated nickel conductors into etched via holes. The assembly was con- ducted by a manual process. Within this master thesis project, it was the main goal to convert the proposed manually conducted assembly into a fully automated process. In order to reach this goal, the design and construction of an assembly tool, which incorporates high precision wafer handling robotics, will form the main task throughout this thesis work. Furthermore, as a second focus, this project aims to develop a novel TSV tech- nology with enhanced high-frequency signal transmission properties. By means of applying a thin gold layer on the perimeter of the nickel conductors, the RF con- ductibility of the TSVs is increased. Because of the skin effect, which causes the current in a conductor to flow close to its surface, all the current will be confined to the gold layer. This effect assures an optimal improvement of the RF charac- teristics. As a concluding task, the newly developed assembly tool will be used to assemble the novel via conductors and manufacture test devices for the evaluation of the RF capability of these TSVs. 10
- 15. Chapter 2 Background The following chapter serves the purpose of providing the reader with an introduc- tion to TSV technology. In addition, an explanation of important effects for the transmission of high-frequency signals is provided. The concept of self-assembly is then introduced and its application in MEMS technologies is touched upon. Fi- nally, a description of the nickel wire TSV technology, on which this project is based upon, is given. 2.1 Through Silicon Via (TSV) The purpose of Through Silicon Vias is to vertically interconnect different func- tional layers of a chip or a chip stack. So, in essence, it is an electrical connection from the front- to the back-side of a wafer or a chip. The basic structure of a TSV is rather simple, as it consists of a hole through the substrate, an electrical conductor, and a dielectric that insulates the conductor from the substrate. The fabrication processes and the actual design of TSVs, however, vary strongly and are very much dependent on the target application. Figure 2.1 shows conceptual drawings of three basic TSV designs. Figure 2.1: Cross sectional view on basic TSV designs. a) Solid metal filled TSV, b) annular metal-lined TSV and c) metallined TSV with tapered side wall profile. Courtesy of A. C. Fischer, KTH Stockholm 11
- 16. 2 Background 2.1.1 Via Structure and Fabrication The fabrication of via holes is typically the first process step in the formation of TSVs. For the most part, it already determines the overall shape and functionality of the TSV. The most important characteristics of a TSV are the via diameter, the via depth, the aspect ratio, plus the shape of the sidewalls. Typically, the via diameters vary between 5 to 150 µm and the via depths typically range from 20 to 200 µm. Typical aspect ratios are above 1 but rarely exceed 10. The basic shapes of the sidewalls are either straight or tapered (see fig. 2.1). Specific applications, though, have shown that the topology of the sidewalls have a profound impact on the via performance and manufacturability. Rough surfaces pose a big challenge for electroplating steps and are often cause for high conductive losses in high-frequency signals. Special care is therefore taken to ensure a smooth profile. In addition, the overall design of the via hole tends to take much more elaborate shapes in order to optimise its performance for specific applications. The state-of-the-art fabrication techniques used to process via holes can gener- ally be divided into three categories. The most common of which is a dry etching technique called Deep Reactive Ion Echting (DRIE) [4, 5, 6, 7, 8, 9, 10, 11] while the other two are wet etching [6] and drilling processes [12]. A dielectric layer between the core and the sidewall is necessary to insulate the via from the substrate. There are two main types of insulation concepts. One is Chemical Vapour Deposition (CVD) of silicon dioxide, silicon nitride, or other inorganic dielectric materials while the other utilizes organic dielectrics. Because of its CMOS compatibility and its convenient operation, CVD of SiO2 or Si3N4 are the most commonly used insulation methods for TSVs [4, 5, 7, 13]. For the insulation with organic dielectrics [8], various materials such as Bisbenzocyclobutene (BCB) [9, 14], SU8 [10], epoxy [9], silicone [9], or parylene [11] are being applied. In many regards, the organic dielectrics outperform their inorganic counterpart. Low k values of polymer-based dielectrics provide superior electrical properties [10] and due to their low Young’s modulus, a layer of organic dielectric can absorb thermo- mechanical stresses, induced by mismatch of the coefficient of thermal expansion (CTE). One of the biggest issue with TSVs today is the filling of the conductive core. It is the most restricting factor in both processability and via dimensions, as it limits the achievable aspect ratio. As conductive material for the core mainly copper [6, 7, 9, 10, 11, 15], tungsten [13], polysilicon [5, 13], or low-resistivity silicon [8] are used. The most widespread process for the metallisation step is the electroplating of copper. Electroplating methods pose a big challenge, though, since it is very difficult to fill high-aspect ratio TSVs with a void-free metal core. In search for a better and more reliable way of filling TSVs, many alternative approaches to the problem are being explored. These include the filling of TSV holes with conductive metal pastes [4], the usage of solder balls [16], or the forming of wire-bonded gold cores [14]. 12
- 17. 2.2 High-frequency Signal Transmission 2.2 High-frequency Signal Transmission In electronics and MEMS devices signal transmission plays a major role since al- most every device in this field is dependent on the transportation of information by electrical signals. The general trend towards miniaturisation and 3D integra- tion of chips also includes optimisation of compact signal transmission paths. In fact, 3D integration provides a number of distinct benefits for this field. With ever smaller designs and more compact devices, the signal transmission distances shrink. Smaller signal lengths decrease the parasitic effects of transmission lines and, thus, increase their performance. The three-dimensional integration approach has a great potential for shortening the signal lengths between chips and reducing the parasitics. While low frequency signals are contempt with a simple conductive path, this matter is a bit more delicate for high-frequency signals. Since high-frequency sig- nals are more susceptible to parasitic effects, the demand for good signal transmis- sion performance is getting more predominant. The choice of conductive material which is used to form the signal paths gains in significance. The main reason for this is the fact that the electrical resistance in a conductor is not only dependent on the choice of material but also on the signal frequency, as shown in figure 2.2. Material DC Resistance Copper 1.67 µΩcm standard TSV conductive materials Gold 2.44 µΩcm Aluminium 2.65 µΩcm Tungsten 5.60 µΩcm Cobalt 6.24 µΩcm ferromagnetic materials Nickel 8.71 µΩcm Iron 9.66 µΩcm Table 2.1: DC resistances for various conductive materials. Even though the DC resistances of commonly used conductive materials such as copper, gold, aluminium, or tungsten, are within a very close range to those of ferromagnetic materials like cobalt, nickel, or iron (see table 2.1), there is an enormous discrepancy regarding their performance for high-frequency signal trans- mission. As table 2.2 reveals, nickel as well as the other ferromagnetic materials show very poor RF conductibility characteristics. This discrepancy shows very clearly in the comparison of nickel and gold, whose dc resistances are separated by a factor of 4, while their sheet resistances at 75 GHz differ by a factor of 50. Since the conductive cores of the TSVs, within this thesis work, are made of nickel, they suffer from a low RF performance. In order not to counteract the 13
- 18. 2 Background advantage of short signal lengths by poor high-frequency conductibility, this issue has to be addressed. The nickel can not easily be replaced by another conductive material, since its ferromagnetic properties are essential to the assembly process, as explained in section 2.3. What can be done, though, is to use the nickel core just as a carrier and deposit a layer of gold on its perimeter to increase the RF conductance. This solution still allows the conductive cores to be assembled magnetically, without compromising the RF properties. Figure 2.2: Frequency dependent sheet resistances for various conductive materials. The values for ferromagnetic materials, such as Iron, Nickel, and Cobalt are almost two orders of magnitude bigger than the values for Tungsten, Aluminium, Gold, and Copper. Material RF Sheet Resistance at f = 75 GHz Copper 0.070 Ω/ standard TSV conductive materials Gold 0.085 Ω/ Aluminium 0.089 Ω/ Tungsten 0.129 Ω/ Cobalt 2.149 Ω/ ferromagnetic materials Nickel 3.933 Ω/ Iron 11.959 Ω/ Table 2.2: RF Sheet Resistance for different conductive materials at f = 75 GHz. 14
- 19. 2.3 Self-Assembly in Microtechnology 2.2.1 Skin Effect One reason for the frequency dependence of the conductivity in different materials lies in the so-called skin effect. This basically describes the fact that the flow of alternating electrical currents is confined to a small area close to the surface of the conductor. In and around the conductor, magnetic fields are produced which in turn induce spiralling currents that counteract the flow of the current at the centre of the conductor. The extents of this confinement to the area near the surface is strongly depen- dent on the frequency of the alternating current and can be quantitatively described by the skin depth δ. This metric value holds the depth from the conductor surface, at which the current density is reduced to 1/e which is approximately 0.37. In formula 2.1 the relation between the skin depth δ, the specific electric resistivity ρ, the angular frequency of the current ω, and the magnetic permeability µ is shown. δ = 2ρ ωµ (2.1) At the targeted signal frequency of 75 GHz the RF conductivity of nickel and gold differs significantly. Figure 2.2 reveals the values for the sheet resistance as 0.085 Ω/ for gold and 3.933 Ω/ for nickel. To make sure that the RF-capable TSV profits from the excellent conductivity properties of the gold, its layer thickness has to be big enough to properly restrict the current flow to the gold layer. In other words the gold layer has to be thicker than the skin depth of the signal. With equation 2.1 the skin depth of a signal at 75 GHz in gold can be calculated and it reveals the value 0.29 µm. Since the goal of this thesis is to fabricate TSVs that exhibit a broad-band RF capability, is was decided to set the thickness of the gold layer to 1.5 µm which provides a theoretical bandwidth down to 3 GHz. Even though the skin effect usually causes the overall resistivity to drop with increasing current frequency, in this case it works to our advantage. The outermost area of the conductive cores consist of a layer of gold and since the current is con- fined to the skin of the conductor almost all the current will flow in this gold layer. By utilizing the skin effect in this way, an excellent high-frequency conductibility can be reached and the disadvantages of the nickel core can be overcome. 2.3 Self-Assembly in Microtechnology In line with the previously mentioned trend towards heterogeneous integration for combined MEMS and IC devices arises the challenge to reliably and efficiently assemble these devices. The predominant method of assembly in the industry is robotic pick-and-place. This method, however, exhibits a few distinct disadvan- tages as it is based on a serial process, i.e. placement of the components happens one-by-one, and thus provides a limited potential for throughput. Moreover, it suf- fers from unfavourable properties for down-scaling of the device dimensions. These 15
- 20. 2 Background include sticktion problems, the fragility of the structures, and the sheer number of components which has a tendency to increase as the scale drops. The concept of self-assembly in a generic sense describes the autonomous or- ganisation of a number of components into ordered patterns or the spontaneous construction of a feature out of its constituent parts without human intervention [17]. Ultimately this means that the components organise themselves automat- ically and unguided by external manipulation to exact predetermined locations. But the real strength of self-assembly lies in the parallelisation, meaning that all components are being assembled simultaneously in stead of subsequently. Thus, a much higher throughput and efficiency than conventional pick-and-place can be achieved. Self-assembly methods for components ranging from milli- to nanoscale exist in various forms and are based on different physical principles. These are e.g. shape matching with the exploitation of the gravitational force [18, 19, 20], capillary effects [21, 22, 23], electric fields [24], and magnetic forces [25, 26]. While all of the mentioned principles possess unique fields of application and individual strengths and weaknesses, this work focusses on the utilisation of magnetic forces. A thorough review of other self-assembly technologies is given in [17]. Figure 2.3: Behaviour of nickel wires in a magnetic field: a) Approx. 300 straight nickel wires ( = 35 µm, = 350 µm) without an applied field. b) A magnetic field of 1.1 T is applied from below. The nickel wires stand perpendicular on the surface, as they align themselves along the field lines. Courtesy of A. C. Fischer, KTH Stockholm Self-assembly by magnetic force offers a very versatile range of applications and shows distinctive possibilities as well a s a few disadvantages. Namely, this method offers long-distance forces that are, other than e.g. electric fields, rela- tively insensitive to the surrounding medium and independent of surface chemistry. Furthermore, it exhibits a very high energy density and favourable down-scaling characteristics [27, 28]. Since magnetic force can act either attractive or repellent it offers a potent process control. In figure 2.3, an example of such a long-distance magnetic force effect is presented. A limitation of such applications, though, is that the components need to have permanent magnetic or ferromagnetic functionality in order to be manipulated. 16
- 21. 2.3 Self-Assembly in Microtechnology While very few of these methods have yet been successfully adapted for in- dustrial use, many concepts are being investigated. Examples are the assembly of magnetised nanopills directly into electronics chips using CoPt and nickel [25] or the combination of shape matching and magnetic assembly to align a large number of chips to predetermined positions on wafer scale using NdFeB magnets [29]. A further example is the programmable magnetic self-assembly of micro sized electric components with Ni anchors [30]. 2.3.1 Magnetic Assembly of TSV Conductor Material The concept of utilizing a contact-free magnetic self-assembly process to fabri- cate high aspect ratio void-free TSVs has been devised in previous work at the Microsystem Technology Lab at KTH [1]. Since this master thesis includes the automation of this process, this section provides an explanatory overview of this assembly process. Figure 2.4: Via assembly process: a) DRIE process to fabricate via holes b) mag- netic assembly of nickel wires into the via holes c) filling and curing of BCB that acts as an insulation layer between the via core and the substrate. Courtesy of A. C. Fischer, KTH Stockholm As the schematic depiction in figure 2.4 shows, the assembly process consists of three main steps. First, there is the formation of the via holes by DRIE etching. The etch is done through the entire height of the silicon substrate (350 µm) and stops at the back-side silicon oxide (see figure 2.4 a). Secondly, the magnetic assembly of the nickel conductors into the via holes is performed (see figure 2.4 b). By the application of a magnetic field from the back-side of the wafer, the conductor wires align themselves normal to the surface (compare figure 2.3) and can be assembled into the holes. Lastly, the gap between the sidewall of the via hole and the assembled conductor has to be filled with a dielectric material. Therefore BCB is applied in liquid form and cured on a vacuum hotplate to ensure a void-free enclosure of the nickel rods. 17
- 22. 2 Background This approach differs from state-of-the-art TSV metallisation processes in the order of the shown process steps. According to the industrial standard the met- allisation is performed by a gradual deposition of conductive material on top of a previously formed insulation layer. This novel concept, however, contains a re- versed process flow such that the insulation layer is applied after the formation and assembly of the conductive core. The above presented method incorporates both a great potential for an effective and reliable fabrication process as well as favourable via characteristics. The pre- fabricated metal cores are inherently void free and therefore ensure a good electrical connection through the substrate. Since the cores are made from nickel they possess ferromagnetic properties and can, therefore, be manipulated by magnetic fields. The developed filling process by magnetic assembly utilises this very property. The application of a magnetic field from the back-side of the wafer allows the nickel cores to be steered and positioned on the wafer surface. The magnetic field induces a force that pulls the cores towards the wafer and by moving the cores directly over the via holes the conductive cores are autonomously assembled into the holes. This method has been demonstrated by the MST lab at KTH. However, the shown process has been performed by manual means which results in a very un- reliable reproducibility. Moreover, the manual manipulation of the magnetic field by moving a small permanent magnet at the back of the wafer suffers from very bad precision and position control. The manual movement tends to be undefined and, therefore, causes a very unrepeatable filling rate which describes the number of wires that are assembled per minute. Although the presented manual attempts show a great potential for the magnetic assembly of nickel wires, it has never been achieved to reach 100% filling yield. The goal of this thesis is to address and solve aforesaid issues of the manual execution of the magnetic assembly and to automate this process step. The advan- tages of a robotic assembly setup, such as high precision and process repeatability, provide a well structured approach to an improvement and optimisation of the process. 18
- 23. Chapter 3 Design and Construction of the Assembly Tool The main task of this master thesis was the development of a fully automated wire assembly process for the fabrication of nickel TSVs. This process has to be capable of assembling the nickel wires on wafer level without losing the precision needed to fill micro-scale structures. To meet these demands, a specialized high precision robotics setup was designed and constructed. The following chapter presents said construction and explains how the assembly process was automated. 3.1 Wafer Handling & Assembly Stage The robotics and assembly setup within this project was designed after a list of requirements and specifications that had to be fulfilled. According to the indus- trial standard in the fabrication of MEMS devices, the assembly process and its components were designed for 200 mm wafers. Furthermore, it was devised as a cassette-to-cassette process, meaning that the robot had to be able to fetch the processing wafer out of a cassette, to carry out the assembly, and to put the wafer back into the cassette. To meet these requisites, a wafer handler robot of the IWH-series from Isel Robotik was chosen. As figure 3.1 shows, the wafer handler robot is equipped with two 200 mm wafer grippers at the end of the moving arm. This two-gripper config- uration allowed for the practical feature of giving the two ends different tasks. One end acted as wafer handler, placing and fetching wafers to and from the cassette, while the other end was used to build the assembly tool. Another key feature was the high precision of the movement. Positions in radial and vertical extension can be reached with a precision of 30 µm, while the rotational movement can be con- trolled down to 0.02◦. A comprehensive specification list for the selected robot is provided in appendix A.1. 19
- 24. 3 Design and Construction of the Assembly Tool Figure 3.1: Assembly Robot (ISEL IWH-series) with wafer handler gripper to the left, an LED-beam wafer scanner (Synx M-DW1) at the ”elbow“ joint in the front, and the custom built assembly arm to the right. The assembly arm consists of a permanent magnet mounted on an aluminium sheet and a camera above the magnet. The whole setup for the assembly process had to meet a number of requisites. First an assembly stage for 200 mm wafers had to be built that allows free access to both the back-side and the front-side of the wafer (see figure 3.2). On the assembly arm of the robot, a magnet is mounted in a way that it can reach under the wafer. Further, the feature of optical inspection on the front-side is needed in order to position the magnet and monitor the assembly. To provide these functionalities, an aluminium structure was built in a way that a camera can be mounted exactly on top of the magnet. The fork-like character of the aluminium structure permits lateral movement to reach every position of the wafer surface with the magnet. A schematic depiction of the functionality of said assembly arm is presented in figure 3.1, as well as a picture of the final configuration of the assembly robot. With this setup it is possible, first of all, to find via holes and other structures on the wafer. Secondly, the assembly arm can be positioned very accurately, and thirdly, the state of the assembly during a running process can be monitored. For this tool configuration a custom made table has been built so that the body of the wafer handler robot can be embedded and only the movable arm protrudes the tabletop. Around it, the cassette and assembly stages were positioned in a way that they can be reached by the robot arm. The final setup, as shown in figure 3.2, consists of the robot in the middle, a station for a 200 mm wafer cassette, and the assembly stage. While setting up the above shown robot installation, both of the stages sur- rounding the robot were carefully placed so that they face exactly radially towards the centre. The distance had to be adjusted to make them reachable by the robot arm and only then could the robot be taught the exact locations of the stations. With all the parameters set, the robot is then able to fetch any wafer from the 25 slot cassette and place it on the assembly stage and put it back in the cassette. In addition, this configuration allowed the assembly arm to position the magnet on every location under the wafer without hindrance. 20
- 25. 3.2 Automated Magnetic Assembly The the surface of the custom made aluminium table was deliberately designed to have spare areas, not used by the current assembly setup. The intention behind this decision is to provide enough room for future adaptation and extensions. The work towards the completion of this tool will most likely incorporate the addition of a second wafer cassette, a vacuum hotplate, and/or a wafer spin-coating station. Figure 3.2: The whole assembly setup with the robot arm in the centre of the table, the wafer cassette station and the assembly stage to its right. The assembly process consists of four steps: 1. scanning the cassette for wafers, 2. picking a chosen one and placing it on the assembly stage, 3. positioning the assembly arm and carrying out the magnetic assembly, 4. putting the wafer back into the cassette. 3.2 Automated Magnetic Assembly With the robotic setup completed and fully functional the task of developing a completely automated magnetic assembly process for the nickel via cores could be tackled. The performed work consisted of two main parts that were conducted in parallel. The first of these tasks was to ensure the communication between the robot and a computer in order to be able to send commands and receive data and status information. By these means the robot can be controlled from the computer, but to do this conveniently and also to enhance the controllability of the robot, a new control software was devised and implemented. The second task was to study the behaviour of the nickel cores under manip- ulation of magnetic fields. With this knowledge it was then possible to develop a movement strategy that ensures a reliable and fast assembly process for a large number of vias. 21
- 26. 3 Design and Construction of the Assembly Tool In order to test the capabilities of this assembly setup, arrays of 100 via holes were systematically filled. From these experiments, the filling rate as well as the filling yield could be extracted. The filling rate describes the number of wires that are assembled within a minute while the filling yield gives the percentage of holes that were filled in the overall process. Based on the observations the parameters of the movement of the magnet were iteratively adjusted to improve the assembly performance. 3.2.1 Robot Control Software A direct and customisable control over the wafer handler robot is crucial to this as- sembly setup. To be able to implement precisely executed assembly movements and to automate the process, a robot control software was created. The communication with the robot could be established over a serial connection. For the implemen- tation of the software LabVIEWTM from Natinal Instruments was chosen since it is well suited for the control of peripheral equipment via a serial connection. The robot was not equipped with any drivers or communication protocol of its own. Therefore, it was necessary to create a new interface for the communication. The basic principle of said interface consists of a three ASCII character long command string which is send to the robot. If the command is recognised and can be exe- cuted, the robot acknowledges it by sending a single ’>’. If the command is not recognised, the robot declines it with a ’?’. Upon the basis of this interface it is possible to implement a control software and to automate the assembly process. The demands, this software has to fulfil, span a number of different operations and functions. First of all, it has to provide the user with complete control over the robot which is achieved through a command line over which direct commands can be sent. The responses sent by the robot are then displayed in a log indicator (see figure 3.3). A list of the most frequently used commands is presented in appendix A.2. Secondly, a whole set of functions are required to carry out the wafer handling, such as scanning the wafer cassette and the stations for the presence of wafers, and placing or fetching single wafers to and from the different stations. For the assembly process itself the tool has to provide means of precisely con- trolling the assembly arm and setting the parameters that define the assembly movement. The first requirement was met with an x-y-movement control at a pre- cision down to 30 µm. Furthermore the complete parameter set for the assembly movement was made customisable through slide controls for speed, acceleration, and jerk in all three dimensions. Lastly, it has to provide a way of displaying the visual feedback from the camera, mounted on top of the magnet. The whole user interface of this software, as shown in figure 3.3, consists of a multitude of small frames. Each one of these frames includes one of the elementary functions needed for the operation of the assembly robot. The presented software was implemented in parallel to the filling test and evolved throughout the process of optimising the assembly. New functionalities were added as the need arose and different movement patterns and parameter sets were implemented based on the gained knowledge from preceding test iterations. 22
- 27. 3.2 Automated Magnetic Assembly Figure 3.3: User interface of the robot control software. It includes all necessary functions for the operation of the assembly tool, such as sending robot commands (including a response log), wafer handling operations, positioning of the assembly arm, setting the assembly movement parameters, and a visual inspection. 3.2.2 Movement Trajectories Since the previously conducted experiments of the magnetic assembly were carried out by hand, almost no knowledge about movement strategies could be acquired from those. The manual manipulation of the magnetic field has proven to be very difficult to control in a precise way, resulting in fairly erratic movement patterns. The encountered problems are very unstable filling rates, the difficulty to repro- duce the experiments, and unsatisfying yield. No experiment succeeded in filling a complete array of via holes. 23
- 28. 3 Design and Construction of the Assembly Tool The transition from manual to robotic assembly resolves a number of those issues intrinsically. The high precision of the robot eradicates the controllability issues that dominated the manual approach. Since the movements of the robot arm are programmed and executed in a computer-controlled way, a perfect repeatability is an inherent property of the process. With these prerequisites it was possible to conduct a systematic approach to find an efficient and reliable filling strategy. Figure 3.4: For the filling experiment a TSV array chip, consisting of 10 × 10 via holes ( = 42 µm, depth = 350 µm), was placed in a milled recess to hold it in place during the assembly. For these experiments chips with TSV hole arrays were fabricated (see chapter 4 for detailed information) and placed in a custom made chip carrier substrate, as shown in figure 3.4. It was milled out of a 0.6 mm thick printed circuit board (PCB) sheet. The reason for carrying out these experiments on chip level and not on wafer level, for which the process was designed for, lay in the arrangement of via arrays on the wafer. According to the space-efficient design, the array structures were fabricated right next to each other on the wafer, making it impossible to access a single array. Therefore, the wafer was diced to test the assembly on single array chips. The experiments were conducted with approximately 3000 wires per chip. This large amount of excess wires is necessary to ensure a fast assembly. The first and most basic pattern implemented and tested was a small square with an edge length of d = 0.76 mm. Since it was not possible to cover the whole area of the test array with this pattern, it was altered slightly, to correct this. The new movement still followed the same rectangles but advanced 0.5 mm after each turn. In figure 3.5 a) a schematic depiction of said trajectory is shown. Note that the size of the magnet is almost as big as the array, so that even with this small scale movement, the whole chip area could be covered. The filling rate was relatively poor, as it took more than two minutes to fill 80% of the array. Since even after 200 seconds of movement of the magnet this experiment could not reach 100% yield, the reliability is insufficient as well. The detailed progress and data sets of this experiment can be found in figure 3.6 and appendix B. The knowledge acquired from this first automated assembly experiment is re- lated to observations of the motional behaviour of the nickel rods. For very short movements, such as the small rectangles from trajectory a) in figure 3.5, the ma- noeuvrability of the wires gets very limited and imprecise. Many wires on top of 24
- 29. 3.2 Automated Magnetic Assembly Figure 3.5: Robotic assembly trajectories: a) Small advancing rectangles with an edge length of d = 0.76 mm. b) Large spline movement of approx. d = 1.5 cm width. the wafer do not follow these small movements of the magnet. Instead they just remain in place. The reason for this behaviour can be explained by the fact that the gradient in the magnetic field, generated by the displacement of the magnet, does not suffice to introduce a lateral force that is strong enough to overcome the friction between the nickel rods and the wafer surface. Only when the magnet is moved over a large distance and the gradient in magnetic field gets high enough, the wires follow the movement of the magnet and relocate themselves on top of the magnet. The conclusion from the first experiment was then incorporated in a second iteration. The small scale movements of the magnet were replaced by larger move- ments of about d = 1.5 cm, as shown in figure 3.5 b). The advancing movement (upwards in figure 3.5 b) was maintained the same so that the magnet shifted half a millimetre after every back and forth sweep over the chip. The improvement of performance was significant, as depicted in figure 3.6. An 80% filling ratio could be reached after just one minute. Hence the new pattern exhibited a filling rate that was more than twice as fast as compared to the first experiment. For the next iteration of filling experiments the influence of the velocity of the assembly motion was investigated. The preceding filling experiments were conducted at an angular velocity of 120◦/s and a radial velocity of 22.9 cm/s. At these speeds, it was observed that the nickel rods follow the movement of the magnet with a slight delay which results in a small lateral offset. The nickel rods that follow a bit off-centred are tilted away from the magnet since the magnetic field lines are not normal to the wafer surface at the edges of the magnet. This, 25
- 30. 3 Design and Construction of the Assembly Tool Figure 3.6: Filling rates for the assembly of via arrays (10 × 10 holes). Two different movement patterns and two different speeds were tested. The slow spline pattern exhibited a yield of 100% and the highest filling rate. See appendix B for complete data. in turn, hampers the filling rate of the assembly process. With this effect in mind, the speed of the magnet was reduced to 4◦/s and 10.2 cm/s. The pattern was not changed in order to see the impact of the velocity of the movement in these experiments. As expected, the decrease of speed resulted in a higher filling rate. Further- more, the assembly process reached a filling yield of 100%. Thus, making it both the fastest and most reliable strategy that was evaluated. In order to verify the reliability of the results, the experiment was repeated. Also the second experiment reached a yield of 100% and exhibited an even higher filling rate. The progress of these two filling experiments is depicted by triangular and round data points in figure 3.6 and an extensive list of the measurement data is presented in appendix B. 3.3 Discussion and possible Improvements The focus of preceding sections lies on the assembly robotics, showing the design and construction of the assembly setup, the development of a control software, as well as the attainment of an effective and reliable movement strategy for the mag- net. The final process exhibited an outstanding performance with very fast wafer handling operations, well controllable and precise alignment functionalities, and a very successful magnetic assembly of the nickel wires. In the course of developing said process, many hampering effects and other issues have been observed. A few possible improvements are proposed for future projects and continuative research. 26
- 31. 3.3 Discussion and possible Improvements One encountered problem is related to the pre-fabrication process of the nickel rods. The cutting process, which is explained in more detail in section 4.1.2, leaves the rods with an edge on both ends (see figure 4.2 f). In some cases, this edge enlarges the diameter of the rods to such an extent that they do not fit into the via holes any longer. In other cases, they act like hooks that partially hinder the rod from falling into the via hole. Additionally it lets the rods cling to one another. The evident solution to this problem is the removal of said edge which can be achieved either through adjusting the cutting process to minimise the formation of edges or through shortly immersing the cut wires in nickel etch to remove the edges. Another observed effect is that sometimes the nickel rods do not fall all the way down into the hole but get stuck in a tilted position half way in. The appearance of this effect is partly caused by the roughness of the sidewalls but mainly by the aforementioned edge at the ends of the nickel wires. An elimination of these edges will most likely solve this problem. Another proposed approach is to introduce a shaking step during or after the magnetic assembly to guide the rods into an upright position. The most severe problem of the assembly process, though, is caused by the ferromagnetic properties of nickel. When exposed to a magnetic field, the nickel rods gets magnetized and act as magnets themselves. The wires are therefore not only attracted by the permanent magnet below the wafer but also by one another. This causes the rods to stack on top of each other and gather in big clusters. The clustering effect often hinders single wires to fall into a via hole and, additionally, many wires magnetically stick to already assembled wires. The only way to demag- netize the nickel rods is to apply a magnetic field in the opposite direction. The ideal solution to this problem would be to exchange the permanent magnet with an electromagnet and apply an alternating magnetic field that would not allow the rods to be fully magnetized. However, no commercially available electromagnet that provides a sufficiently strong field to manipulate the wires could be found. As a compromise solution, a permanent magnet could be mounted rotatable on the assembly arm and turned upside down every few movement revolutions. This reversal of the magnetisation will dissolve the clusters momentarily while the wires would be magnetized in the opposite direction. In order to perform the assembly on chip level, a special chip holder has been fabricated to hold the chips in place. From the milling process there are inevitable gaps between the chip and the recess, as shown in figure 3.4. While dragging the nickel wires over the array, naturally, many of these wires are caught in this gap, thereby diminishing the number of wires that are actually carried over to the chip. The loss of these rods directly affects the filling efficiency of the experiments. Therefore, when observing the results presented in figure 3.6 and appendix B, these shortcomings have to be considered since the elimination of this issue would result in a further increased performance of the assembly process. 27
- 32. Chapter 4 Fabrication of RF-capable TSVs The preceding chapter focused on the assembly of nickel wires into the via holes and the robotic setup which was constructed to autonomously carry out said process. However, the fabrication of functional RF-capable TSVs comprises a whole set of process steps that have not yet been discussed. Therefore, this chapter gives a detailed overview of the entire manufacturing process of a TSV test structure; from the plain silicon wafer to the functional device chip. 4.1 Wire Preparation The major novelty of this TSV technology lies in its conductive core. The approach to the metallisation step by assembling pre-fabricated metal cores into the via holes differs from all other developed technologies to date. Fabrication wise, this expresses itself in a reversed fabrication process since the assembly of the metal cores is performed prior to the application of the insulation layer. It also allows for a well-controlled manufacturing process of the cores, making it possible to modify its properties to ensure the best possible electrical performance. Figure 4.1: The TSV metal conductors were pre-fabricated by deposition of a gold layer of 1.5 µm on top of a 35 µm thick nickel wire. This picture shows an early gold plating attempt with a gold layer of approx. 5 µm. 28
- 33. 4.1 Wire Preparation Nickel was chosen as conductive material for the cores for its ferromagnetic properties. Since nickel is commercially available in form of wires with diameters down to 10 µm, there is a cost-efficient supply of core resources available. The pre- fabrication of nickel cores consists of the deposition of gold on its circumference and the cutting process to manufacture single rods out of long wires. These process steps are described in the following sub-sections. 4.1.1 Gold Plating As discussed in section 2.2, a good RF performance can be achieved by depositing a gold layer on top of the nickel cores. The specifications suitable for broad band RF capability dictate a gold layer thickness of 1.5 µm. Furthermore, the gold layer thickness has to be uniform around the wire which puts a very high demand on the depositioning process. As shown in previous research [31], electroplating is suited for the deposition of metals on wire surfaces with micro scale diameters. In contrast to electroless gold plating, electroplating shows a good process controllability and a high plating rate. In figure 4.1, the result of this plating process is shown. An ion beam milled recess in the wire reveals the thickness and the uniformity of the gold layer. Figure 4.2: Wire cutting: After the gold plating (a), the nickel wire are transferred to a dummy wafer (b) and then spin-coated with photoresist (c). Embedded in this protective layer of photoresist, the wires can be cut with a dicing tool (d), without the risk of bending the wires. (e) shows the top and cross-sectional views of a cut nickel wire, still embedded in photoresist. By dissolving the resist layer the wires can then be released. (f) shows a single cut wire with clearly visible edges from the cutting process (as discussed in 3.3). 29
- 34. 4 Fabrication of RF-capable TSVs To be able to plate a long piece of wire in one step, a special frame was designed and milled, as figure 4.2 a) shows. A 2.5 metre long nickel wire was mounted on said frame. Hence, one single plating process step delivered the supply of gold plated nickel wire for over 4000 metal cores. 4.1.2 Wire Cutting The transition from a long gold plated nickel wire to single rods, ready to be assembled into via holes, is the last procedure of the pre-fabrication of via cores. This step was achieved by utilising a wafer dicing tool to mechanically cut the wires into 350 µm long pieces. To do so required special preparations since it was crucial that the cutting action did not bend or distort the wires in any way, and thus, rendering them incapable of fitting into the via holes. Therefore, the wires are fixed on a dummy wafer and covered by a layer of photoresist prior to the cutting, as shown in figure 4.2 steps b) and c). The central opening in the frame (figure 4.2 a), was purposefully designed for a 100 mm wafer to fit through which enabled a direct and practical transition of the wires from the frame to the dummy wafer. By dicing the wafer surface perpendicular to the wires and with the high precision of the dicing tool, nickel rods with a well defined length and straight ends can be fabricated. As figures 4.2 d) and e) show, the cuts are just deep enough to separate the rods, while only cutting slightly in the underlying dummy wafer in the process. During the cutting itself, the wires are protected and held in place by the photoresist which can be dissolved with acetone afterwards. Thus, perfectly straight plated nickel rods that are ready for the assembly are released. The end result of this cutting process is presented in figure 4.2 f). 4.2 Etching the Via Holes At the very start of the via fabrication process the type of silicon wafer had to be chosen. Since the application of this TSV technology is targeted at high-frequency signal transmission, it was crucial to use a silicon substrate which would introduce very low losses to the system. The most important property of such a substrate is a high resistivity. This property hampers the coupling of close conductors and reduces transmission losses in the substrate. According to these prerequisites, a 100 mm diameter, 350 µm thick, high resistivity silicon substrate was chosen. The complete substrate specifications are shown in appendix C.1. Once the wafer was chosen, the next step was to fabricate the via holes. There was enough space on the chosen 100 mm wafer to place multiple TSV structures. Therefore, different test arrays as well as RF test structures could be fabricated on one wafer surface. The design for the etched structures contained two different array configurations, one with a narrow pitch and one with a wider pitch. Further, four different RF test structure were designed (see section 4.5 for details). In figure 4.3, the process flow of the TSV fabrication is shown with steps a) to d) depicting the formation of the via holes. Starting at 4.3 a) with a double-side polished 350 µm thick wafer with layers of 2 µm thick thermal silicon oxide on both 30
- 35. 4.3 Magnetic Assembly Figure 4.3: The TSV fabrication in three main steps: (a – d) Formation of via holes by DRIE etching. (e – h) Autonomous magnetic assembly of gold coated nickel TSV cores and the application of BCB as an insulation layer. (i – k) Fabrication of the via contacts and transmission lines. Courtesy of A. C. Fischer, KTH Stockholm sides, standard lithography is used to define the openings for the etching process. By RIE (Reactive Ion Etching) the front-side silicon is etched which then acted as a hard mask for the silicon etching step, as shown in figure 4.3 b). The high requirements that the etching of 350 µm deep and straight holes imposes were met by DRIE (Deep Reactive Ion Etching), as depicted in figure 4.3 c). Finally, figure 4.3 d) shows a thermal wet oxidation step to cover the via sidewalls with a 1 µm thick silicon oxide layer. For most TSV fabrication processes the smoothness of the sidewalls of the via holes is a crucial factor for the processibility as well as the electrical performance. Rough sidewalls provide a very difficult basis for the deposition of the core material, e.g. by electroplating of copper. To minimise the formation of rough sidewalls, the DRIE process has to be carried out at lower power which, in turn, prolongs the process time. For this project, however, the texture of the sidewalls is not critical since neither the metal core nor the dielectric are dependent on a depositioning procedure. As a result, the DRIE step can be operated at high power which decreases the process time of the etching step and, thereby, results in a higher throughput for the fabrication of the TSVs. 4.3 Magnetic Assembly With the formation of via holes and the pre-fabrication of the metal cores com- pleted, the magnetic assembly can now be carried out. Since the metal cores consist of nickel rods that are plated with gold, they possess both ferromagnetic properties as well as excellent RF conductibility. This makes it possible to utilise magnetic assembly to fill the vias, while not compromising the RF capability. The entire assembly of the TSV structures on the wafer was carried out by the automated as- sembly process, as described in chapter 3. To ensure a good process performance, 31
- 36. 4 Fabrication of RF-capable TSVs an excess amount of wires was deposited on top of the wafer, as shown in figure 4.3 e). The application of a magnetic field from below the wafer causes the wires to erect themselves perpendicular to the surface, as depicted in figure 4.3 f). Com- puter controlled and completely autonomous, robotic movements of the magnet then drag the metal rods into the via holes (figure 4.3 g). 4.4 Insulation Layer The second part of the fabrication process is completed by the application of the in- sulation layer. With the metal cores already in place, the insulating material is ap- plied in liquid form rather than deposited (e.g. CVD), as it is most commonly done in industrial applications. The challenge of this process step, therefore, presents itself in the application of liquid polymer into the just 2 µm wide gap between the metal core and the sidewalls of the substrate (figure 4.3 h). Subsequently, the polymer is hard-cured and the excess BCB on top of the wafer is removed by a grinding step to uncover the metal rods for the electrical contacting of the vias. 4.4.1 BCB Filling and Curing The utilisation of organic dielectrics, such as BCB, provides three main features to the TSV technology. Firstly, the BCB has to insure the total electrical insulation of the metal core from the silicon substrate. The other two features are on the one hand, the low k-values of the polymer which lowers the coupling to the substrate and hence provides superior electrical characteristics. And on the ohter hand, due to the low Young’s modulus, the polymer layer acts as a buffer for thermo- mechanical stresses induced by CTE mismatch [1]. For these three features to take full effect it is crucial that the BCB layer is void-free. In order to achieve this, special measures are taken. First of all, there is the oxidation step, d) in figure 4.3. After the DRIE process, the sidewalls of the via holes are covered with a thin passivation layer of C4F8 which shows teflon- like, hydrophobic properties that would prevent BCB from entering the gap. The subsequent oxidation process removes this passivation layer from the sidewalls and leaves a hydrophilic SiO2 surface that, together with the hydrophilic wire surface, creates a capillary effect that guides the BCB into the gap. To further aid the filling process, the wafer was heated to 60 ◦C to lower the viscosity of the polymer. After the manual application of BCB onto the TSV structures, the hard-curing of the polymer can be conducted. The full polymerisation of BCB is then per- formed by a temperature ramping cycle, according to the manufacturer’s standard procedure (for details see appendix C.2). In order to achieve a total void-free insu- lation layer, the entire curing process is carried out in a vacuum chamber at 0.02 mbar. 32
- 37. 4.5 Front- and Back-side Metallisation 4.4.2 Grinding To prepare the wafer for the formation of via contacts, the excess of hard-cured BCB that inevitably covers the front-side of the TSV structures has to be removed. As figure 4.3 h) shows, not only the excess BCB has to be removed but also the protruding metal rods have to be levelled with the silicon oxide layer. The critical factor about this process is the requirement to stop the grinding exactly at the silicon oxide layer which has a thickness of only 2 µm. Since industrial grinding processes are not designed for materials such as BCB and Nickel, the planarisation was carried out manually. A soft grinding stone was utilised to work through the nickel and BCB. Since the hardness of this grinding stone is lower than that of silicon oxide, the grinding process automatically stopps when the oxide layer is reached. Nevertheless, a cautious approach to the grinding process is necessary. Even though the grinding stone is unable to grind through silicon oxide, it is still hard enough to scratch the surface of the wafer. For the consecutive fabrication steps to form the metal connections and transmission lines, smooth surfaces are a crucial requirement for a good RF performance. 4.5 Front- and Back-side Metallisation The third and last part of the TSV fabrication comprises of the metallisation of the front- and the back-side of the wafer. This concluding step contains the functionalisation of the TSV interconnections. The separated connectors through the silicon substrate are transformed into connected, functional structures. While the array structures only need a simple connection to the front- and back-side, the RF test structures need more elaborate treatment. Different designs of transmission lines with various lengths and different via numbers have to be fabricated. Each line connects two TSV feed-throughs to form a transmission line that runs both on the front- and the back-side of the wafer. 4.5.1 Fabrication The metallisation comprises three process steps that transmute the planarised wafer, as shown in figure 4.3 i), into the final device. Since high conductibility of the metallisation material is vital for a good RF performance, the transmission lines are made of gold. Before the gold can be deposited on the TSV structures both ends of the via interconnections have to be exposed. As figure 4.3 i) show, the front-side of the vias is opened up by the grinding process but the back-side is still covered by a layer of silicon oxide, as well as BCB. Therefore, as depicted in figure 4.3 j), both the silicon oxide and the BCB are etched through which is achieved by RIE. Thereafter, the gold metallisation process on both sides of the wafer is carried out. In order to enhance the adhesion of the gold layer to the wafer surface, an intermediate layer of 50 nm titanium tungsten is applied prior to the gold deposi- tion. The thickness of the gold layer was chosen to be 1 µm which is significantly 33
- 38. 4 Fabrication of RF-capable TSVs higher than the signal’s skin depth of 0.3 µm to provide a good RF conductibility. The gold, which is distributed over the entire area of the wafer, has to be structured and functionalised. In order to form the transmission lines, the front- and the back-side are subsequently patterned with standard lithography. Thereby, a mask for the gold etching is created which then protects the gold from the etchant in designated areas. In figure 4.3 k) the end result is depicted, showing RF TSVs connected to gold transmission lines on the front- and back-side of the wafer. 4.5.2 RF Test Structure Design In order to evaluate the capability for high-frequency signal transmission of this novel type of TSV, different test structures have been designed. Their fabrication was carried out according to the metallisation process, explained in detail in the preceding sections. The functionality and design of these structures is presented in this section. The main purpose of RF-capable TSVs lies in the transportation of high- frequency signals from one side of the wafer to the other. To achieve this functional- ity, a conductor on the front-side is contacted to the top end of an RF capable TSV, while the other end of the TSV is connected to a back-side conductor. In plane, i.e. on the wafer surfaces, the conductance of these signals is achieved through micro strip transmission lines. In figure 4.4 a), both a cross-sectional view and a top view of such a transmission line and the connecting TSV feed-throughs is shown. The top view reveals the configuration of the transmission line which consists of a central connector, the so-called signal trace, and two broader ground traces on either side. This configuration is referred to as ground-surrounded microstrip line. In order to be able to measure the signal transmission over such a structure, both ends of the line have to be on the front-side of the wafer. This means that two sets of feed-throughs have to be incorporated in every path of the test structure. The transmission lines on the front-side only serve the purpose of contact pads for the measurement probes and therefore are just 350 µm long. Whereas, the majority of the signal path runs on the back-side, whose length is referred to as t (see figures 4.4 (a) and 4.5). All test structures have to follow this basic scheme in order to fulfil the func- tionality and provide a measurable result. Four different designs of test structures were devised and fabricated. As shown in figure 4.4 b), the four different config- urations possess varying numbers of TSVs per feed-through and different widths of the signal trace. The full design specifications are presented in table 4.1. Addi- tionally, a transmission line matching the design of each configuration but without any TSVs was fabricated as a reference basis to the RF measurements. The most critical aspect to be considered for high-frequency measurement is to ensure that the read-out of the measured parameter is not dominated by noise and distortion, introduced by parasitic effects. The first measure, that was taken to reduce parasitic effects, was the careful choice of the wafer substrate material and the utilisation of gold as conductive material for the transmission lines. While the 34
- 39. 4.5 Front- and Back-side Metallisation Figure 4.4: Transmission line with RF TSVs: a) Cross-sectional and top view schematic of a transmission line with two incorporated TSV feed-throughs. b) Four different configurations of the RF feet-throughs are shown as well as a reference transmission line without TSVs. Design no. Width of the Width of the No. of TSVs signal trace ground trace per feed-through 1 60 µm 250 µm 3 2 120 µm 250 µm 3 3 120 µm 250 µm 4 4 120 µm 250 µm 8 Table 4.1: Design specifications for the different TSV configurations. selection of material has a big influence on the losses and hence the performance, it is often the measurement setup itself that introduces severe parasitic effects. These effects increase inversely with the feature size of the sample. One example of such a parasitic effect is the electrical coupling between the measurement probes themselves which occurs when they are placed too close to each other. In order to prevent this, the probes should be as far away from each other as possible which would result in a very big t. The losses of a transmission line, however, are proportional to its length and, thus, propose a contradictory trend towards short signal paths. In order to get the best results possible from the measurement setup, the length of the back-side transmission line t was designed in different variations. The overall configuration of the transmission lines of the test structure is shown in figure 4.5. 35
- 40. 4 Fabrication of RF-capable TSVs Figure 4.5: Transmission line design of the RF test structures and the reference structures. Different lengths t (see table 4.2) were fabricated to deal with field coupling effects. Transmission line no. Length t 1 300 µm 2 600 µm 3 1200 µm 4 2400 µm 5 4800 µm 6 9600 µm Table 4.2: Different lengths t of the back-side transmission line. For each of the four designs depicted in figure 4.4, a total of six transmission lines of increasing length were fabricated. In table 4.2 the exact lengths of the six different transmission lines are given. By measuring the signal transmission over these different distances, it is possible to identify the distortion, introduced by the field coupling, and extract the veracious information from the measured value. 36
- 41. Chapter 5 Conclusion This master thesis presents both the improvement of a new TSV technology as well as the design and construction of an assembly tool which incorporates an autonomous self-assembly process step for nickel-based via cores. A strong focus lies thereby on the investigation of the interaction of an applied magnetic field and the nickel rods. Although self-assembly technology is being explored in contemporary research (e.g [25, 29]), there is a very low number of such processes that were successfully transferred to an industrial application. The gap separating the two domains is very wide which is partly due to the lack of a comprehensive work on simulation and modelling in this field [17]. Naturally, the development methods and the fabrication restrictions of indus- trial applications differ from those in an academic research environment, such as the MST lab at KTH Stockholm. Attributes such as the implementation of non- standard materials or the throughput of the fabrication process generally are of minor significance in research, whereas in an industrial background these factors are ultimately decisive for the realisation or dismissal of novel technologies. A fur- ther aspect, which is important for industrial application, is the cost-effectiveness of the overall fabrication process, low material expenses, and available infrastructure. Typically, in an academic environment it is not feasible to develop a novel tech- nology that already fulfils all the criteria relevant for industrial uses. However, the closer a research project gets to these requirements the more realistic is the crossover to industrial application. Because of its nature, this project manages to propose not only a novel TSV technology but also a fabrication process that incor- porates many close to industry-ready attributes. Thus, this project provides not only the proof of concept but also works towards the development of an automated fabrication tool. This approach allowes e.g. for the implementation of a highly par- allelised self-assembly process of TSV cores with a high throughput. Furthermore, only commercially available material resources are utilised such as BCB and nickel wires to ensure a cost-effective fabrication. 37
- 42. 5 Conclusion 5.1 Project Summary In the beginning of this project, the scope of this master thesis work was determined and specific goals were formulated. In the course of six months, the presented work has been performed in pursuit of said goals. This section is therefore dedicated to summarise the performed work and to evaluate the achievements this thesis aimed for. The basis for this project was laid by preceding research, conducted at the Mi- crosystem Technology Lab of the KTH Royal Institute of Technology in Stockholm [1]. In said work, the utilisation of pre-fabricated nickel rods as conductive via cores which are magnetically assembled into the via holes is proposed. A proof of concept of this novel approach was provided by a TSV filling test, executed by an entirely manual process. As this process suffers from low controllability and repeatability, it was the task of this project to devise and realise a reliable and fully automated assembly process step. As elaborated in chapter 3, a robotic assembly tool was designed and con- structed to set the foundation for a fully autonomous TSV fabrication tool. The construction of said tool contained the incorporation of the high-precision wafer handler robot ISEL IWH-series as well as a considerable amount of custom-built tools and structures. Furthermore, the development of said tool also contained the implementation of a communication interface between a computer and the robot as well as the programming of a control software for the assembly process. Thus equipped, the resulting tool provides excellent controllability through the control software and it is able to execute the magnetic assembly process as an automated cassette-to-cassette process. A special focus was laid on the investigation of the behaviour of nickel rods under the influence of a moving magnetic field. The gained knowledge was then applied to the assembly process by an iterative optimisation of the movement parameters. As shown in figure 3.6, it was, thus, accomplished to devise a trajectory which ensures a repeated yield of 100% at a measured filling rate of 100 wires per minute. Furthermore, the parallelised nature of this process favours the assembly of large numbers of wires, as it would for example not take 10 seconds to assemble 1000 wires. Moreover, a second task of this project was defined and initiated. Based upon the TSV technology presented in [1], a novel approach to the pre-fabrication of nickel conductors was to be devised in order to provide RF capabilities for TSVs fabricated with this technology. While nickel possesses ferromagnetic properties and is therefore well suited for magnetic self-assembly, its high-frequency signal transmission properties, i.e. RF conductibility, are very poor, as indicated in fig- ure 2.2. Non-ferromagnetic materials, e.g. gold, exhibit significantly better RF conductibility. To improve the conductivity of the given concept of TSVs, a layer of gold was applied to the perimeter of the nickel conductors. This addition of a highly conductive material as an outer layer allowed for an excellent utilisation of the skin effect which causes electric current to flow just below the surface of a 38
- 43. 5.2 Outlook conductor. In the course of this work a fabrication procedure for this novel type of RF-capable TSVs was established (see figure 4.2). It contained the calibration of the gold plating process as well as the incorporation of the wire cutting step. For the plating process a special carrier frame for the nickel wire was manufactured, as shown in figure 4.2 a). Combining the achievements of these two main project tasks provided the means to fabricate RF test structures. The design of said test structures consists of various configurations of micro strip transmission lines with integrated TSVs along their paths. They were devised to characterise the RF capability of this new TSV technology. Due to long processing tool downtime and limited accessibility of these tools, the fabrication of said test structures was delayed to such an extent that is was not possible to conduct the RF measurements within of this thesis work. It was especially the gold plating process and the BCB grinding step which proved difficult to conduct and thus consumed more time than expected. 5.2 Outlook Even though this project has been successfully conducted and the formulated goals have been achieved, there is still room for consecutive research. The most imminent continuation of this work is the completion of the RF measurements. In order to characterise the performance of the improved RF capable TSVs, they have to be measured thoroughly and compared to nickel TSVs without gold deposition. Additional potential for continuation and improvement lies in the magnetic assembly process itself. Within this work, a very reliable and considerably fast process has been developed. Nevertheless, with further investigation of the move- ment of the nickel rods even higher filling rates could be achieved. The excellent controllability of the process through the control software provides the possibility of systematic optimisation of the motion parameters. In addition, the assembly process can be improved further by the implementation of an optical inspection feedback. The camera, mounted on the assembly arm, already now allows the monitoring of the assembly process. By the utilisation of pattern recognition, the software can be extended to be able to identify filled and empty holes. This infor- mations can then be used to implement a feedback loop for the assembly movement. Thus, an adaptive optimisation of the assembly movement during operation can be obtained. Moreover, this addition would provide the assembly process with an inherent quality control functionality, since unfilled holes can be detected. Furthermore, the nickel wires showed a tendency to be assembled in a tilted position or to get stuck in the hole. Therefore, some of these nickel wires did not fall all the way down to the bottom of the hole. Suggested measures to improve the assembly are firstly, the removal of the edge at the end of the wires, left by the wire cutting process (see figure 4.2 f). This would allow the wires to fall into the via holes more easily. And secondly, the exposure of the wafer to a vibration step is suggested to ensure a straight and concentric alignment of the conductor rods in the via holes. One possible realisation of this new functionality is the integration 39
- 44. 5 Conclusion of the vibration motion in the assembly stage. Alternatively, the vibration step could be executed during the BCB filling process. The constructed assembly tool was specifically devised with the intention of future continuation and completion. The layout of the tool was designed to allow the implementation of many additional stages and functionalities. Such a possible addition is for example a BCB spin-coating station to deposit an evenly distributed thin layer of BCB on the wafer. To complete the formation of the dielectric layer between the metal core and the silicon substrate, a vacuum hotplate could also be designed and constructed for this fabrication tool. The wafer handler robot provides the means to transport single wafers from the cassette to different stations, from station to station, and finally back into the cassette again. Thus, further automated fabrication processes and operations can be added, while maintaining the properties of an autonomous cassette-to-cassette tool. 40
- 45. Acknowledgement This master thesis work has been performed in the research environment of MST lab, KTH Stockholm. It was, therefore, the competent collaboration and support from many different members of the MST research group that enabled the success- ful completion of this project, a few of which shall be mentioned more specifically for their contribution and help: Andreas Fischer, Ph.D. student MST, for his solution oriented, knowledgeable ad- vice and his genial and supporting daily supervision. Kjell Nor´en, research engineer MST, without whose help and expertise the con- struction of the assembly setup would not have been possible. Niklas Sandstr¨om, Ph.D. student MST, for his help in operating the milling ma- chine. 41
- 46. Bibliography [1] A. C. Fischer, N. Roxhed, T. Haraldsson, N. Heinig, G. Stemme, and F. Niklaus, “Fabrication of high aspect ratio through silicon vias (TSVs) by magnetic assembly of nickel wires,” proc. MEMS, pp. 37–40, Jan. 2011. [2] W. Arden, M. Brillou¨et, P. Cogez, M. Graef, B. Huizing, and R. Mahnkopf, “More than Moore,” ITRS White Paper, 2009. [3] Y. Development, “3D TSV Integration Webinar Presentation,” 2010. [4] M. Motoyoshi, “Through-Silicon Via (TSV),” proc. IEEE, vol. 97, pp. 43–48, Jan. 2009. [5] D. S. Tezcan, K. De Munck, N. Pham, O. Luhn, A. Aarts, P. De Moor, K. Baert, and C. Van Hoof, “Development of vertical and tapered via etch for 3D through wafer interconnect technology,” proc. EPTC, pp. 22–28, Dec. 2006. [6] P. Nilsson, A. Ljunggren, R. Thorslund, M. Hagstrom, and V. Lindskog, “Novel through-silicon via technique for 2d/3d SiP and interposer in low- resistance applications,” proc. ECTC, pp. 1796–1801, May 2009. [7] M. J. Wolf, T. Dretschkow, B. Wunderle, N. Jurgensen, G. Engelmann, O. Ehrmann, A. Uhlig, B. Michel, and H. Reichl, “High aspect ratio TSV copper filling with different seed layers,” proc. ECTC, pp. 563–570, May 2008. [8] M. Rimskog, “Through Wafer Via Technology for MEMS and 3D Integration,” proc. IEMT, pp. 286–289, Oct. 2007. [9] D. S. Tezcan, F. Duval, H. Philipsen, O. Luhn, P. Soussan, and B. Swinnen, “Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging,” proc. ECTC, pp. 1159–1164, May 2009. [10] S. W. Ho, S. W. Yoon, Q. Zhou, K. Pasad, V. Kripesh, and J. H. Lau, “High RF performance TSV silicon carrier for high frequency application,” proc. ECTC, pp. 1946–1952, May 2008. [11] D. S. Tezcan, N. Pham, B. Majeed, P. De Moor, W. Ruythooren, and K. Baert, “Sloped Through Wafer Vias for 3D Wafer Level Packaging,” proc. ECTC, pp. 643–647, May 2007. 42
- 47. BIBLIOGRAPHY [12] P. Garrou, C. Bower, and P. Ramm, Handbook of 3D Integration Technology and Application of 3D Integration Circuits. Wiley, KGaA, 2008. [13] M. Koyanagi, T. Fukushima, and T. Tanaka, “High-Density Through Silicon Vias for 3-D LSIs,” proc. IEEE, vol. 97, pp. 49–59, Jan. 2009. [14] A. C. Fischer, N. Roxhed, G. Stemme, and F. Niklaus, “Low-cost through silicon vias (TSVs) with wire-bonded metal cores and low capacitive substrate- coupling,” proc. MEMS, pp. 480–483, Jan. 2010. [15] K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, “Thermo- mechanical reliability of 3-D ICs containing through silicon vias,” proc. ECTC, pp. 630–634, May 2009. [16] J. Gu, W. T. Pike, and W. J. Karl, “A novel vertical solder pump structure for through-wafer interconnects,” proc. MEMS, pp. 500–503, Jan. 2010. [17] M. Mastrangeli, S. Abbasi, C. Varel, C. Van Hoof, J. P. Celis, and K. F. B¨ohringer, “Self-assembly from milli- to nanoscales: methods and applications,” Journal of Micromechanics and Microengineering, vol. 19, pp. 083001+, Aug. 2009. [18] H. J. J. Yeh and J. S. Smith, “Fluidic self-assembly for the integration of GaAs light-emitting diodes on Si substrates,” Photonics Technology Letters, IEEE, vol. 6, pp. 706–708, June 1994. [19] J. K. Tu, J. J. Talghader, M. A. Hadley, and J. S. Smith, “Fluidic self-assembly of InGaAs vertical cavity surface emitting lasers onto silicon,” Electronics Letters, vol. 31, pp. 1448–1449, Aug. 1995. [20] I. Soga, S. Hayashi, Y. Ohno, S. Kishimoto, K. Maezawa, and T. Mizutani, “Direct integration of GaAs HEMTs on AlN ceramic substrates using fluidic self-assembly,” Electronics Letters, vol. 41, pp. 1275–1276, Nov. 2005. [21] U. Srinivasan, M. A. Helmbrecht, C. Rembe, R. S. Muller, and R. T. Howe, “Fluidic self-assembly of micromirrors onto microactuators usingcapil- lary forces,” IEEE Journal of Selected Topics in Quantum Electronics, vol. 8, pp. 4–11, Jan. 2002. [22] K. L. Scott, T. Hirano, H. Yang, H. Singh, R. T. Howe, and A. M. Nikne- jad, “High-performance inductors using capillary based fluidic self-assembly,” Journal of Microelectromechanical Systems, vol. 13, pp. 300–309, Apr. 2004. [23] X. Xiong, Y. Hanein, J. Fang, Y. Wang, W. Wang, D. T. Schwartz, and K. F. Bohringer, “Controlled multibatch self-assembly of microdevices,” Journal of Microelectromechanical Systems, vol. 12, pp. 117–127, Apr. 2003. [24] C. F. Edman, R. B. Swint, C. Gurtner, R. E. Formosa, S. D. Roh, K. E. Lee, P. D. Swanson, D. E. Ackley, J. J. Coleman, and M. J. Heller, “Electric 43
- 48. BIBLIOGRAPHY field directed assembly of an InGaAs LED onto silicon circuitry,” Photonics Technology Letters, IEEE, vol. 12, pp. 1198–1200, Sept. 2000. [25] C. Fonstad, “Magnetically-Assisted Statistical Assembly - a new heteroge- neous integration technique,” tech. rep., MIT, 2002. [26] E. Iwase and I. Shimoyama, “Multistep sequential batch assembly of three- dimensional ferromagnetic microstructures with elastic hinges,” Journal of Microelectromechanical Systems, vol. 14, pp. 1265–1271, Dec. 2005. [27] J. S. Agashe and D. P. Arnold, “A study of scaling and geometry effects on the forces between cuboidal and cylindrical magnets using analytical force solutions,” Journal of Physics D: Applied Physics, vol. 41, pp. 105001+, May 2008. [28] O. Cugat, J. Delamare, and G. Reyne, “Magnetic micro-actuators and systems (MAGMAS),” IEEE Transactions on Magnetics, vol. 39, pp. 3607–3612, Nov. 2003. [29] Q. Ramadan, Y. S. Uk, and K. Vaidyanathan, “Large scale microcomponents assembly using an external magnetic array,” Applied Physics Letters, vol. 90, pp. 172502–172502–3, Apr. 2007. [30] J. H. Hoo, K. S. Park, R. Baskaran, and K. F. Bohringer, “Programmable self- assembly for microsystem integration,” proc. TRANSDUCERS, pp. 848–853, June 2011. [31] S. Kaimori, T. Nonaka, and A. Mizoguchi, “The development of Cu bonding wire with oxidation-resistant metal coating,” IEEE Transactions on Advanced Packaging, vol. 29, pp. 227–231, May 2006. 44
- 49. Appendix A ISEL Robot A.1 ISEL Robot Specifications The ISEL IWH-series robot is a high precision wafer handler robot with a two- sided wafer gripper and a wafer mapper. The following specifications describe the operation condition as well as motion precision and parameter limits. Operation Condition Since the robot is capable of very fast and wide movements, it is imperative that the robot is fastened immovable and that no obstacle is placed around the robot. The robot should not be approached too closely or touched during operation for the risk of injury. The specifications on the environmental condition is given in table A.1. Ambient temperature 5 ◦C to 40 ◦C Humidity 5 to 90%, non-condensing Table A.1: Environmental condition for operation of the wafer handler robot. Motion Specifications The movement of the robot arm is described by three axes, T, R, and Z. The T-axis describes the rotational movement of the arm around the centre line of the robot. The radial movement of the wafer gripper is described by the R-axis, whereat the gripper itself always keeps a radial position towards the centre. And finally, the Z- axis describes the vertical movement of the whole robot arm. The units of measure for the T-axis, therefore, is given in rotational units (typically 0.01◦), while the R- and Z-axes are measured in a metric unit (typically 1 mil = 25 µm). The range of movement of these three axes is given in table A.2. The maximum speed of each axis is then presented in table A.3 and finally the precision of the robotic motion is listed in table A.4. 45
- 50. A ISEL Robot Axis Range of movement T -240◦ to 240◦ R -14.4" to 14.4" (-36.6 cm to 36.6 cm) Z -0.5" to 12.2" (-1.3 cm to 31.0 cm) Table A.2: Range of movement for the rotational axis T, the radial axis R, the and vertical axis Z. Axis Maximum speed T 360◦/s R 1000 mm/s Z 450 mm/s Table A.3: Maximum speed specification for all three axes. Axis Precision T 0.02◦ R 30 µm Z 30 µm Table A.4: Precision specification for all three axes. A.2 Command Set Table A.5, provides an overview over the most frequently used commands for the assembly robot. This is not to be mistaken with a complete list of commands, as it only contains commands which are relevant during the execution of the robotic as- sembly process. The left column entries consist of a three letter ASCII string which represents the key word that has to be sent to the robot through the command line in the control software. For the complete syntax of the commands, including additional parameters and options, the command reference in the robot hand book is to be consulted. Command string Description ACL Set / display axis acceleration AJK Set / display axis acceleration jerk CPO Display current position DCL Set / display axis ceceleration ... ... Table A.5: Most frequently used commands for the assembly robot. 46
- 51. A.2 Command Set Table A.5: continued Command string Description ... ... DJK Set / display axis ceceleration jerk GET Get a wafer from a station HOM Start homing procedure for the robot (= Move to Home position!) MAP Display results from last wafer scanning MSS Move a wafer from station to station MTH Move to Home position MTP Move three axes to position (Caution! New position will be approached on shortest path.) MTS Move arm to station position MVA Move axis to absolute position MVR Move axis to relative position NST Display number of stations PUT Put a wafer into a station RES Reset the controller SCN Start wafer scanning for a sta- tion SNR Display robot serial number SOF Turn axis servo power OFF SON Turn axis Servo power ON SPD Set / display working speed STA Command execution status (Consult status table in robot hand book page 131) STP Stop motions and tasks VOF Turn vacuum OFF VON Turn vacuum ON Table A.5: Most frequently used commands for the assembly robot. 47
- 52. Appendix B Experimental Data for Filling Rates Filling experiments were conducted in order to determine the capabilities of the robotic assembly process and to find an effective and reliable movement strategy. Multiple via hole arrays with of 10 × 10 holes were filled in the process. Below, the gathered data is presented in its raw numerical form. For a graphical depiction of the data, see figure 3.6. Small Rectangles The pattern called small rectangles is a pattern of advancing rectangles and is implemented in the control software under the name Helix. The path length of this pattern was set to d = 30 (See figure 3.5) and the movement parameters were taken from the parameter set Slow2 (See appendix B.1). Time [s] 0 10 20 30 40 80 120 160 200 Filled Holes [%] 0 15 17 20 22 49 73 82 90 Table B.1: Filling rate experiment for the pattern small rectangles with movement parameter set Slow2 Spline The spline movement pattern is implemented under the same name and was exe- cuted with a path length of d = 200 (See figure 3.5). The movement parameter set was again set to Slow2 (See appendix B.1). Time [s] 0 5 10 15 20 25 30 40 50 60 80 100 Filled Holes [%] 0 15 25 36 46 51 57 74 78 82 92 96 Table B.2: Filling rate experiment for the pattern spline with movement parameter set Slow2 48
- 53. B.1 Movement Parameter Sets Slow Spline The slow spline experiment was conducted with the pattern called spline and path length of d = 200 (See figure 3.5). The movement parameters were set to re- allySlow (See appendix B.1). Since this experiment achieved 100% filling yield, it was repeated to verify its performance. Time [s] 0 6 13 18 23 27 32 37 42 47 53 66 81 Filled Holes [%] 0 28 45 59 75 79 87 89 90 94 96 98 100 Table B.3: The first filling rate experiment for the pattern slow spline with move- ment parameter set reallySlow Time [s] 0 6.5 13 19.5 26 32.5 39 45.5 52 66 Filled Holes [%] 0 48 64 80 91 91 94 95 96 100 Table B.4: The second filling rate experiment for the pattern slow spline with move- ment parameter set reallySlow B.1 Movement Parameter Sets The different movement parameter sets used for the filling rate experiments are shown in this section. They comprise characteristic values for all three axes. Slow2 Speed Acceleration Jerk T 1200 1400 25 R 900 2000 25 Z 950 2000 25 Table B.5: Movement parameter set Slow2 reallySlow Speed Acceleration Jerk T 40 1400 25 R 400 2000 25 Z 450 2000 25 Table B.6: Movement parameter set reallySlow 49
- 54. Appendix C Fabrication Specifications C.1 Wafer Specifications For the fabrication of RF-capable TSV structures special high resistivity wafers were used to ensure good signal transmission performance. The exact specifications of these wafers are given in table C.1. Price $/unit Material Orient. Diam. [mm] Thickn. [µm] Surf. Source Resistivity [Ωcm] Comment $86.60 p-type Si:B [100] 100 350 P/P ITME FZ 5,000- 8,500 SEMI, 1Flat Table C.1: Specifications of the high resistivity wafers C.2 BCB Curing Procedure The curing step of the insulation polymer BCB CYCLOTENER 3022-46 was car- ried out on a hot plate inside a vacuum chamber at 0.02 mbar. A temperature ramping procedure was performed according to the manufacturers specifications, as shown in table C.2. Step Full Cure 1 15 min ramp to 100 ◦C 2 15 min soak at 100 ◦C 3 15 min ramp to 150 ◦C 4 15 min soak at 150 ◦C 5 60 min ramp to 250 ◦C 6 60 min soak at 250 ◦C 7 cool to < 150 ◦C Table C.2: Curing procedure for BCB CYCLOTENER 3022-46 50