![CMOS Operation
VG = 0, p+ majority carriers freely floating to
the p substrate.
VG<0, Freely floating holes are accumulated
near to the meal oxide layer. [Accumulation
Mode]
0<VG<VT, Holes will start to ripple.
[Depletion Mode]
VG>VT, Current will start to flow from VDD to
VSS [Inversion Mode]](https://image.slidesharecdn.com/metroscientificweek1-230630052632-9aeae3e4/85/MetroScientific-Week-1-pptx-10-320.jpg)
MetroScientific Week 1.pptx
- 1. Overview of VLSI Circuits and Design Bipin Saha Electrical Engineer Intern MetroScientific
- 2. Evaluation of Transistor A piece of gold foil was glued to the edge of a triangular plastic wedge, and then the foil was sliced with a razor at the tip of the triangle. The result was two very closely spaced contacts of gold. Vacuum Tube is a device that controls electric current flow in a high vacuum between electrodes to which an electric potential difference has been applied.
- 3. Integrated Circuit (IC) Jack Kilby's original hybrid integrated circuit from 1958. This was the first integrated circuit, and was made from germanium. Reduce size of circuits. Increased cost-effectiveness for devices. Improved performance in terms of operating speed of the circuits. Requires less power than discrete components. Higher device reliability. Requires less space and promotes miniaturization. Advantage of VLSI
- 5. VLSI Development Process VLSI Development Process Includes Problem Specification Architecture Definition Functional Design Logic Design Circuit Design Physical Design Circuit Partitioning Floor Planning and Placement Routing Layout Compaction Extraction and Verification Packaging Package Entity Declaration Architecture Process Config VHDL Code Blocks
- 6. VLSI Design Process Full Custom Design Semi Custom Design Complete deign, layout, geometry, orientation and placement of transistor is done by resistor. Some commonly used design, layout geometry and placement of transistor is interfaced with given demand. Entire design is made without use of any library. Design is completed with the use of multiple multiple library. Development time for design before maturity is more. Development time for design before maturity is less. It has more opportunity for performance improvement. It has less opportunity for performance improvement. Less dependency on existing technology. Complete dependency on existing technology. High Cost Low Cost
- 7. VLSI Design Process Contd.
- 8. VLSI Design Flow Design Specification Architecture Design Gate Level Design Circuit Level Design HDL Coding Simulation Verification Fabrication CMOS Circuit Gate Module Integrated System
- 9. Domains of VLSI Design Behavioral Domain Structural Domain Physical/Geometrical Layout Domain
- 10. CMOS Operation VG = 0, p+ majority carriers freely floating to the p substrate. VG<0, Freely floating holes are accumulated near to the meal oxide layer. [Accumulation Mode] 0<VG<VT, Holes will start to ripple. [Depletion Mode] VG>VT, Current will start to flow from VDD to VSS [Inversion Mode]
- 11. pMOS vs nMOS Type nMOS pMOS Symbol Structure Source, Drain – n Type Substrate – p Type Source, Drain – p Type Substrate – n Type Majority Carrier Electron Holes Current Flow Drain to Source Source to Drain Size Smaller compared to pMOS Larger compared to nMOS Working If G = 0, o/p = 0 If G = 1, o/p = 1 If G = 0, o/p = 1 If G = 1, o/p = 0 Operating Speed Faster Slower
- 12. CMOS Operation Region Vin Vout nMOS pMOS A VIN<V VT VOH OFF SAT B VIL VOH SAT LIN C VT VT SAT SAT D VIH VOL LIN SAT E VDD VOL LIN OFF A B C D *SAT - Saturation, **LIN - Linear
- 13. CMOS Fabrication Process Includes Wafer Clean and Prime Photoresist Coating Soft Bake Post-exposure Bake Development Pattern Inspection Hardbake Photoresist Stripping p Well Process Twin Tub Process
- 14. Gates using CMOS At nMOS If G = 0, OFF If G = 1, ON At pMOS If G = 0, ON If G = 1, OFF pMOS Transistor can easily pass Logic HIGH nMOS Transistor can easily pass Logic LOW Pullup - a network that provides a low resistance path to Vdd when output is logic '1' and provides a high resistance to Vdd otherwise. Pulldown - a network that provides a low resistance path to Gnd when output is logic '0' and provides a high resistance to Gnd otherwise. AND (.) Operation pMOS – Parallel nMOS – Series OR (+) Operation nMOS – Parallel pMOS – Series
- 15. Gates using CMOS Contd. CMOS NAND Gate AND (.) Operation pMOS – Parallel nMOS – Series OR (+) Operation nMOS – Parallel pMOS – Series Input pMOS nMOS Out A B Q1 Q2 Q3 Q4 0 0 ON ON OFF OFF 1 0 1 ON OFF OFF ON 1 1 0 OFF ON ON OFF 1 1 1 OFF OFF ON ON 0 Q1 Q2 Q3 Q4
- 16. Gates using CMOS Contd. CMOS NOR Gate AND (.) Operation pMOS – Parallel nMOS – Series OR (+) Operation nMOS – Parallel pMOS – Series Input pMOS nMOS Out A B Q1 Q2 Q3 Q4 0 0 ON ON OFF OFF 1 0 1 ON OFF OFF ON 1 1 0 OFF ON ON OFF 1 1 1 OFF OFF ON ON 0 Q1 Q2 Q3 Q4 VDD GND
- 17. Gates using CMOS Contd. CMOS SR Latch AND (.) Operation pMOS – Parallel nMOS – Series OR (+) Operation nMOS – Parallel pMOS – Series S R Q Qnot Oprt. 0 0 Memory Hold 0 1 0 1 Reset 1 0 1 0 Set 1 1 0 0 N/A
- 18. Stick Diagram A Stick Diagram is a simple way of representing the layout by using thick lines with their interconnections. The diagram is useful in estimating the area and planning the layout before the layout is generated withing a shorter cycle time. A Stick Diagram can be called a cartoon of layout. Lines using different colors are used to draw different components of the layout Metal 1 poly ndiff pdiff Can also draw in shades of gray/line style. Gnd VDD x x X X X X VDD x x Gnd
- 19. CMOS Transmission Gate Trai State Buffer AND (.) Operation pMOS – Parallel nMOS – Series OR (+) Operation nMOS – Parallel pMOS – Series Input Output C A F State 0 0 Z OFF 0 1 Z OFF 1 0 0 ON 1 1 1 ON *pMOS Good to PASS Logic ‘1’
- 20. CMOS Transmission Gate MUX 4:1 Multiplexer Input Output C0 C1 M 0 0 X0 0 1 X1 1 0 X2 1 1 X3
- 21. Dynamic CMOS Precharge When CLK=0, the o/p node is precharged to VDD by the pMOS Mp. During that time the evaluate nMOS transistor Me is OFF, so that the PDN path is disabled. The evaluation FET eliminates any static power that would be consumed during precharge period. Evaluation For CLK=1, the precharge transistor Mp is OFF, and the evaluation transistor Me is turned ON. The o/p is conditionally discharged based on the i/p values and the PDN topology. If the i/p are such that PDN conducts, then a low resistance path exists between Out and GND, the o/p is discharged to GND.
- 22. PLA and PAL Programmable Logic Array The definition of term PLA presents the Boolean function in the form of a sum of product (SOP). The designing of this programmable logic array can can be done using the logic gates like AND, OR, and and NOT by fabricating on the chip, that makes every input as well as its compliment obtainable toward every AND gate. Programmable Array Logic The definition of term PAL or Programmable Array Logic is one type of PLD which is known as Programmable Logic Device circuit, and working of this PAL is the same as the PLA. The designing of the programmable array logic can be done with fixed OR gates as well as programmable AND gates. gates. By using this we can implement two easy functions wherever the associates AND gates with each OR gate denote the highest number of product conditions that can be produced in the form of SOP (sum of product) of an exact function. Programmable Array Logic Programmable Logic Array
- 23. Field Programmable Gate Array FPGA - Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. The architecture mainly consists of, Configurable logic blocks Configurable I/O blocks Programmable interconnect Configurable logic blocks Configurable I/O blocks Programmable interconnect
- 24. Thank You Bipin Saha Electrical Engineer Intern MetroScientific