microprocessor and its application with practical gaining.ppt

Microprocessors & its
Applications
Prepared By,
Esther Hannah

What is microprocessor?
• It is a multipurpose programmable clock-driven,
register-based electronic device that reads binary
instructions from a storage device called memory,
accepts binary data as input and processes data
according to those instructions, and provides
results as output.

Evolution of Microprocessors
Background
• In 1971, intel launched the 4004, the first 4-bit microprocessor
• In 1972, Intel launched the 8008, the first 8-bit microprocessor The device needed
several additional ICs to produce a functional computer
• In 1974, Intel launched the 8080, employing the new 40-pin packages originally
developed for calculator ICs to enable a separate address bus.
• Intel launched 8085 with few more added features in the architecture of 8080, thus
becoming the popular and widely used 8-bit microprocessor.
• Other well known 8-bit microprocessors that emerged during these years were Motorola
6800 (1974), Microchip PIC16X (1975), MOS Technology 6502 (1975), Zilog Z80
(1976), and Motorola 6809 (1977), as well as others.
• In 1978, intel launched the 8086, the first 16-bit microprocessor, with more powerful
instruction set with programming flexibility and speed better than 8-bit microprocessors.

8086
• Intel 8086 Microprocessors:
Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC compatible
computers(8086 introduced in 1978, first IBM-PC released in 1981)
All Intel and other advanced microprocessors are based on and are
compatible with the original 8086
* At Power Up and Reset time, Pentiums, etc all look like 8086 processors
• Features:
* Intel 8086 is a 16bit microprocessor:
* 16b data registers, 16bit ALU
* Width of external data bus: 16bit
* Width of external address bus: 16bit+4bit=20bits
To optimize the CPU performance when it’s executing programs
8086 consists of two internal units
1. The execution unit (EU) - executes the instructions
2. The bus interface unit (BIU) - fetches instructions, reads operands and writes
results

Register Organization
• The 8086 family, like other processors, has both
• General purpose data registers
• Special l purpose registers
• General Purpose Data Registers
The general purpose registers can be considered to fall down in one of three groups
based upon the size (width) of the register itself. 8-bit, 16-bit, and 32-bit registers .

Data Registers
•
There are four data registers. They are used to hold data for manipulation. The processor
can operate faster on data stored on the registers than the data stored in memory.
The four Data registers are AX, BX,CX and DX.
1. AX Register:
Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of
the word, and AH contains the high-order byte.
Accumulator can be used for I/O operations and string manipulation.
AH (8 bit) AL (8 bit)
2. BX Register:
Base register consists of two 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word,
and BH contains the high-order byte.
BX register usually contains a data pointer used for based, based indexed or register
indirect addressing.
BH (8 bit) BL (8 bit)

Data Registers
3. CX Register:
Count register consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX. When combined, CL register
contains the low-order byte of the word, and CH contains the high-order byte.
Count register can be used as a counter in string manipulation, shift/rotate instructions,
and as loop counter.
CH (8 bit) CL (8 bit)
4. DX Register:
Data register consists of 2 8-bit registers DL and DH, which can be combined
together and used as a 16-bit register DX. When combined, DL register contains the
low-order byte of the word, and DH contains the high-order byte. Data register can be
used as a port number in I/O operations.
In integer 32-bit multiply and divide instruction the DX register contains high-order
word of the initial or resulting number.
DH (8 bit) DL (8 bit)

Intel 16-Bit Registers
General Purpose
AX
BX
DX
CX
AH AL
7 0 7 0
AX
15 0

1. Segment Registers
2. Pointers and Index registers
3. Flag Registers

Segment Registers
• Segment Registers - CS, DS, SS, ES
Always point to low address end of segment
CS - Code Segment Register - points to a segment containing code
DS - Data Segment Register - points to a segment containing data
SS - Stack Segment Register - points to a segment containing stack
ES - Extra Segment register - points to a segment containing data
There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor memory these 4 segments are located the processor
uses four segment registers:
• 1. CS register
Code segment (CS) is a 16-bit register containing address of 64 KB segment with
processor instructions. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register.
• 2. SS Register
Stack segment (SS) is a 16-bit register containing address of 64KB segment with
program stack. By default, the processor assumes that all data referenced by the stack
pointer (SP) and base pointer (BP) registers are located in the stack segment.

Segment Registers
• 3. DS register
Data segment (DS) is a 16-bit register containing address of 64KB
segment with program data. By default, the processor assumes that all data
referenced by general registers (AX, BX, CX, DX) and index register (SI, DI)
is located in the data segment.
• 4. ES register
Extra segment (ES) is a 16-bit register containing address of 64KB
segment, usually with program data. By default, the processor assumes that the
DI register references the ES segment in string manipulation instructions.

Segment
CS
SS
ES
DS
CS
15 0

Pointer registers and Index registers
The pointer registers are used to hold the offset of memory location. The pointer registers can
be used in arithmetic and other operations.
1. SP register  The SP (Stack Pointer) register is used in conjunction with SS for accessing
the stack segment.
2. BP register  The BP (Base Pointer) register is used to access data on the stack. BP can
also be used to access data in other segment.
3. IP register  The IP (Instruction Pointer) register contains the offset address of the next
instruction that is to executed. IP is associated with the CS register in that IP indicates the
current instruction within the currently executing code segment. The 16-bit instruction pointer
(IP) is analogous to the program counter (PC) on other CPUs. The instruction pointer is
updated by the BIU
4. SI register  The SI (Source Index) register is used to point to memory locations in the
data segment addressed by DS. By incrementing SI we can access consecutive memory
locations. They are normally used for string manipulation.
5. DI register  The DI (Destination Index) register is used to point to memory locations in
the extra segment addressed by ES. By incrementing DI we can access consecutive memory
locations. They are normally used for string manipulation.

Index & Pointers registers
BP
SP
DI
BP
15 0
SI
IP

Flag Register
• Flags Register – individual bit positions within register show status of CPU or results of
arithmetic operations.
– Control Flags (Direction, Interrupt, Trap)
– Status Flags (Carry, Overflow, Sign, Zero, Auxiliary Carry, Parity)
• Status Flags :
• Carry (CF) – set when the result of an unsigned arithmetic operation is too large to fit
into the destination.
• Overflow(OF) – set when the result of a signed arithmetic operation is too wide to fit into
the destination.
• Sign(SF) – set when the result of an arithmetic or logical operation generates a negative
result.
• X – Not used
X X X X O D I T S Z X Ac X P X Cy

Flags
• Zero (ZF) – set when the result of an arithmetic or logical operation is zero.
• Auxiliary Carry (AF) – set when the result of an operation causes a carry from
bit 3 to bit 4.
• Parity (PF) – reflects whether the number of 1 bits in the result of an operation
is even or odd. 1 – odd, 0-even.
• Control flags:
• Interrupt (IF) – dictates whether or not system interrupts can occur. 1 –
enabled, 0 – disabled.
• Trap(TF) – determines whether or not the CPU is halted after each instruction.
Allows programmers to do tracing.
• Direction(DF) – affects block data transfer instructions such as MOVS, CMPS.
0 – up, 1 – down.

• 16-bit ALU
• 16-bit registers
• Segmented memory addressing
• Rich instruction set
• Powerful interrupt structure
• Instruction queue

• Bus Interface Unit(BIU)
• Execution Unit(EU)

Bus Interface Unit (BIU):-
• Bus Interface Unit (BIU):-
• The BIU facilitates communication between the EU and the memory or I/O
circuits. It is responsible for transmitting address, data, and the control signals on the
buses.
• It contains :
– Contain segment register,
– instruction pointer,
– address generation adder(Circuit for physical address calculation)
– bus control logic
– instruction queue(Predecoding instruction byte queue(6-bytes long))
• The IP contains the address of the next instruction to be executed by the EU.
An internal bus connects the EU and BIU, and they work together.

• While the EU is executing an instruction the BIU fetches up to six bytes of next
instruction and places it in the Instruction Queue to speed up the processor. This
operation is called instruction prefetch.
• Use instruction queue to implement a pipelined architecture.
• Instruction queue is 6-bytes long, FIFO structure
• Instructions from the queue are taken for decoding sequentially.
• BIU-fetches the instruction and Eu- Executes the instruction
• Perform bus operation such as instruction fetching, reading/writing of data operand for
memory, inputting/outputting data for I/O peripherals.

• Address generation adder:
• 8086 addresses a segmented memory
• Physical address is 20-bits long
• Generated using segment and offset registers,
each 16-bits long

• Segment address:
A segment is a special area in a program that begin on a paragraph. Segment
address represents the starting address or base address of each segment. The segment
address located within one of the segment registers.
• Physical Address:
Physical address is the address placed in the address bus by the
microprocessor. The value contained in the IP is referred to as an offset. This value must
be added to the segment base address in CS to produce the required 20 bit physical
address.
• Segment
A Memory segment is a block of 216 (or 64 KB) consecutive memory bytes. A segment
number, starting with 0, identifies each segment. A segment number is 16 bits, so the
highest segment number is FFFF H.
Within the segment, a memory location is specified by giving an offset, which is the
number of bytes from the beginning of segment. Within the 64KB segment the offset
can be given as a 16-bit number. The first byte in a segment has an offset 0. The last
offset in a segment is FFFF H.
Segment registers work together with general-purpose register to access any memory
value. Providing a segment number and an offset, written in the form segment:offset, we
can specify a memory location.

Address Calculation
• For example if we would like to access memory at the physical address
12345h (hexadecimal), we should set the DS = 1230h and SI = 0045h. CPU makes a
calculation of physical address by multiplying the segment register by 10h and adding
general purpose register to it (1230h * 10h + 45h = 12345h):
• 12300 H Segment address
+ 0045 H Offset
-----------------
12345 H 20-bit physical address
-----------------
The value in the segment register left shifted by four bits position, with LSB filled with
zeros (ie multiplying the hexadecimal address in segment register by 10H) is called the
segment address.
• The address formed with 2 registers (segment register and index register) is called an
effective address. By default BX, SI and DI registers work with DS segment register, BP
and SP work with SS segment register. Other general-purpose registers cannot be used
to form effective address.
• When the physical address and the offset is given the segment address can be calculated

Execution Unit (EU)
• The purpose of the execution unit is to execute the instruction. It contains a circuit called
arithmetic and logic unit (ALU).
• The ALU can perform arithmetic and logical operations. The data for the arithmetic and
logic operations are stored in circuits called registers. Registers are temporary storage
area, which can be referred by its name.
• The EU has eight registers for storing data. They are AX, BX, CX, DX, SI, DI, BP and
SP. In addition
• EU has temporary registers for holding operands for CPU, and the FLAGS registers
whose individual bit reflect the result of a computation.
• EU is responsible for decoding and executing instruction and accesses the instruction
from output end of the instruction queue and data from general-purpose register.
• It reads one instruction at a time, decodes them, generates operand address if necessary,
passes them to BIU and requests to perform the read/write cycle to memory or I/O, and
performs the operation specified by the instruction on operand.
• During execution, EU may test the status and control flags and update these flags based
on the results of execution.

Segmentation
8086 Address Space
* The 8086 processor has a 20-bit physical address to directly address 1M byte of
memory
* Word size is only 16 bits
* 20-bit address is splitted in 16-bit segment address and 16-bit offset address
Segment address shifted four bits to the left and added to the offset value to generate a 20-
bit effective address. Effective address is expressed as a 5 digit hex value (00000h to
FFFFFh)
Memory Segments
* A segment is a block of 64K consecutive memory bytes
* Segments are identified by segment numbers 0 - FFFFh
* A 16 byte block makes up a paragraph
* Segments always start on paragraph boundaries
* Least significant nibble of segment address will always be 0

Addressing
• Addresses
The memory is collection of bytes. Each memory byte has an address.
• The 8088 processor assigns a 20-bit physical address to its memory location.
• It is possible to address 220
=1,048,576 (one mega byte) of memory.
• The lowest physical memory address is 0000H and the highest physical memory
address is FFFFF H.
The first five bytes of memory address are
0000 H, 0001 H, 0002 H, 0003 H, 0004 H
All the registers and address bus used in the 8088 microprocessor is 16 bit long but the
physical address is of 20 bit long, 8088 overcomes this problem by partitioning the
memory into segments.
• Effective address:
• Within a program,all memory locations within a segment are relative to the segmaent
starting address.The distance in bytes from the segment address to another location
within the segment is expressed as an offset or displacement.
• Effective address = Segment starting address + displacement
• To address a specific memory location within a segment we need an effective address of
16-bit long.

Example
• Given physical address = 80FD2 h
Offset = BFFD2 h.
• Calculate the segment address.
• Solution
Physical address = segment * 10 h + offset
Segment = (physical address – offset ) /10 h
= (80FD2 h – BFD2 h) /10
= 7500 h
So the segment address for the given physical address and offset is 7500 h.

• Addressing mode indicates a way of locating data or
operands.
• Instructions may belong to one or more addressing
modes, or some instructions may not belong to any of
the Addressing Modes.
• Addr. modes of the instns. Depending upon their
types:
• Instruction types
– Sequential control flow
– Control transfer

• Sequential control flow:
Instructions which after execution, transfer control to the
next instruction appearing immediately after it in the program. Eg:
• Arithmetic
• Logical
• Data transfer
• Processor control instructions
• Control transfer
• Transfer control to some predefined address or the address
specified in the instruction, after their execution. Eg: INT,
CALL, RET and JUMP

• Types
– Addressing modes for accessing immediate and
register data
– Addressing modes for accessing data in memory
– Addressing modes for accessing I/O ports
– Relative Addressing mode
– Implied Addressing mode
Note: Eff. Address is the address which contains the
actual operand

(1) Register
• Register mode allows a register to be specified as an operand
• Example 1: MOV AX, DX
• AX := DX -> Contents of DX is copied to AX
• Example 1: MOV CL, BL
(2) Immediate
• Immediate mode: constant specified as source
• constant value assembled into the instruction
• Example : MOV AL, 5 // AL: 8-bit destination
• Example : MOV AX, 5 // AX: 16-bit destination
• Example : MOV DH, VAL [ VAL EQUATE 35H]

• EU cannot directly access the memory operand
• EU must use BIU to access memory operands
• To access a memory location
– EU sends an offset value to BIU
– Offset is called Effective address which is the displacement from the segment base
– BIU address adder generates 20-bit physical address
• 8086 must use a segment register whenever it accesses the memory.
• For every memory addressing instructions uses an intel-defined standard default seg.
Registers
• However, a segment override prefix can be placed before most of the mem. Address
instructions whose default segment registers is to be overridden.
– Eg: INC BYTE PTR[START]
– INC ES: BYTE PTR[START]
– s

• Direct addressing mode
• Register indirect addressing mode
• Based addressing mode
• Indexed addressing mode
• Based indexed addressing mode
• String addressing mode

(3) Direct Memory
• Direct memory mode: address offset of a memory variable specified as an operand
• constant address offset: encoded as part of the instruction
• During execution, address offset implicitly combined with DS
Example : MOV AL, [5]// Reads contents of byte at address DS:[0005]
Example : MOV X, AX // Assumes variable declared in data segment & Write contents of
word at address DS:X
Example : MOV CX, START
START DW 0040H
(4) Register Indirect
• The address of the memory location which contains data or operand is determined in an
indirect way using offset registers.
• The offset address of data is in either BX, SI or DI register.
• The default segment is DS or ES.
• Ex: MOV AX, [BX] // data is present in a memory location whose offset is in BX

(5) Indexed
• Offset of the operand is stored in one of the index registers.
• DS is the default segment for the index registers SI & DI.
• Ex: MOV AX, [SI] // data is stored at an offset address specified in Source index
register.
(6) Register Relative
• Data is available at an effective address formed by adding an 8 bit or 16 bit
displacement with the content of any one of the BX, BP,SI and DI registers.
• Ex: MOV AX, 50H[BX]// 50h is added with the content of BX register to get the offset
address of the operand.
(7) Based Indexed
• The effective address of data is formed by adding the content of a base register (BP or
BX) to the content of the index register (SI or DI).
• Ex: MOV AX, [BX] [SI]

(8) Relative Based Indexed
• The effective address is formed by adding an 8 or 16 bit displacement with the sum of
the contents of any one of the base registers (BX or BP) and the index register specified.
• Ex. Mov AX, 50h [BX][SI]
• 50h is immediate displacement , BX is the base register and SI is the source index
register.

• Types:
• Intersegment
– Intersegment direct mode
– Intersegment indirect mode
• Intrasegment
– Intrasegment direct mode
– Intrasegment indirect mode
• Intersegment: Location to which the control is to be
transferred lies in a different segment, other than the current
one.
• Intrasegment: Location lies in the same segment.

Instruction Types
1. Data copy/Transfer Instructions
2. Arithmetic and logical Instructions
3. Branch Instructions
4. Loop Instructions
5. Machine control Instructions
6. Flag Manipulation
7. Shift and rotate
8. Subroutine and Interrupt Instructions
9. String Instructions

Instruction Types
• Data copy / Transfer Instructions: Used to transfer data from source
operand to destination operand.
– MOV Move byte or word to register or memory
– IN, OUT Input byte or word from port, output word to port
– LEA Load effective address
– LDS, LES Load pointer using data segment, extra segment
– PUSH, POP Push word onto stack, pop word off stack
– XCHG Exchange byte or word
– XLAT Translate byte using look-up table
• Logical Instructions: Used to perform logical operations
– NOT Logical NOT of byte or word (one's complement)
– AND Logical AND of byte or word
– OR Logical OR of byte or word
– XOR Logical exclusive-OR of byte or word
– TEST Test byte or word (AND without storing)

Instruction Types
• Shift and Rotate Instructions: Involve the bitwise shifting or rotation in either direction with or
without a count in CX
– SHL, SHR Logical shift left, right byte or word by 1 or CL
– SAL, SAR Arithmetic shift left, right byte or word by 1 or CL
– ROL, ROR Rotate left, right byte or word by 1 or CL
– RCL, RCR Rotate left, right through carry byte or word by 1 or CL
• Arithmetic Instructions: Used to perform arithmetic operations
– ADD, SUB Add, subtract byte or word
– ADC, SBB Add, subtract byte or word and carry (borrow)
– INC, DEC Increment, decrement byte or word
– NEG Negate byte or word (two's complement)
– CMP Compare byte or word (subtract without storing)
– MUL, DIV Multiply, divide byte or word (unsigned)
– IMUL, IDIV Integer multiply, divide byte or word (signed)
– CBW, CWD Convert byte to word, word to double word (useful
– before multiply/divide)
– AAA, AAS, AAM, AAD ASCII adjust for addition, subtraction, multiplication,
– division (ASCII codes 30-39)
– DAA, DAS Decimal adjust for addition, subtraction (binary coded
– decimal numbers)

Instruction Types
• Branch Instructions: Transfer control of execution to the specified address
– JMP Unconditional jump
– JA (JNBE) Jump if above (not below or equal)
– JAE (JNB) Jump if above or equal (not below)
– JB (JNAE) Jump if below (not above or equal)
– JBE (JNA) Jump if below or equal (not above)
– JE (JZ) Jump if equal (zero)
– JG (JNLE) Jump if greater (not less or equal)
– JGE (JNL) Jump if greater or equal (not less)
– JL (JNGE) Jump if less (not greater nor equal)
– JLE (JNG) Jump if less or equal (not greater)
– JC, JNC Jump if carry set, carry not set
– JO, JNO Jump if overflow, no overflow
– JS, JNS Jump if sign, no sign
– JNP (JPO) Jump if no parity (parity odd)
– JP (JPE) Jump if parity (parity even)

Loop instructions: Used to implement unconditional and
conditional loops
–LOOP Loop unconditional, count in CX
–LOOPE (LOOPZ) Loop if equal (zero), count in CX
–LOOPNE (LOOPNZ) Loop if not equal (not zero), count in CX
–JCXZ Jump if CX equals zero

Instruction Types
• Subroutine and Interrupt Instructions: Transfer control of execution to the
Specified address.
– CALL, RET Call, return from procedure
– INT, INTO Software interrupt, interrupt if overflow
– IRET Return from interrupt
• String Instructions: Involves various string manipulation operations
– MOVS Move byte or word string
– MOVSB, MOVSW Move byte, word string
– CMPS Compare byte or word string
– SCAS Scan byte or word string
– LODS, STOS Load, store byte or word string
– REP Repeat
– REPE, REPZ Repeat while equal, zero
– REPNE, REPNZ Repeat while not equal (zero)

• Machine control Instructions: control the m/c status
– HLT
– NOP
– WAIT
– LOCK

• Flag manipulation Instructions: Directly affect the flag registers
– CLD
– STD
– CLI
– STI

• MOV instruction
The MOV instruction transfers data from a source operand (second operand) to
a destination operand (first operand). The operands can be internal registers of
8088 and memory locations. The content of the source operand is not changed.
Syntax
• MOV Destination, Source
• Example
MOV AX,40H ; Move the immediate value 40H to the AX register.
MOV AX,DS ; Move the segment register to AX
MOV BX,CX ; Move the content of CX register to BX register.
• The following are some of invalid MOV operation
MOV BX,CL ; Moving byte to word not allowed
MOV ES,CS ; Moving segment register to segment register not allowed
MOV num1,num2 ; moving memory to memory not allowed byte:
MOV instruction cannot be used to:
• Transfer data between segment register to segment register
• Transfer data between a source and destination that reside in external memory

• IN : -used for reading an input port
• Port address may be specified in the instruction directly or
indirectly
• AL and AX are the allowed destinations for 8 and 16-bit
input operations
• DX is the only register allowed to carry the port address
• Eg: IN AL, 0300H
IN AX

• OUT : -used for writing to an output port
• Port address may be specified in the instruction directly or
implicitly in DX
• AL and AX are the allowed source operands for 8 and 16-
bit operations
• DX is the only register allowed to carry the port address
• Data to an odd addressed port is transferred on D8-D15 while
that to an even addressed port is transferred on D0-D7
• Eg: OUT 0300H, AL
OUT AX

• PUSH: -Pushes the contents of the specified
register/memory location on to the stack
– Push operation decrements SP by 2 and then stores the 2 byte
contents of the operand onto the stack.
– Higher byte is pushed first and then the lower byte
• Eg: PUSH [3000H]
PUSH AX
PUSH DS

microprocessor and its application with practical gaining.ppt

• POP: -Loads the the contents of the specified
register/memory location with the contents of the
memory location[address -> SEG.REG:SP]
– POP operation increments SP by 2
– POP instruction serves exactly opposite to the PUSH
instruction.
• Eg: POP [3000H]
POP AX
POP DS

• XCHG : - exchanges the contents of the specified
source and destination operands, which may be registers
or one of them may be a memory location.
• Exchange of data contents of two memory locations is
not permitted.
• Eg: XCHG [3000H], AX
XCHG BX ; exchanges data between AX and BX

• XLAT:Translate instruction- used for finding out the codes in case of code
conversion problems, using look up table technique.
• Hexa decimal keypad having 0 to F which is interfaced with 8086 using
8255PPI
• When a key is pressed , the code of that key is returned in AL.
• For displaying the no. corr. to the key pressed on the 7-segment display device,
7-segment code for corr. To the pressed key is found out and sent to the display
port.
• This translation is performed using XLAT instruction.

• LEA: The load eff. Addr. Instruction loads the offset of an operand in the
specied register.
• Eg: LEA BX, ADR
loads the offset of the label ADR in BX

• LES/LDS: The instruction, load DS/ES with pointer means loads the
DS or ES register and the specified destination register in the instruction with
the content of memory location specified as source in the instruction.
• Eg: LDS BX, 5000H/LES BX,5000H

• LAHF: This instruction, loads the AH register with the lower byte of the
flag register.
• Eg: LAHF

• SAHF: This instruction sets or resets the condition code flags(except
overflow) in the lower byte of the flag register depending upon the corr. Bit
positions in AH If a bit in Ah is one , the flag corr. To the bit position is set,
else it is reset.
• Eg: SAHF

• PUSHF: This instruction pushes the flag register onto the stach; first the
upper byte and then the lower byte will be pushed .
• SP is decremented by 2 for each PUSH.
• Eg: PUSHF

• POPF: This instruction loads the flag register
completely (both bytes) from the word contents
of memory location currently addressed by SP
And SS.
• SP is incremented by 2 for each POP.
• Eg: POPF

• Basic Arithmetic instructions
The instruction set of 8086 microprocessor contains a variety of arithmetic
instructions. They include instructions for
• Addition
• Subtraction
• Multiplication
• Division
• Increment
• Decrement
• Negation
These operations can be performed on numbers expressed in variety of numeric
data formats. The data formats include signed or unsigned binary bytes or
words, unpacked or packed decimal bytes, or ASCII numbers.
• The status that results from the execution of an arithmetic instruction is stored
in the flag register. The flags affected by the arithmetic instruction are Carry
Flag (CF), Auxiliary Carry Flag (AF), Sign Flag (SF), Zero Flag (ZF), Parity
Flag (PF) and Overflow Flag (OF).

Note:
• Both the source and dest. Operands cannot be
memory operands
• Also the contents of the segment registers cannot
be used
• All the flags are affected , depending upon the
result.

• ADD instruction
• ADD instruction is used to add the contents of two registers, a register and a memory
location, to add a number to the register or memory location. The ADD instruction adds
the contents of source operand and the destination operand and stores the result in the
destination operand.
• Syntax
ADD destination, source
• destination=source + destination
The ADD instruction affects AF, CF, OF, PF, SF, and ZF.
Example:
ADD AX,BX ; This instruction adds the contents of AX and BX register and stores
the result in AX. : Register
• ADD AX,0100H : immediate/implicit
• ADD AX,[SI] : register indirecr
• ADD AX,[5000H] : direct
• ADD [4000H], 0100H : immediate
• ADD 0100H : implicit[Destination AX]

• ADC (Add with Carry) instruction
ADC instruction adds the source operand and the carry flag (CF) with the destination
operand and stores the result in the destination operand. ADC instruction is normally
used with multiple precision arithmetic.
• Syntax
ADC destination, source
• destination=source + CF + destination
• The ADC instruction affects AF, CF, OF, PF, SF, and ZF.
• Example:
ADC AX,BX ; This instruction adds the contents of AX , BX register and CF and
stores the result in AX.

• SUB instruction
SUB instruction is used to subtract the contents of two registers, a register and a memory
location. The SUB instruction subtracts the contents of source operand from the
destination operand and stores the result in the destination operand.
• Syntax
SUB destination, source
• destination= destination - source
The SUB instruction affects AF, CF, OF, PF, SF, and ZF.
• Example:
SUB CX,BX ;This instruction subtracts the contents of the register BX from the content
of the register CX and stores the result in CX.
• SUB AX,0100H : immediate/implicit
• SUB AX,[SI] : register indirecr
• SUB AX,[5000H] : direct
• SUB [4000H], 0100H : immediate
• SUB 0100H : implicit[Destination AX]

• SBB( Subtract with borrow) instruction
SBB instruction subtracts the contents of source operand and Carry Flag (CF) from the
destination operand and stores the result in the destination operand. SBB instruction is
normally used with multiple precision arithmetic.
• Syntax
SUB destination, source
• destination= destination - source - CF
The SUB instruction affects AF, CF, OF, PF, SF, and ZF.
• Example:
SBB CX,BX ;This instruction subtracts the contents of the register BX and CF from the
content of the register CX and stores the result in CX.

• Note: immediate data cannot be operand of INC & DEC
• INC instruction
The INC instruction adds 1 to the contents of a register or memory location.
• Syntax
INC destination
• The destination can be register or memory location.
• The INC instruction affects AF, OF, PF, SF, and ZF.
• Example:
• INC BX ; This instruction adds 1 to the content of BX
• INC [BX]
• INC [3000H]

• Note: immediate data cannot be operand of INC & DEC
• DEC instruction
The DEC instruction subtracts 1 from the contents of a register or memory location.
• Syntax
DEC destination
The destination can be register or memory location.
The DEC instruction affects AF, OF, PF, SF, and ZF.
Example:
• DEC BX ;This instruction subtracts 1 from the content of BX
• DEC [BX]
• DEC [3000H]

• NEG instruction
NEG replaces the content by its two’s complement.
• Syntax
NEG destination
• The destination can be register or memory location.
The NEG instruction affects AF, CF, OF, PF, SF, and ZF.
• If OF flag is set, indicates operation could not be completed
successfully.
• Example:
NEG BX ;This instruction negates the contents of register BX.

• MUL instruction(unsigned multiplication byte or word)
• The 8086 has instructions to support multiplication of binary and BCD numbers.
• Two basic types of multiplication instructions for processing of unsigned and signed numbers
are available.
If two bytes are multiplied the product is a word (16 bit). If two words are multiplied the
product is a double word (32 bit).
• MUL instruction assumes the MSB as data bit and not as sign bit.
• The multiplier may be register or memory.
• It cannot be a constant
This instructions affects CF and OF. After MUL, CF/OF=0 if the upper half of the result is zero.
• Most significant word of the result is stored in DX.
• Least significant word of the result is stored in AX.
• Syntax
MUL multiplier
• Eg: MUL BH : [AX]  [AL] * [BH]
MUL CX : [DX][AX]  [AX] * [CX]
MUL WORD PTR [SI] :[DX] [AX]  [AL] * [[SI]]

• IMUL instruction(signed multiplication byte or word)
• This instruction multiplies a signed byte in source operand by signed byte in AL or
signed word in source operand by signed word in AX.
• Source- Gen. pur. Reg or mem. operand or index reg. or base reg.
• Cannot not be an immediate data.
• Result is 32 bit , MSW is stored in DX and Lower order word in AX.
• Syntax
IMUL multiplier
• Eg: IMUL BH : [AX]  [AL] * [BH]
IMUL CX : [DX][AX]  [AX] * [CX]
IMUL [SI] :[DX] [AX]  [AL] * [[SI]]

Examples
• Division instructions
When division is performed we obtain two results, the quotient and the remainder.
• DIV instruction
The DIV instruction is to divide unsigned data. We can divide a byte by byte, a word by byte,
double word by word.
Syntax
DIV divisor
• The divisor may be register or memory. It cannot be a constant
Divide word by byte
When we divide a word by a byte the dividend is in AX and the divisor is a byte in memory or
register. The operation stores the remainder in AH and the quotient in AL
•
The multiplier may be register or memory. It cannot be a constant
IDIV instruction
The IDIV instruction is to divide signed data. We can divide a byte by byte, a word by byte, double
word by word and the operations are just like DIV instructions
For signed division the remainder has the same sign as the dividend.

Examples
• Conditional Jump
The processor supports a variety of conditional jump instruction that transfer control depending on settings in the
flags register.
To implement a conditional jump, the CPU looks at the FLAGS reg¬ister. We already know it reflects the result
of the last thing the processor did. If the conditions for the jump (expressed as a combination of status flag
settings) are true, the CPU adjusts the IP to point to the destination label, so that the instruction at this label will
be done next. If the jump condition is false, then IP is not altered; this means that the next instruction in line will
be done.
Syntax
Jxxx short label
Where xxx is the condition which specifies the status flags.
Range of a Conditional Jump
The structure of the machine code of a conditional jump requires that destination label must precede the jump
instruction by no more than 126 bytes, or follow it by no more than 127 bytes
There are three categories of conditional jumps: (1) the signed jumps are used when a signed interpretation is
being given to results, (2) the unsigned jumps are used for an unsigned interpretation, and (3) the single-flag
jumps, which operate on settings of individual flags. Note: the jump instructions themselves do not affect the
flags.
Signed and unsigned data
Distinguishing the purpose of conditional jumps should clarify their use. The type of data (unsigned or signed) on
which you are performing comparisons or arithmetic can determine which instruction to use.
An unsigned numeric item (logical data) treats all bits as data bits. For example numeric values such as customer
numbers, phone numbers are unsigned.
A signed numeric item (arithmetic data) treats the leftmost bit as a sign, where 0 means positive and 1 means
negative; typical examples are quantity, bank balance, which may be either positive or negative.
We can express these conditional jumps in one of the two symbolic operations; choose the one that is clearer and
more descriptive.
Signed Jumps

• The CMP instruction
The jump condition is often provided by he CMP (compare) instruction. The
CMP instruction can be used to compare two numeric data.
Syntax
• CMP destination, source
The operands for CMP cannot both be memory locations and the destination
location cannot be a constant.
The instruction computes the difference of the destination minus source
content. The result is not stored but the flags are affected.
CF SF ZF
Destination < source 1 1 0
Destination = source 0 0 1
Destination > source 0 0 0
The CMP instruction affects AF, CF, OF, PF,SF and ZF flags.

• LOOP instruction
The LOOP instruction works with respect to the contents of the CX register. CX must be preloaded with the count that represents the number of times the loop is to repeat.
Whenever the LOOP is executed, the contents of CX are first decremented by one and then checked to determine if they are equal to zero. If equal to zero the loop is complete,
and the instruction following LOOP is executed, otherwise, control is transferred instruction at the label specified in the loop instruction.
Syntax
• LOOP short-label
• Example:
………..
………..
MOV CX,10
NEXT: ………..
………..
LOOP NEXT
………..
………..
The LOOP instruction sequence shown above, the part of the program from label NEXT through the instruction LOOP is repeated ten times.
LOOPE / LOOPZ instruction
The instruction loop while equal (LOOPE) / loop while zero (LOOPZ) checks the contents of both CX and the zero flag (ZF). Each time the loop instruction is executed, CX
decrements by 1 without affecting the flags, its contents are checked for 0, and the state of the ZF that results from execution of the previous instruction is tested for 1.if CX is
not equal to 0 and ZF equals 1, a jump is initiated to the location specified with the short-label operand and the loop continues. If either CX or ZF=0 the loop is complete and the
instruction following the loop instruction is executed.
Syntax
• LOOPE / LOOPZ short-label
LOOPNE / LOOPNZ instruction
The instruction loop while not equal (LOOPNE) / loop while not zero (LOOPNZ) checks the contents of both CX and the zero flag (ZF). Each time the loop instruction is
executed, CX decrements by 1 without affecting the flags, its contents are checked for 0, and the state of the ZF that results from execution of the previous instruction is tested
for 0. If CX is not equal to 0 and ZF equals 0, a jump is initiated to the location specified with the short-label operand and the loop continues. If either CX or ZF=0 the loop is
complete and the instruction following the loop instruction is executed.
Syntax
• LOOPE / LOOPZ short-label

• PUSH AND POP INSTRUCTIONS:
•
• • Syntax of PUSH:
PUSH source
Where source is either imm8, imm16, imm32, segment register, 16- or 32-bit general purpose
register. If source is imm8, then the value is zero or sign extended to 16-bits.
• Syntax of POP:
POP destination
Where destination is either mem16, mem32, segment register, 16- or 32-bit general purpose
register.
•
Examples:
• PUSH A pushes the 16-bit general purpose registers in the order AX, CX, DX, BX, SP, BP,
SI, and DI.
POP A pops the 16-bit general purpose registers in the reverse order of PUSH A.
•

• Assembler Directives
• An assembler directive is a message to the assembler that tells the assembler something it needs to know in order to carry out the assembly process; for
example, an assemble directive test the assembler where a program is to be located in memory.To distinguish them from other instructions, directive names
begin with a period.
• The assembler directives fall into the following categories:
• Compiler-Use-Only Directives
• Data Storage Directives
• Location Control Directives
• Symbol Declaration Directives
• Routine Entry Point Definition Directives
• Repeat Block Directives
• Assembler Option Directive (.set)
• Procedure Attribute Directives
• Version Control Directive (.verstamp)
• 1. ASSUME segment register: name [, segment register: name]
Tells the assembler to associate a segment register with the segment name.
Example:
ASSUME CS:CODE, DS:DATA
2. SEGMENT Directive
Assembly language program consists of one or more segment. The segment directive helps the programmer to organize the segments.
• Syntax
name SEGMENT [align] [combine] [‘class’]
………..
………
name ENDS
• Where name is the name of the segment.
3. TITLE directive
This causes a title for a program to print on line 2 of each line of the page.
TITLE text

• 4. PROC directive
The code segment may consist of one or more procedures. The procedures can be defined using the PROC directive, which ends with ENDP directive.
Syntax
name PROC [type]
…..
….
RET
name ENDP
Where name is the name of the procedure, which must be unique. The type specified may be FAR/NEAR . NEAR means the statement that calls the procedure
remains in the same segment as the procedure itself. If FAR means that the calling statement is in different segment. By default NEAR is assumed.
An example of an assembler directive is
MAIN PROC
…..
…..
MAIN ENDP
MAIN is the name, and the operation field contains PROC. This particular directive creates a procedure called MAIN.
• 5. END directive
The END directive ends the entire program and it appears as the last statement.
Syntax
END
• 6. EQU directive
To assign a name to a constant, we can use the EQU (equates) directive.
Syntax
Name EQU numeric value
Name EQU <string>
The assembler replaces each occurrence of the name by the number or string. no memory is allocated for EQU names.
Example
A EQU 10
PMT EQU ‘Type a line of text$’

DB and DW
• Directive Name :
• PAGE
• Syntax :
• PAGE[LENGTH][]
• Uses :
• Designates the maximum number of lines to list on a page and the maximum number of characters on aline.
• Example:
• PAGE 50 132
• ie., Page contains 50 lines and 132 characters per line.
•
•
• TITLE
•
• Syntax :
• TITLE text
•
• Uses :
• To cause a title for a program.Maximum of 60 characters are allowed as title
• Example:
• TITLE EX01

Page & title
• Directive Name :
• PAGE
• Syntax :
• PAGE[LENGTH][]
• Uses :
• Designates the maximum number of lines to list on a page and the maximum number of characters on aline.
• Example:
• PAGE 50 132
• ie., Page contains 50 lines and 132 characters per line.
•
• Directive Name:
• TITLE
•
• Syntax :
• TITLE text
•
• Uses :
• To cause a title for a program.Maximum of 60 characters are allowed as title
• Example:
• TITLE EX01

• Macros
A macro is a block of text that has been given a name. When MASM encounters the name the name during
assembly, it inserts the block into the program. The text may consist of instructions, pseudo-ops, comments, or
references to other macros
Macros are especially useful for carrying out tasks that occur frequently.
Syntax
macro-name MACRO d1,d2,….,dn
Statements
ENDM
• Example :
A macro to return to DOS
DOS_RTN MACRO
MOV AH, 4CH
INT 21H
ENDM
We can use this name DOS_RTN in the place where we want to exit to DOS.
• Difference between Macro and Procedure
A procedure is called at execution time; control transfers to the procedure and returns after executing its
statements.
A macro is invoked at assembly time. The assembler copies the macro’s statements into the program at the
position of the invocation. When the program executes, there is no transfer of control.

There are two types of interrupts:
• non mask-able (NMI)
– Could not be masked
– Jump to 0066H of memory
• mask-able(INT)
– Has 3 mode
– Can be set with the IM x Instruction
– IM 0 sets Interrupt mode 0

Interrupt Modes
• Mode 0:
– An 8 bit opcode is Fetched from Data BUS and executed
– The source interrupt device must put 8 bit opcode at data bus
– 8 bit opcode usually is RST p instructions
• Mode 1:
– A jump is made to address 0038h
– No value is required at data bus
• Mode 2:
– A jump is made to address (register I × 256 + value from interrupting
device that puts at bus)
– I is high 8 bit of interrupt vector
– Value is low 8 bit of interrupt vector

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