MIPI DevCon 2016: Implementing MIPI C-PHY
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The document provides a comprehensive overview of MIPI C-Phy, detailing its unique properties, benefits for camera and display interfaces, and technical specifications such as encoding and mapping. It highlights the performance advantages of C-Phy over D-Phy, including reduced power consumption, fewer connections, and flexibility in lane assignments for applications. The roadmap for future advancements and ecosystems surrounding C-Phy are also discussed, showcasing its potential impact on device designs.
![Encoding & Mapping
• 6 Wire States; 5 possible transitions from each.
• log2(5) ≅ 2.3219 bits/symbol are possible,
C-PHY uses 16÷7 ≅ 2.2857 bits/symbol
• Mapping converts 16-bit word to 7 symbols.
• 16 bits ⇒ 216 = 65,535 states,
7 symbols ⇒ 57 = 78,125 states.
• 12,589 states left over; ≅0.0362 bits/symbol are wasted!
• Actually, what’s left over goes to good use! Will explain later.
6
[Flip, Rota,on, Polarity]](https://image.slidesharecdn.com/c-phy-160926050126/85/MIPI-DevCon-2016-Implementing-MIPI-C-PHY-6-320.jpg)
MIPI DevCon 2016: Implementing MIPI C-PHY
- 1. Implementing MIPI C-PHYSM Unique properties of the MIPI C- PHY physical layer and system- level benefits and values for Camera and Display interfaces George Wiley Qualcomm Technologies, Inc.
- 2. MIPI C-PHY • At first glance it seems a bit… unusual! 2
- 3. Summary • MIPI C-PHY, Brief Overview. • Unique properties of the physical layer • Some random but interesting tidbits about C-PHY • Why things are the way they are (beyond the scope of the specs) • (a little bit of “secret sauce”). • MIPI C-PHY Benefits and Value for Camera and Display. • Applications. • Roadmap.
- 4. MIPI C-PHY Brief Overview
- 6. Encoding & Mapping • 6 Wire States; 5 possible transitions from each. • log2(5) ≅ 2.3219 bits/symbol are possible, C-PHY uses 16÷7 ≅ 2.2857 bits/symbol • Mapping converts 16-bit word to 7 symbols. • 16 bits ⇒ 216 = 65,535 states, 7 symbols ⇒ 57 = 78,125 states. • 12,589 states left over; ≅0.0362 bits/symbol are wasted! • Actually, what’s left over goes to good use! Will explain later. 6 [Flip, Rota,on, Polarity]
- 7. Unique Properties of the Physical Layer
- 8. 8
- 9. MIPI C-PHY & MIPI D-PHY Similarities • Close cousins, there are a lot of similarities, and some differences. • Things that are the same (or almost the same): • Document section #’s correspond to the same type of parameters/items. • The D-PHY spec was used as a template for the first C-PHY spec! • LP (Low-Power) Mode is identical, functional definition & electrical specs. • (C-PHY LP Mode has a 3rd wire, but it doesn’t do much.) • Channel models are common between the specs • (Interconnect and Lane Configuration specs are nearly the same.) • PHY-Protocol Interface definition has a lot in-common. • (Many signals are defined using common language.) • Similar High-Speed Mode voltage levels. • A dual-mode C/D-PHY driver or receiver can be built to share the same pins. • Things that are different: • High-Speed Data encoding is completely different. • High-Speed timing specs are unique to C-PHY encoding. 9
- 10. C-PHY & D-PHY Global Timing • Similar signaling going into and out of HS Mode. 10
- 11. C-PHY/D-PHY Pin Sharing • C-PHY & D-PHY can co-exist on the same AP pins. • Mode bit at system boot configures as either C-PHY or D-PHY mode. • Electrical Specs are similar. • Timing/encoding is completely different. • Low-Power Modes in C-PHY & D-PHY are identical. 11
- 12. Mapping Function • Looks really complicated, but it’s not. • For a human: it’s complicated. For a circuit implementation: it’s easy. • For human understanding, an intuitive mapping could have been: • A base-5 number representation. (But base-5 would be a more complex circuit.) • The C-PHY Mapper implementation: • Has no arithmetic operations, no carry or look-ahead. • Reduces to simple combinatorial logic, no states. • Can be pipelined easily. • The spacing of unused code words is convenient for other functions. (a topic for another day) • A complete implementation using 4-to-1 muxes and small look-up table is provided in the spec. • Or just plug the diagram on the right into logic synthesis to create the RTL. 12
- 13. Why the Mapper? • Hypothetically, let’s explore this… • Assume we had used only 4 states per symbol instead of 5. • Translation of symbols to words becomes trivial. • Each symbol would encode 2 bits ⇒ 8 symbols represent 16 bits • Hypothetical case would be 8 symbols that represent 16 bits • Instead of 7 symbols that represent 16 bits • Would have many more unused states & wasted capacity • Log2(5) – 2 ≅ 0.3219 bits/symbol would be lost; • Instead of Log2(5) - (16/7) ≅ 0.0362 bits/symbol currently unused. • Increase link capacity by more than 14%, at the cost of: • Some digital circuits that perform the mapping function. A good tradeoff! 13
- 14. C-PHY Triggered Eye Concept • Trigger at first zero-crossing of AB, BC or CA. • The right-most point of the eye interior aligned with the first zero crossing trigger point. (First Transition) • Capture the received data in the Rx just prior to the trigger point. • 1, 2 or 3 Transitions at each UI boundary. • When 2 or 3 Transitions, they are often staggered in time. Caused by: • 2-Transition case: Weak-to-Strong & Strong-to-Weak. • Slight differences in rise and fall times between the three signals of the lane (DCD), and ISI. • Slight differences in signal propagation times between the combinations of signal pairs received (e.g. A-B, B-C, and C-A). 14 An “ideal” view: without ISI or DCD.
- 15. Symbol Clock Recovery • Clock edge is at the first zero-crossing (the Trigger Point). • Ignore subsequent edges in the same UI. • Zero-crossings following the first zero-crossing are ignored. • (For 2 or 3 Transition symbols, only the 1st transition is used for clock recovery.) • Data is sampled just prior to the Trigger Point. 15
- 16. Properties of the Preamble • The first field of the burst. • All 3’s. Single-transition symbols. • Simplifies Clock Recovery start-up. 16
- 17. Inter-Lane Skew Impact • Clock timing embedded in each Lane. Tolerant of Inter-Lane skew. • Small elastic buffer facilitates data alignment. • Important characteristic for Lane grouping flexibility. 17
- 18. Built-in Test Capability • 19 pages in the C-PHY spec dedicated to built-in test (of 140p total) • Control/status register definitions, PRBS definitions, test data sequence definitions and examples.
- 19. Built-in Test Registers • Detailed Register Definitions, per-Lane and Global Registers • But physical access to registers is the system designer’s choice. • Register functions are standardized, but layer to access the registers can be defined based on product requirements/convenience. • Control: Select test or normal operation, select PRBS & starting seed, define debug pattern. • Read: burst status, word or symbol error count, first error location.
- 20. Example, Test Configurations • Showing a variety of different methods to access the test registers.
- 22. D-PHY Common-Mode Filter • Differential filter, shown for comparison purposes. • Filter attenuates common-mode noise, but not the differential signal. 22
- 23. C-PHY Common-Mode Filter • Similar general concept as the differential common-mode filter, but magnetics are different. 23
- 24. MIPI C-PHY Benefits & Value
- 25. MIPI C-PHY Benefits • Performance (bit rate 2.28x the signaling rate, e.g. 1Gsym/s = 2.28Gbps) • Pins • Enables fewer pins/balls on AP (due to higher performance and flexibility) • Coexists on same pins with existing D-PHY. • Flexibility • Embedded clock enables assigning lanes to any port on the AP (flexible Lane (trio) to camera ISP mapping and display link mapping. • Power • Qualcomm simulations/measurements show about a 20-50% power reduction for Tx+Rx, depending on configuration. • Interference (Low Emissions) • Embedded clock eliminates clock spur emissions. • Built-in Test • Extensive built-in test capability.
- 26. C-PHY System Benefits, Display Example At the Same Link Rate, C-PHY has: • 40% fewer connections • 12.5% Lower Toggle Rate/Lane • Lower Power Consumption • No Emissions from a Clock Lane
- 27. Flexibility to Reassign Lanes • C-PHY Lanes (Trios) easily reconfigured to different AP Links. • Since C-PHY has embedded clock, there’s no limitation to associate data lanes with a clock lane. • Easy to mux PHY Lanes (Trios) to Lane Merge/Distribution functions in Protocol Layer. • Can choose allocation of Lanes (Trios) to Links via register configuration. 27 2 Links of 3-trios 2 Links of 4-Lanes 3 Links: 1L, 2L & 4L 1 Link of 4 1 Link of 2 2 Links of 2 2 Links of 1 1 Link of 3 1 Link of 2 1 Link of 1
- 28. Camera Example - Pins, Power & Speed • C-PHY v1.0, D-PHY v1.2. • Savings of pins, power, or link rate reduction. Current savings is Tx & Rx combined.
- 29. Camera Example - Pins, Power & Speed • C-PHY v1.1, D-PHY v2.0. • Savings of pins, power, or link rate reduction. Current savings is Tx & Rx combined.
- 30. C-PHY Low Emissions • No clock interference due to embedded clock • No observable emissions/EMI due to non-differential signaling • A few simple configurations of D-PHY and C-PHY were evaluated for emissions • Lanes routed on a board, in close proximity to WWAN Antenna • For comparison purposes only, as Absolute levels depend on many complex conditions in a real device • Higher emissions from the D-PHY clock lane correlates with real-world designs
- 32. Drone Camera Connection Example • One 20 Mpixel main camera (2 Lanes, 6 wires). • 8 navigation cameras (1 Lane each, 3 wires each). 10 Lanes Total
- 33. The Trend to Fewer Pins • The conventional MIPI D-PHY Link configuration has been 4 Data + 1 Clock. • 10 pins total. • Reduction to 6 pins • A majority of 10 to 20 Mpixel image sensors can be supported using 1 or 2 C-PHY Lanes. • Low-res image sensors that have sensitivity to high channel rates can be supported using 2 Lanes. 33
- 35. C-PHY Feature Roadmap Copyright © 2016 MIPI Alliance. All rights reserved. Category Feature v1.0 v1.1 v1.2 next Board Adop,on 4Q14 1Q16 ~4Q16 Target Speed Symbol Rate (Gsps/Lane) * 2.5 2.8 ~3.5 Symbol Rate C-PHY/D-PHY Unified Channel Models ! ! ! Tx Timing by Tx Eye Diagram ! ! ! Basic Pre-emphasis ! ! ! PVT CalibraDon for Rx ! ! AddiDonal UI JiJer (RCLK jiJer) specs ! ! Pre-emphasis/De-emphasis, Gen 2 ! ! Technology Enhancements to Increase the Symbol Rate ! Power ReducDon Unterminated Mode ! ! ! Reduced Amplitude HS Mode opDon (same VOD as D-PHY) ! ! LP Mode Alternate Low-Power Mode ! ! Enhanced FuncDon Co-exists with D-PHY on same device pins ! ! ! ! Track D-PHY SG Ac,vity to Keep C/D-PHY Specs In-Sync ! ! ! ! 16-bit/32-bit PPI ! ! ! Op,cal Interconnect ! ! ! HS Reverse Mode ! ! Low Latency Delimiter (LLPD), for Camera ! ! Various Func,onal Enhancements Planned ! * The stated Symbol Rate is with the Standard Channel except v1.0 which is the rate with the Legacy Channel
- 36. Summary
- 37. C-PHY Ecosystem • Application Processor companies • Qualcomm, others in development • Image Sensors • OmniVision, Sony, others in development • Display Driver ICs • In development • Test equipment companies • Introspect, Keysight, Tektronix, The Moving Pixel Company, others in development • Silicon IP • In development • System components • Common-mode filters: Murata, Panasonic, TDK • C-PHY switches
- 38. Summary • Satisfies all KPI’s… • Pins (Cost), Architectural Flexibility, Performance, Power, Low Emissions • Suitable for all product tiers • C/D-PHY combo into high tier products first, now migrating to mid and low-tiers.
- 39. Thank You
- 40. Backup Material
- 41. CSI-2 and DSI/DSI-2 Ecosystems • Protocol specs, CSI-2 and DSI (now DSI-2) reference C-PHY & D-PHY. • Huge existing ecosystems for Camera and Display are preserved. • Camera & Display protocol specs have been updated to include C-PHY. 41
- 42. CSI-2 and DSI-2 Details • How Camera & Display protocol specs reference both PHY’s. • Low-Level packet header formats are a little different for C-PHY vs. D-PHY. • Application-Specific Payloads of the Packets are identical. 42