module-4_sent to students computer organization.pptx

COMBINATIONAL AND
SEQUENTIAL LOGIC
CIRCUITS(CONTD)
Module 4

• Communication is possible over the air (radio frequency), using a
physical media (cable), and light (optical fiber). All mediums are
capable of multiplexing.
• When multiple senders try to send over a single medium, a device
called Multiplexer divides the physical channel and allocates one to
each. On the other end of communication, a De-multiplexer receives
data from a single medium, identifies each, and sends to different
receivers.

Multiplexing VS No Multiplexing

• Multiplexer(MUX) is a device(combinational logic circuit) that allows
digital signals from several sources to be routed onto a single line of
output.
• This can act as a digital switch
• It has several input lines and a single output line.
• It has also data selector lines which specifies which input signal has to
be switched to the output line.
• Since there are ‘n’ selection lines, there will be 2n
possible
combinations of zeros and ones. So, each combination will select only
one data input. Multiplexer is also called as Mux.

• A 4-input multiplexer has two data-selector lines a combination of
which are used to select any of the four data-input lines.
• Logic symbol of a 4-input MUX is shown in figure.

4 x 1 MUX
D2
D3
D1
D0
S0
S1
Y
2n
input lines
n- Selection lines
Output of MUX depend upon Selection lines
MSB
LSB

• If a binary 0 is applied to the data-selector lines, the data on input
D0 appear on the data-output line. If a binary 1 is applied to the data-
selector lines, the data on input D1 appear on the data-output line. If a
binary 2 is applied to the data-selector lines, the data on input
D2 appear on the data-output line. If a binary 3 is applied to the data-
selector lines, the data on input D3 appear on the data-output line.
D3
D2
D1

The total expression for the data output is
This can be implemented using four 3-input AND gates, a 4-input OR gate, and two inverters as shown in the
figure.

8-input Multiplexer
An 8-input multiplexer has three data-selector
lines a combination of which is used to select any
of the eight data-input lines.
Logic symbol of a 8-input MUX is shown in figure.

Higher-Order MUX Using Lower Order MUX

Implementation of Higher-order Multiplexers
• Now, let us implement the following two higher-order Multiplexers using
lower-order Multiplexers.
• 8x1 Multiplexer
• 16x1 Multiplexer
• implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We
know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one
output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines and
one output.
• So, we require two 4x1 Multiplexers in first stage in order to get the 8 data
inputs. Since, each 4x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as
inputs and to produce the final output.

• Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection
lines s2, s1 & s0 and one output Y. The Truth table of 8x1 Multiplexer is
shown below.
8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We know
that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1 Multiplexer has 8
data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since, each 4x1
Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by considering the
outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and one output Y.
The Truth table of 8x1 Multiplexer is shown below.

We can implement 8x1 Multiplexer
using lower order Multiplexers easily
by considering the above Truth table.
The block diagram of 8x1 Multiplexer
is shown in the following figure.

• The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data
inputs of upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1
Multiplexer are I3 to I0. Therefore, each 4x1 Multiplexer produces an output based on
the values of selection lines, s1 & s0.
• The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer
that is present in second stage. The other selection line, s2 is applied to 2x1
Multiplexer.
• If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to
I0 based on the values of selection lines s1 & s0.
• If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to
I4 based on the values of selection lines s1 & s0.
• Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer
performs as one 8x1 Multiplexer.

16x1 Multiplexer
• In this section, let us implement 16x1 Multiplexer using 8x1 Multiplexers
and 2x1 Multiplexer. We know that 8x1 Multiplexer has 8 data inputs, 3
selection lines and one output. Whereas, 16x1 Multiplexer has 16 data
inputs, 4 selection lines and one output.
• So, we require two 8x1 Multiplexers in first stage in order to get the 16 data
inputs. Since, each 8x1 Multiplexer produces one output, we require a 2x1
Multiplexer in second stage by considering the outputs of first stage as
inputs and to produce the final output.
• Let the 16x1 Multiplexer has sixteen data inputs I15 to I0, four selection lines
s3 to s0 and one output Y. The Truth table of 16x1 Multiplexer is shown
below.

We can implement 16x1
Multiplexer using lower
order Multiplexers easily by
considering the above
Truth table. The block
diagram of 16x1
Multiplexer is shown in the
following figure.

• The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The
data inputs of upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower
8x1 Multiplexer are I7 to I0. Therefore, each 8x1 Multiplexer produces an
output based on the values of selection lines, s2, s1 & s0.
• The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1
Multiplexer that is present in second stage. The other selection line, s3 is
applied to 2x1 Multiplexer.
• If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs
Is7 to I0 based on the values of selection lines s2, s1 & s0.
• If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I15 to
I8 based on the values of selection lines s2, s1 & s0.
• Therefore, the overall combination of two 8x1 Multiplexers and one 2x1
Multiplexer performs as one 16x1 Multiplexer.

De-Multiplexer
The De-Multiplexer is a combinational logic circuit that
performs the reverse operation of multiplexer (Several
output lines, one input line).
De -Multiplexer means one to many. A De-Multiplexer
is a circuit with one input and many output. By applying
control signal, we can steer any input to the output. Few
types of De -Multiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to
16 De -Multiplexer .
De-Multiplexer is the process of taking information
from one input and transmitting the same over one of
several outputs.

• De-Multiplexer is a combinational circuit that performs the reverse
operation of Multiplexer. It has single input, ‘n’ selection lines and
maximum of 2n
outputs. The input will be connected to one of these
outputs based on the values of selection lines.
• Since there are ‘n’ selection lines, there will be 2n
possible
combinations of zeros and ones. So, each combination can select only
one output. De-Multiplexer is also called as De-Mux.

• One input and many output
• Reverse operation of Multiplexer
• One to many circuit or data distributer
• Enable is 0- no output

1x4 De-Multiplexer
• 1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and
four outputs Y3, Y2, Y1 &Y0. The block diagram of 1x4 De-Multiplexer is
shown in the following figure.
The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of selection
lines s1 & s0.

• The Truth table of 1x4 De-Multiplexer is shown below.
From the above Truth table, we can directly write the Boolean functions for each output as

• We can implement these Boolean functions using Inverters & 3-input
AND gates. The circuit diagram of 1x4 De-Multiplexer is shown in the
following figure.
We can easily understand the operation of the above circuit. Similarly, you can implement 1x8 De-Multiplexer
and 1x16 De-Multiplexer by following the same procedure.

Implementation of Higher-order De-Multiplexers
• Now, let us implement the following two higher-order De-Multiplexers
using lower-order De-Multiplexers.
• 1x8 De-Multiplexer
• 1x16 De-Multiplexer

1x8 De-Multiplexer
• In this section, let us implement 1x8 De-Multiplexer using 1x4 De-
Multiplexers and 1x2 De-Multiplexer. We know that 1x4 De-Multiplexer has
single input, two selection lines and four outputs. Whereas, 1x8 De-
Multiplexer has single input, three selection lines and eight outputs.
• So, we require two 1x4 De-Multiplexers in second stage in order to get the
final eight outputs. Since, the number of inputs in second stage is two, we
require 1x2 DeMultiplexer in first stage so that the outputs of first stage will
be the inputs of second stage. Input of this 1x2 De-Multiplexer will be the
overall input of 1x8 De-Multiplexer.
• Let the 1x8 De-Multiplexer has one input I, three selection lines s2, s1 &
s0 and outputs Y7 to Y0.

1x8 De-Multiplexer using lower order Multiplexers

1x16 De-Multiplexer
• Implement 1x16 De-Multiplexer using 1x8 De-Multiplexers and 1x2 De-
Multiplexer. We know that 1x8 De-Multiplexer has single input, three
selection lines and eight outputs. Whereas, 1x16 De-Multiplexer has single
input, four selection lines and sixteen outputs.
• So, we require two 1x8 De-Multiplexers in second stage in order to get the
final sixteen outputs. Since, the number of inputs in second stage is two, we
require 1x2 DeMultiplexer in first stage so that the outputs of first stage
will be the inputs of second stage. Input of this 1x2 De-Multiplexer will be
the overall input of 1x16 De-Multiplexer.
• Let the 1x16 De-Multiplexer has one input I, four selection lines s3, s2, s1 &
s0 and outputs Y15 to Y0.

The block diagram of 1x16
De-Multiplexer using lower
order Multiplexers
Exercise
Draw the truth table and logic diagram of
1 x 16 De-Mux

• Decoder is a combinational circuit that has ‘n’ input lines and
maximum of 2n
output lines. One of these outputs will be active High
based on the combination of inputs present, when the decoder is
enabled. That means decoder detects a particular code. The outputs
of the decoder are min terms of ‘n’ input variable lines when it is
enabled.

Difference between Decoder and De-Multiplexer.
Sr. No. Key Decoder De-Multiplexer
1
Purpose A Decoder decodes an encrypted input
signal to multiple output signals from one
format to another format.
A De-Multiplexer routes an input signal to
multiple output signals.
2
Input/Output A Decoder has 'n' input lines and maximum
of 2n
output lines.
A De-Multiplexer has single input, 'n'
selection lines and maximum of 2n
outputs.
3
Inverse Decoder's inverse is Encoder. De-Multiplexer's inverse is Multiplexer.
4
Usage Decoder is used to detect bits, encoding of
data.
De-Multiplexer is used in switching, data
distribution.
5
Select Lines Decoder has no select lines. De-Multiplexer contains select lines.
6
Application Decoder is heavily used in networking
applications.
De-Multiplexer is employed in
communication systems.

2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 &
Y0. The block diagram of 2 to 4 decoder is shown in the following
figure.
One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’. The Truth
table of 2 to 4 decoder is shown below.

From Truth table, we can write the Boolean functions for each output as
Y3=E.A1.A0
Y2=E.A1.A0′
Y1=E.A1′.A0
Y0=E.A1′.A0′
Each output is having one product term. So, there are four
product terms in total. We can implement these four
product terms by using four AND gates having three inputs
each & two inverters. The circuit diagram of 2 to 4
decoder is shown in the following figure.

Therefore, the outputs of 2 to 4 decoder
are nothing but the min terms of two
input variables A1 & A0, when enable, E
is equal to one. If enable, E is zero,
then all the outputs of decoder will be
equal to zero.
Similarly, 3 to 8 decoder produces eight
min terms of three input variables A2,
A1 & A0 and 4 to 16 decoder produces
sixteen min terms of four input
variables A3, A2, A1 & A0.

Implementation of Higher-order Decoders
• Now, let us implement the following two higher-order decoders using
lower-order decoders.
• 3 to 8 decoder
• 4 to 16 decoder

3 to 8 Decoder
In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know
that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas,
3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
We can find the number of lower order decoders required for implementing
higher order decoder using the following formula.
Required number of lower order decoders=m2/m1
Where,
m1 is the number of outputs of lower order decoder.
m2 is the number of outputs of higher order decoder.
Substitute, these two values in the above formula.
m1 = 4 and m2 = 8
Required number of 2 to 4 decoders=8/4=2

Therefore, we require two 2 to 4 decoders for
implementing one 3 to 8 decoder. The block
diagram of 3 to 8 decoder using 2 to 4 decoders is
shown in the following figure.
The parallel inputs A1 & A0 are
applied to each 2 to 4 decoder. The
complement of input A2 is
connected to Enable, E of lower 2
to 4 decoder in order to get the
outputs, Y3 to Y0. These are
the lower four min terms. The
input, A2 is directly connected to
Enable, E of upper 2 to 4 decoder
in order to get the outputs, Y7 to Y4.
These are the higher four min
terms.

4 to 16 Decoder
• In this section, let us implement 4 to 16 decoder using 3 to 8
decoders. We know that 3 to 8 Decoder has three inputs A2, A1 &
A0 and eight outputs, Y7 to Y0. Whereas, 4 to 16 Decoder has four
inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0
• We know the following formula for finding the number of lower order
decoders required.
Required number of 3 to 8 decoders = 16/8 =2

Therefore, we require two 3 to 8 decoders for implementing one 4 to
16 decoder. The block diagram of 4 to 16 decoder using 3 to 8 decoders
is shown in the following figure.
The parallel inputs A2, A1 & A0 are applied to
each 3 to 8 decoder. The complement of
input, A3 is connected to Enable, E of lower
3 to 8 decoder in order to get the outputs,
Y7 to Y0. These are the lower eight min
terms. The input, A3 is directly connected to
Enable, E of upper 3 to 8 decoder in order
to get the outputs, Y15 to Y8. These are
the higher eight min terms.

Sequential circuit Design
- Flip-flop and Latches

Block diagram of sequential circuit
This sequential circuit contains a set of inputs and outputs ‘s’. The outputs ‘s’ of sequential circuit depends
not only on the combination of present inputs but also on the previous outputs ’s’. Previous output is nothing
but the present state. Therefore, sequential circuits contain combinational circuits along with
memory storage elements. Some sequential circuits may not contain combinational circuits, but only
memory elements.

Differences between combinational circuits
and sequential circuits.
Combinational Circuits Sequential Circuits
Outputs depend only on present inputs. Outputs depend on both present inputs and
present state.
Feedback path is not present. Feedback path is present.
Memory elements are not required.
Memory elements are required.
Clock signal is not required. Clock signal is required.
Easy to design. Difficult to design.

Clock signal
Clock signal is a periodic signal and its ON time and OFF time need not be the same. We can
represent the clock signal as a square wave, when both its ON time and OFF time are same. This
clock signal is shown in the following figure.

A Latch is a special type of logical circuit. The latches have low and high two stable states. A latch is a
storage device that holds the data using the feedback lane. The latch stores 1 -bit until the device set to
1. The latch changes the stored data and constantly trials the inputs when the enable input set to 1.
Latches are single bit
storage elements which are
widely used in computing as
well as data storage. Latches
are used in the circuits like
power gating & clock as a
storage device.
Latches are the smallest
building blocks of memory.
They are used in other circuits,
like flip-flops and shift registers
and they'll apply the input(s) to
their output as long as they are
enabled.

• A flip-flop is a sequential digital electronic circuit having two stable
states that can be used to store one bit of binary data. Flip-flops are
the fundamental building blocks of all memory devices.
• A Flip-flop is a clock-controlled memory device.
• Types of Flip–Flops
• S-R flip-flop
• J-K flip-flop
• D flip-flop
• T flip-flop
Flip-Flop

Counters
• Counter – is essentially a register that goes through a predetermined
sequence of states

What are registers?
Register – is a group of flip-flops. Its basic function is to hold information within a digital system
so as to make it available to the logic units during the computing process.
• A register is a group of flip-flops used to store binary information. An n-bit register can store n-
bit information
• A register which is able to shift the information either from left to right (Division) or from right
to left (Multiplication) is called a shift register.
• Shift register can perform four different operations.
1. Serial input Parallel output ( SIPO)
2. Serial input Serial output (SISO)
3. Parallel input Parallel output (PIPO)
4. Parallel input Serial output (PISO)
Registers

Serial In − Serial Out (SISO) Shift Register The shift register, which allows serial
input and produces serial output is
known as Serial In – Serial
Out SISO shift register. The number of
bits that can be shifted out before the
next bit arrives depends on the speed
of the clock signal that controls the
operation of the shift register.
The block diagram of 4-bit SISO shift
register is shown in figure.

SISO Shift Register Circuit Diagram
We know that the input in this type of shift register is serially fed whereas the output is received in a serial way. The
SISO shift register circuit diagram is shown below where the D FFs like D0 to D3 are connected serially as shown in
the following diagram.
Wave Form representation

Working of SISO Shift Register
• The circuit must be set to reset mode so the output of every register will be ‘0’, so the output provided by all the
registers will be “0000”.
• In this 4-bit shift register example like “1111”, the LSB bit is ‘1’ and the MSB bit is ‘1’. First, the high signal (LSB
bit) is used as an input to the first D3 flip flop, then D3=1. But primarily all the D FFs outputs will be 0. So,
D2=D1=D0=0. When D3 input is high signal (1) then D3 will cause ‘Q3’ to be ‘1’. Therefore the overall o/p for 1st
falling edge will become 1000.
• Similarly, when the next data i/p bit in the above 4-bit like high signal (1) is given at flip flop D3, again this ‘D3’
will cause ‘Q3’ to be 1, however, ‘Q3’ is given as input to FF ‘D2’. So, this ‘D2’will cause ‘Q2’ to be 1 when all the
remaining outputs will become 0.
• As a result, we will obtain ‘11’ for a 2nd falling edge; so will obtain ‘11’ at the stored bit in the shift register, thus
the overall o/p for the 2nd falling edge will get o/p as“1100”.
•
When the third input bit like high signal (1) is applied at the ‘D3’ FF then earlier ‘Q2’ o/p will cause the ‘D1’ i/p to
be ‘0’. This will give the output Q3, Q2 & Q1 as ‘1’ whereas ‘Q0’ will be ‘0’. So the overall o/p for the 3rd falling
edge will get o/p as “1110”.
• In addition, an MSB bit like high signal (1) is given as input, after that ‘1’ at ‘Q1’ will cause input ‘D0’ to be ‘1’,
thus, this will make ‘Q0’ be ‘1’. Therefore, finally, SISO shift register store 1111 bit & shows in the o/p.

In the waveform representation, the 1st waveform is the CLK i/p signal whereas the
2nd waveform shows the data i/p to be stored as ‘1111’.
So the waveform will be a constant high signal. In addition, the above-shown
waveform will represent the 4 data o/p of the FFs.
Firstly, all the FFs o/ps were ‘0’ which is very clearly given in the above representation
of the waveform. But, the ‘Q3’ output will vary from ‘0’ to ‘1’ once the 1st CLK signal
arrives while the remaining o/ps are still ‘0’.
In this way, the 2nd CLK signal ‘Q2’ will vary from ‘0’ to ‘1’. As a result, both ‘Q2’ & ‘Q3’
will show logic high within the above waveform.
That how a SISO shift register operates.
Once the 4th CLK signal arrives then all the four registers outputs will become ‘1’.
So the storage can be performed by shifting each bit on the arrival of every CLK signal
so it is called a SISO shift register.

Serial In - Parallel Out (SIPO) Shift Register
The shift register, which allows
serial input and produces parallel
output is known as Serial In –
Parallel Out SIPO shift register.
The block diagram of 4-bit SIPO
shift register is shown in figure.
The SISO shift register circuit diagram is shown below. This circuit can be built with 4 D flip-flops which are
connected as shown in the diagram where the CLR signal is given additionally to the CLK signal to all FFs o
RESET them. In the above circuit, the first FF output is given to the second FFs input. All these four D flip-flops
are connected with each other serially because the same CLK signal is given to every flip-flop.

Working of SIPO Shift Register
Timing Diagram of SIPO Shift
Register

Working of SIPO Shift Register
• The working of the SIPO shift register is; that it takes the serial data input from the first flip flop of the left side and
generates a parallel data output. The 4-bit SIPO shift register circuit is shown below. The operation of this shift
register is, first all the flip flops from the circuit from FF1 to FF4 have to RESET so that all the outputs of FFs like
QA to QD will be at logic zero level so there is no parallel data output.
• The construction of the SIPO shift register is shown above. In the diagram, the first flip flop output ‘QA’ is
connected to the second flip flop input ‘DB’. The second flip flops output ‘QB’ is connected to the third flip flops
input DC, and the third flip flops output ‘QC’ is connected to the fourth flip flops input ‘DD. Here, QA, QB, QC, and
QD are data outputs.
• Initially, all the output will become zero so without CLK pulse; all the data will become zero. Let’s take a 4-bit data
input example like 1101. If we apply the first clock pulse ‘1’ to the first flip flop, the data to be entered into the FF
and QA becomes ‘1’, and remaining all the outputs like QB, QC and QD will become zero. So the first data output
is ‘1000
• If we apply the second clock pulse as ‘0’ to the first flip flop then QA becomes ‘0’, QB becomes ‘0’, QC becomes
‘0’ and QD becomes ‘0’. So the second data output will become ‘0100’ due to the shift right process.
• If we apply the third clock pulse as ‘1’ to the first flip flop then QA becomes ‘1’, QB becomes ‘0’, QC becomes ‘1’
and QD becomes ‘0’. So the third data output will become ‘1011’ due to the shift right process.
If we apply the fourth clock pulse as ‘1’ to the first flip flop then QA becomes ‘1’, QB becomes ‘1’, QC becomes ‘0’
and QD becomes ‘1’. So the third data output will become ‘1101’ due to the shift right process

• Timing Diagram –
• Here we are using a positive edge CLK i/p signal. In a first clock pulse
the input data becomes QA = ‘1’ and all other values like QB, QC, and
QD become ‘0’. So the output will become ‘1000’. In the second clock
pulse, the output will become ‘0101’. In the third clock pulse, the
output will become ‘1010’ and in the fourth clock pulse, the output
will become ‘1101’.

Parallel In − Serial Out (PISO)Shift Register
The shift register, which allows parallel input
and produces serial output is known as
Parallel In − Serial Out PISO shift register.
The block diagram of 3-bit PISO shift
register is shown in figure.
This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is
connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the
same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For
every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get
the serial output from the right most D flip-flop.

Example
Let us see the working of 3-bit PISO shift register by applying the binary information “011” in parallel
through preset inputs.
Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops from
leftmost to rightmost will be Q2Q1Q0=011.
We can understand the working of 3-bit PISO shift register from the following table.
No of positive
edge of Clock
Q2 Q1 Q0
0 0 1 1 LSB
1 - 0 1
2 - - 0 LSB
Here, the serial output is coming from Q0. So,
the LSB 11 is received before applying
positive edge of clock and the MSB 0 is
received at 2nd
positive edge of clock.
Therefore, the 3-bit PISO shift register
requires two clock pulses in order to produce
the valid output. Similarly, the N-bit PISO
shift register requires N-1 clock pulses in
order to shift ‘N’ bit information.

The shift register, which allows parallel input and produces parallel output is known as
Parallel In − Parallel Out PIPOPIPO shift register. The block diagram of 3-bit PIPO shift register is shown in the following figure.
Parallel In - Parallel Out (PIPO) Shift Register
This circuit consists of three D flip-flops, which are
cascaded. That means, output of one D flip-flop is
connected as the input of next D flip-flop. All these
flip-flops are synchronous with each other since, the
same clock signal is applied to each one.
In this shift register, we can apply the parallel
inputs to each D flip-flop by making Preset Enable to
1. We can apply the parallel inputs through preset or
clear. These two are asynchronous inputs. That
means, the flip-flops produce the corresponding
outputs, based on the values of asynchronous
inputs. In this case, the effect of outputs is
independent of clock transition. So, we will get
the parallel outputs from each D flip-flop.

Example
Let us see the working of 3-bit PIPO shift register by applying the binary information “011” in
parallel through preset inputs. Since the preset inputs are applied before positive edge of Clock,
the initial status of the D flip-flops from leftmost to rightmost will be Q2Q1Q0=011.
So, the binary information “011” is obtained in parallel at the outputs of D flip-flops before
applying positive edge of clock. Therefore, the 3-bit PIPO shift register requires zero clock
pulses in order to produce the valid output.
Similarly, the N-bit PIPO shift register doesn’t require any clock pulse in order to shift ‘N’ bit
information.

Counters
Counter is a sequential circuit. Counter is a digital circuit which is used for a counting pulses & is also known as frequency
divider. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters are of
two types according to clock cycle.
Asynchronous counters. (Each flip-flop is applied only to the initial flip flop whose value would be considered as LSB.
Instead of the clock pulse, the output of first flip-flop acts as a clock pulse to the next flip flop, whose output is used as
a clock to the next in line flip-flop and so on.)
Synchronous counters. (Each flip-flop is applied with similar clock pulse)
• Counters can count in two ways
1) Up count(0, 1, 2,….,N) eg: EVM(Electronic voting Machine)
2) Down count(N, N-1, …,1) eg: Space related applications i.e. in rocket launching
• Present state of the counter represents state of the counter
• Counter contains set of flip-flops(integration of flip-flops).
• A ‘n’ bit counter requires ‘n’ flip-flops & 2n
states. Eg:If you taken any 2 bit counter, it requires 4 states (22
)
• Each state frequency= Total frequency of the counter/2n
(2n
- No of states)

Asynchronous
• Asynchronous refers to states that doesn’t have a fixed time relationship with
each other. We are not using similar clock duration. Eg: 2 bit counter requires
2n
states. Each state time duration will be different.
• In asynchronous counters flip flops doesn’t have a common clock pulse.
• So their states doesn’t change exactly at same time
• Not using many generators for clock pulse
• 1st
flip-flop has clock, output of each flip-flop will act as clock to the next flip-
flop in the counter
• Example: Ripple counter

• For making Toggle condition JK flip-flop or T flip flop is used in
Asynchronous counter.
• For making JK flip-flop in Toggle, give high voltage(1).

2-bit Ripple-up-Counter
High Voltage
(Logic 1)
At first given high voltage.
When ever clock pulse occurs , the flip-flop toggle
State of the flip-flop is Q1Q0 (Represents 1) so the state of the flip-flop is first state.
For a 2 bit counter four states. Ie. 22
=4 states. So requires 4 clock pulses. (Considering positive edge triggered pulse)
When clock is not applied(initial stage)
it is in 0 stage
When clock rising it to upper, the first
flip-flop toggle.
Ie. It’s state changes from 0 to 1
2nd
stage, clock pulse Q0 toggle from 1
to 0
When Q0
’
= 1, next flip-flop triggers
At stage 4 flip-flop changes to reset
state.
i.e. stopped counting. It passed all the
stages.
It shows completion of counting.
Previous stage shows maximum value
of counting.
CLK Q1 Q0
0 0 0
1 0 1
2 1 0
3 1 1
4 0 0

2-bit Ripple-down-Counter
CLK Q1 Q0
0 0 0
1 1 1
2 1 0
3 0 1
4 0 0
• Ripple-down counter is an Asynchronous counter that is not having similar clock pulse for every flip-flop integrated in it.
• For a 2 bit counter four states. Ie. 22
=4 states. So requires 4 clock pulses.
• To maintain toggle condition in flip-flops, utilized high voltage for all the flip-flops.
When clock is not applied(initial stage). it is in 0 stage.
When clock rising it to upper, the first flip-flop toggle. Ie. It’s state changes from 0 to 1.
2nd
stage, clock pulse Q0 toggle from 1 to 0
When Q0
’
= 1, next flip-flop triggers. At stage 4 flip-flop changes to reset state.
i.e. stopped counting. It passed all the stages. It shows completion of counting.
Considering positive edge triggered pulse
Considering negative edge triggered pulse

Synchronous counters
• If the "clock" pulses are applied to all the flip-flops in a counter
simultaneously, then such a counter is called as synchronous counter. (Clock
id predefined)
• The inputs for the first flip flop is High(logical 1). Inputs for the second flip-
flop is the output of the first flip-flop
2 bit Synchronous Up Counter

(Considering positive edge triggered pulse)
CLK Q1 Q0
0 0 0
1 0 1
2 1 0
3 1 1
4 0 0
When clock is 0. Q1 and Q0 is also 0.
When clock is 1 or trigged(at initial stage), Q0 toggle from 0 to 1.
The 2nd
flip-flop is in the state 0(J) and K(0) as input and there is no toggle is carrying out. So the state of the second flip-flop is
not changing. The value of output 1 from Q0 is available for the second flip-flop in the next clock pulse. Why second flip-flop
is not changing to 1 during 1st
clock pulse. During first edge of the clock pulse we are getting 1 as for first flip-flop and the
second flip flop is having the value 0.
At second rising edge of clock, first flip-flop toggle from 1 to 0 and second flip flop is toggle from 0 to 1 due to the input 1.
At 3rd
clock pulse, first flip-flop changes from 0 to 1 and the second flip flop has no change of values due to 0 input(No change
condition). For next 4th
clock pulse, first flip-flop toggle from 1 to 0 and second flip-flop toggles from 1 to 0. Once obtained
0,0 to Q0 and Q1, counter stops counting.
2-bit Synchronous counters
JK Flip-flop

module-4_sent to students computer organization.pptx

More Related Content

Similar to module-4_sent to students computer organization.pptx (20)

More from earningmoney9595 (7)

Recently uploaded (20)

module-4_sent to students computer organization.pptx