Mpi chapter 2

Chapter two
THE 8086 MICROCONTROLLER
ARCHITECTURE
2
1

 In 1978, Intel came out with the 8086 processor.
 The Intel 8086 is a 16-bit microprocessor,
implemented in N-channel, depletion load, silicon
gate technology
(HMOS), and packaged it in a 40 pin dual in line
package..
2

Features of 8086
1. The 8086 is a 16-bit microprocessor. The term 16-bit” means
that its arithmetic logic unit, internal registers and most of its
instructions are designed to work with 16-bit binary words.
2. The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time. The
8088, however, has an 8-bit data bus, so it can only read data from
or write data to memory and ports 8 bits at a time.
3. The 8086 has a 20-bit address bus, so it can directly access 220
or 10,48,576 (lMB)memory locations. Each of the 10, 48, 576
memory locations is byte wide. Therefore, a sixteen-bit words
are stored in two consecutive memory locations. The 8088 also
has a 20-bit address bus, so it can also address 220 or 10, 48,
576 memory locations. 3

4. The 8086 can generate 16-bit I/O address, hence it can
access 216 = 65536 1/0 ports.
5. The 8086 provides fourteen 16-bit registers.
6. The 8086 has multiplexed address and data bus which
reduces the number of pins needed, but does slow down the transfer
of data (drawback).
7. The 8086 requires one phase clock with a 33% duty cycle to
provide optimized internal timing.
Range of clock rates (refer Fig. 2.1)
are :- 5 MHz for 8086
8 MHz for 8086-2
10 MHz for 8086-1 4

8. The 8086 is possible to perform bit, byte, word and bock
operations in 8086. It performs the arithmetic and logical
operations on bit, byte, word and decimal numbers including
multiply and divide.
9. The Intel 8086 is designed to operate in two modes, namely the
minimum mode and the maximum mode. When only one 8086
CPU is to be used in a microcomputer system, the 8086 is used In
the minimum mode of operation. In this mode the CPU issues the
control signal required by memory and I/O devices.
In multiprocessor (more than one processor in the system) system
8086 operates in maximum mode. In maximum mode, control
signals are generated with the help of external bus controller
(8288). 5

10. The Intel 8086 supports multiprogramming. In
multiprogramming, the code for two or more processes is in
memory at the same time and is executed in a time-multiplexed
fashion.
11. An interesting feature of the 8086 is that it fetches up to six
instruction bytes (4 instruction byte for 8088) from memory and
queue store, them in order to speed up instruction execution.
Later we will discuss this in detail.
12. The 8086 provides powerful instruction set with the following
addressing modes: Register, immediate, direct, indirect through
an index or base, indirect through the sum of a base and an index
register, relative and implied.
6

2.2 Architecture of 8086
• Fig 2.2 shows a block diagram of the 8086 internal architecture. It
is internally divided in to two separate functional units. These are
the Bus Interface Unit (BIU) and the Execution Unit (EU). These
two functional units can work simultaneously to increase system
speed and hence the throughput.
• Throughput is a measure of number of instruction. executed per
unit time.
7

2.2.1 Bus interface Unit [BIU]
• The bus in unit interface unit is the 8086 interface to the outside
world. It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
• The bus interface unit is responsible for performing all external bus
operations, as listed below.
Functions of Bus Interface Unit
1. It sends address of the memory or I/O.
2. It fetches instruction from memory.
3. It reads data from port/memory.
4. It writes data into port/memory.
5. It support instruction queuing.
6. It provides address relocation facility
To implement these functions the BIU contains the instruction queue,
segment register instruction pointer, address summer and bus control
logic.
9

Instruction Queue
• To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
• These prefetched instruction bytes are held for the execution unit In
a group of registers called Queue. With the help of queue it is
possible to fetch next instruction when current instruction is in
execution.
• For example, current instruction in execution is a multiplication
instruction. In 8086, operands for multiplication operations are
within register. Still it requires 100 clock cycles to execute multiply
instruction.
• During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle. The BIU continues this process as long as the queue
is not full.
10

• Due to this, execution unit gets the ready instruction in the queue
and instruction fetch time is eliminated. This is illustrated in Fig.
2.3.
• The queue operates on the principle first in first out (FIFO). So that
the execution unit gets the instructions for execution In the order
they are fetched,
• In case of JUMP and CALL instructions, instruction already
fetched in queue are of no use. Hence, in these cases queue is
dumped and newly formed by loading instructions from new
address specified by JUMP or CALL instruction.
• Feature of fetching the next instruction while the current instruction
is executing is called pipelining.
11

Execution Unit [EU]
• The execution unit of 8086 tells the BIU from where to fetch
instructions or data, decodes instructions and executes
instructions. It contains
Control Circuitry
Instruction Decoder
Arithmetic Logic Unit (ALU)
Register Organization
Flag Register
General Purpose Registers
Pointers and Index Registers
13

Control Circuitry, Instruction Dcoder, ALU
• The control circuitry in the EU directs the internal operations.
• A decoder in the EU translates the instructions fetched from
memory into a series of actions which the EU performs.
• ALU is 16-bit. It can add, subtract, AND, OR, XOR, increment,
decrements, complement and shift binary numbers.
14

Register Organization
• The 8086 has a powerful set of registers. It includes
general purpose registers
segment registers
pointers and index registers, and
flag register.
• The Fig. 2.4 shows the register organization of 8086. It is also
known as programmer’s model of 8086. The registers shown
in programmer’s model are accessible to programmer. As shown
in the Fig. 2.4, all the registers of 8086 are 16-bit registers.
15

General Purpose Registers
• The 8086 has four 16-bit general purpose registers labeled AX, BX, CX and
DX.
• Each 16-bit general purpose register can be split into two 8-bit registers, The
letters L and H specify the lower and higher bytes of a particular register.
• For example, BH means the higher byte (8-bits) of the BX register and BI
means the lower byte (8-bits) of the BX register The letter X is used to
specify the complete 16-bit register.
• The general purpose registers are either used for holding data, variables and
intermediate results temporarily.
• They can also be used as a counters or used for storing offset address for
some particular addressing modes.
• The register AX is used as 16-bit accumulator whereas register AL (lower
byte of AX) is used as 8-bit accumulator.
• The register BX is also used as offset storage for generating physical
addresses in case of certain addressing modes.
• On the other hand, the register CX is also used as a default counter in case of
string and loop instructions.
17

Segment Registers
• The physica1 address of the 8086 is 20-bitš wide to access 1
Mbyte memory locations.
• However, its registers and memory locations which contain
logical addresses are just 16-bits wide.
• Hence 8086 uses memory segmentation. It treats the 1 Mbyte of
memory as divided into segments, with a maximum size of a
segment as 64Kbytes.
• Thus any location within the segment can be accessed using 16
bits. The 8086 allows only four active segments at a time, as
shown in the Fig. 2.5.
• For the selection of the four active segments the 16-bit segment
registers are provided by the bus interface unit BIU) of the 8006.
• These four registers are : Code segment (CS) register, the data
segment (DS) register, the stack segment (SS) register, and the
extra segment (ES) register. 18

• These are used to hold the upper 16-bits of the starting addresses of
the four memory segments. on which 8086 works at a particular
time.
• For example, the value in CS identifies the starting address of 64 K-
byte segment known as code segment. By “starting address”, we
mean the lowest addressed byte in the active code segment.
• The starting address is also known as base address or segment base.
• The BIU always inserts zeros for the lower 4 bits (nibble) in the
contents of segment register to generate 20-bit base address.
• For example, if the code segment register contains 348AH, then code
segment will start at address 348A0H
20

• Functions of Segment Registers
1. The CS register holds the upper 16-bits of the starting address of
the segment from which the BIU is currently fetching the
instruction code byte.
2. The SS register is used for the upper 16-bits of the starting
address for the program stack (all stack related instructions will
operate on stack).
3. ES register and DS register are used to hold the upper 16-bits of
the starting address of the two memory segment which are used
for data.
21

Pointers and Index Registers
• All segment registers are 16-bit wide. But it is necessary to
generate 20-bit address (physical address) on the address bus.
• To get 20-bit physical address one or more pointer or index
registers are associated with each segment register.
• The pointer registers IP, BP and SP are associated with code, data
and stack segments, respectively. They hold the offset within the
code, data and stack segments, respectively.
• The index registers Dl and SI are used as a general purpose
registers as well as for offset storage in case of indexed. based
indexed and relative based indexed addressing modes.
22

Flag Register
• A flag is a flip-flop which indicates some condition produced by the
execution of an instruction or control's certain operations of the EU.
• The flag register contains nine active flags as shown in the Fig. 2.6.
• Six of them are used to indicate some condition produced by instruction.
1. Carry Flag(CF): In case of addition this flag is set if there is a carry out
of the MSB.The carry flag also serves as a borrow flag for subtraction.
In case of subtraction it is set when borrow is needed.
2. Parity Flag (PF): It is set to 1 if result of byte operation or lower byte
of the word operation contain an even number of ones; otherwise it is
zero.
3. Auxiliary Flag (AF):This flag is set if there is an overflow out of bit 3
i.e. , carry from lower nibble to higher nibble (D3 bit to D4 bit). This
flag is used for BCD operations and it is not available for the
programmer. 23

4. Zero Flag (ZF): The zero flag sets if the result of operation in
ALU is zero and flag resets if the result is nonzero. The zero flag
is also set if a certain register content becomes zero following an
increment or decrement operation of that register.
5. Sign Flag (SF): After the execution of arithmetic or logical
operations, if the MSB of the result is 1, the sign bit is set Sign bit
1 indicates the result is negative; otherwise it is positive.
6. Overflow Flag (OF):This flag is set if result is out of range. For
addition this flag is set when there is a carry into the MSB and no
carry out of the MSB or vice-versa. For subtraction, It is set when
the MSB needs a borrow and there is no borrow from the MSB,
or vice-versa.
25

• The three remaining flags are used to control certain operations of
the processor.
1. Trap Flag (TF): One way to debug a program is to run the
program one instruction at a time and see the contents of used
registers and memory variables after execution of every
instruction. This process is called single stepping through a
program. Trap flag is used for single stepping through a program.
If set, a trap is executed after execution of each instruction, i.e.
interrupt service routine is executed which displays various
registers and memory variable contents on the display after
execution of each instruction. Thus programmer can easily trace
and correct errors in the program.
27

2. Interrupt Flag (IF) : It is used to allow/prohibit the interruption
of a program. If set, a certain type of interrupt (a mask-able
interrupt) can be recognized by the 8086; otherwise, these
interrupts are ignored.
3. Direction Flag (DF) : It is used with string instructions. if DF =
0, the string is processed from its beginning with the first
element having the lowest address. Otherwise, the string is
processed from the high address towards the low address.
28

Bus Operation
• The 8086 has a common address and data bus. The address and data
are time multiplexed, i.e. address and data appear on this bus at
different time intervals.
• The multiplexed address and data bus provides the most efficient
use of pins on the processor while permitting the use of a standard
40-lead package.
• This multiplexed address and data bus has to be demultiplexed
externally with the use of latches and the ALE signal provided by
8086.
• The control operation of 8086 is different in two different modes:
minimum mode and maximum mode.
• The minimum mode is used for a small systems with a single
processor and maximum mode is for medium size to large systems,
which often include two or more processors.
29

Memory Segmentation
• Two types of memory organizations are commonly used. These are
linear addressing and segmented addressing.
• In linear addressing the entire memory space is available to the
processor in one linear array, In the segmented addressing, on the
other hand, the available memory space is divided into ‘chunks”
called segments. Such a memory is known as segmented memory
• In 8086 system the available memory space is 1Mbytes This
memory is divided into number of logical segments. Each segment
is 64 K bytes in size and addressed by one of the segment registers.
• The 16-bit contents of the segment register gives the starting/base
address of a particular segment, as shown in Fig. 27.
• To address a specific memory location within a segment we need
an offset address. The offset address is also 16-bit wide and it is
provided by one of the associated pointer or index register.
30

• Rules for Memory Segmentation
1. The four segments can overlap for small programs. In a minimum
system all four segments can start at the address 00000H.
2. The segment can begin/start at any memory address which is divisible
by 16.
• Advantages of Memory Segmentation
1. It allows the memory addressing capacity to be 1 Mbyte even though
the address associated with individual instruction is only 16.bit.
2. It allows instruction code, data, stack, and portion of program to be
more than 64 KB long by using more than one code, data, stack
segment, and extra segment.
3. It facilitates use of separate memory areas for program data and stack.
4. It permits a program or its data to be put in different areas of memory,
each time the program is executed i.e. program can be relocated which
is very useful in multiprogramming.
32

Generation of 20-bit Address
• To access a specific memory location from any segment we need 20-bit
physical address.
• The 8066 generates this address using the contents of segment register and
the offset register associated with It.
• Let us see how 8086 access code byte within the code segment.
• We know that the CS register holds the base address of the code segment.
The 8086 provides an instruction pointer (IP) which holds the 16-bit address
of the next code byte within the code segment.
• The value contained in the IP is referred to as an offset. This value must be
offset from (added to) the segment base address in CS to produce the
required 20-bit physical address.
• The contents of the CS register are multiplied by 16. i.e. shifted by 4 position
to the left by inserting 4 zero bits and then the offset i.e. the contents of IP
register are added to the shifted contents of CS to generate physical address.
• As shown in the Fig. 2.8, the contents of CS register are 348AH, therefore
the shifted contents of CS register are 348A0H. When the BIU adds the
offset of 4214H in the IP to this starting address, we get 38AB4H as a 20-bit
physical address of memory.
33

• We have seen that how 20-bit physical address is generated within the
code segment. In the similar way the 20-bit physical address is
generated in the other segments. However, It is important to note that
each segment requires particular segment register and offset register
to generate 20-bit physical address. 34
P.A =cs*10H+ip

Pointers and Index Registers
• All segment registers are 16-bit. But it is necessary to put 20-bit
addressee (physical address) on the address bus. To get 20-bit
physical address. one more register is associated with each segment
register the way IP is associated with CS.
• these additional registers belong to the pointer and index group. The
pointer and index group consist of instruction pointer (IP), stack
pointer (SP). BP (base pointer),source index (SI) and destination
index (DI) registers.
1. Stack Pointer (SP) : The stack pointer (SP) register contains the
16-bit offset from the start of the segment to the top of stack. For
stack operation, physical address is produced by adding the contents
of stack pointer register to the segment base address in SS.
To do this the contents of the stack segment register are shifted four
bits left and the contents of SP are added to the shifted result. if the
contents of SP are 9F20H and SS are 4000H then the physical
address is calculated as follows.
SS = 4000M after shifting four bits left SS 40000H
35

Base Pointer, Source Index and Destination Index (BP, SI and DI)
• These three 16-bit registers can be used as general purpose registers.
However, their main use is to hold the 16-bit offset of the data word
in one of the segments.
2. Base pointer: We can use the BP register instead of SP for
accessing the stack using the based addressing mode. In this case,
the 20-bit physical stack address is calculated from BP and SS.
3. Source Index : Source index (SI) can be used to hold the offset of a
data word in the data segment, In this case, the 20-bit physical data
address is calculated from SI and DS.
4. Destination Index : The ES register points to the extra segment in
which data is stored. String instructions always use ES and DI to
determined the 20-bit physical address for the destination. 37

Default and Alternate Register Assignments
• Instruction codes can only be stored in the code segment with IP
used as an offset.
• Similarly, for stack operations only SS and SP or BP registers can
be used to give segment and offset addresses respectively.
• On the other hand, for accessing general data, string source, data
pointed by BX and BP registers; it is possible to use alternate
segments by using segment override prefix.
38

Segment Override Prefix
• The segment override prefix allows the programmer to deviate
from the default segment.
• The segment override prefix is an additional 8-bit code which is
put in memory before the code for the rest of the instruction.
• This additional code selects the alternate segment register. The
code byte for the segment override prefix as the format
OOIXXI1O.
• The XX represents a 2 bits which are as follows: ES = 00, CS= 01,
SS = 10 and DS = 11. It is important to note that the segment
override prefix may be added to almost any instruction in any
memory addressing mode.
43

Mpi chapter 2

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