![What is pH?
The pH relation originated from Danish
Chemist Sorenson in1909.
pH is the unit of measurement for
determining the acidity of alkalinity of a
solution.
The math definition of pH is the negative
logarithm of the molar H+:
pH = - log ([H+])
Source: wwww.emersonprocess.com
3](https://image.slidesharecdn.com/vivachinsengfatt3-viva2-100710064734-phpapp01/85/Design-and-fabrication-of-cmos-isfet-for-ph-measurement-3-320.jpg)
Design and fabrication of cmos isfet for ph measurement
- 1. Design and Fabrication of CMOS ISFET for pH Measurement MSc viva voce presentation by: Chin Seng Fatt Supervised by: 1. Prof. Dr. Uda bin Hashim 2. En. Mohd Khairuddin bin Md Arshad School of Microelectronic Engineering Universiti Malaysia Perlis 1
- 2. Presentation Outline Introduction TCAD Simulation Mask Design Device Fabrication Device Packaging Device Characterization Conclusion Acknowledgments 2
- 3. What is pH? The pH relation originated from Danish Chemist Sorenson in1909. pH is the unit of measurement for determining the acidity of alkalinity of a solution. The math definition of pH is the negative logarithm of the molar H+: pH = - log ([H+]) Source: wwww.emersonprocess.com 3
- 4. Importance of pH Measurement Control a Chemical Reaction Most inorganic reactions are pH neutralizations The rate of many reactions depend on the availability of H+ or OH- ions. Bacterial growth is pH dependent. Corrosion Control Water and Wastewater Treatment Raw Material and Product Quality Control Source: wwww.emersonprocess.com 4
- 5. pH Measurement Methods Litmus paper Simple Quick measurement Color indication Glass pH Electrode Higher accuracy Better selectivity 5
- 6. Litmus paper Glass pH electrode Color indication Bulky, fragile 2 pH value limitation High cost of Initial setup Preliminary measurement Routine maintenance This research proposed an ISFET that can measures This research proposed an ISFET that can measures the ionic activity in a electrolyte solution and can be the ionic activity in a electrolyte solution and can be fabricated using CMOS technology and materials fabricated using CMOS technology and materials without extra processing steps without extra processing steps The advantages of this proposed ISFET include: The advantages of this proposed ISFET include: Fast and direct in-situ monitoring Fast and direct in-situ monitoring Robust and sturdier Robust and sturdier Small size Small size 6
- 7. What is ISFET? ISFET is Ion Sensitive Field Effect Transistor Known as chemical or ion sensor Sensing method based on potentiometric detection First developed by Prof. Bergveld in 1970 by using SiO2 as sensing layer Advantages: small size, robust, fast response Applications: medical, agriculture, food industry, environment monitoring 7
- 8. MOSFET and ISFET Basically the structure of the ISFET is similar to MOSFET The physical difference in the ISFET is the replacement of the gate electrode of the MOSFET by the series combination of reference electrode, electrolyte and ion sensing layer MOSFET operation was controlled by the gate electrode while ISFET operation was controlled by ion concentration in the electrolyte 8
- 9. Flowchart of How ISFET works Gate Gate Inversion Inversion voltage voltage layer layer ISFET ISFET exceeds exceeds formed at formed at threshold threshold SiO2/Si SiO /Si 2 Positive Positive N+ drain N+ drain N+ source N+ source voltage voltage make make supply supply applied to applied to electrons electrons electrons electrons n+ drain n+ drain flow flow Electrons Electrons Gate voltage Gate voltage flow from S flow from S controls controls to D to D electrons and Id electrons and Id 9
- 10. Objective of Research Research Goals To characterize the To design the ISFET ISFET To fabricate the ISFET 10
- 11. Scope of Research Reviewing and understanding the principles of ISFET Design and simulate the ISFET with TCAD Design and fabricate the ISFET masks Fabrication of the ISFET Testing of the ISFET 11
- 12. TCAD Process Simulation Synopsys TCAD is used to Gate metal contact perform process and device simulation on ISFET. Source metal Drain metal contact contact Process simulation models the fabrication steps of the ISFET. N N Simulation starts with definition of structure and finishes with a complete device Si3N4 / SiO2 gate The process simulator used is Virtual ISFET simulated by TSUPREM4 TSUPREM4 12
- 13. TCAD Device Simulation Device simulation in TCAD is the simulation of the device electrical characteristics. The TUSPREM4 ISFET is simulated for its gate and drain characteristics. The characteristics of the ISFET are simulated by applying a set of voltage biases and sweep the biases from one point to another. Device simulator used is Medici. I-V simulation by Medici 13
- 14. Mask Design Layout of ISFET similar to MOSFET: gate, source, drain, contacts. The extended source drain regions separates the metal contacts from gate region during immersion and for straightforward encapsulation. Mask making process is straightforward: CAD design and mask printing. CAD design of individual dies replicated on a wafer to create the wafer layout and then transferred to actual mask. A total of 6 masks created. Material used as the actual mask is transparency. Schematic design of the ISFET 14
- 15. Well Mask (a) (b) (a) Schematic design of well (b) AutoCAD design of the Well mask (c) Photograph of the actual mask (c) 15
- 16. Source Drain Mask (b) (c) (a) Schematic design of source drain (b) AutoCAD design of the source drain masks (a) (c) Photograph of the actual source drain masks 16
- 17. Gate Mask (b) (a) (c) (a) Schematic design of Gate (b) AutoCAD design of the Gate mask (b) Photograph of the actual Gate mask 17
- 18. Contact Mask (b) (a) (c) (a) Schematic design of Contact (b) AutoCAD design of Contact mask (b) Photograph of actual Contact mask 18
- 19. Metal Mask (a) (b) (a) Schematic design of metal contact (b) AutoCAD design of the Metal mask (c) Photograph of the actual Metal mask (c) 19
- 20. Fabrication of ISFET ISFET is fabricated using CMOS technology without any post processing steps. All fabrication steps are performed in-house in Microfabrication Lab. The starting material is a 4 inch p-type Silicon wafer. The gate material of the ISFET is made of SiO2 and Si3N4, both CMOS compatible materials. Six masking steps: creation of n-well, n and p source drains, gate, contact and metal. The etching of Si3N4 and SiO2 is done using buffered oxide etch (BOE) solution. 20
- 21. Equipment modules Consumables PECVD system Silicon wafer 4 inch PVD system Buffered oxide etch (BOE) Wet/dry oxidation furnace Acetone N/P diffusion furnace Positive photoresist Mask aligner/exposure system DI water Wet etch module Aluminum foil Wafer spinner Aluminum etchant Hot plate SiH4 gas Purified oxygen gas Purified nitrogen gas 21
- 22. Process Flow of ISFET Fabrication 1. Starting material 1. Starting material Si, p-type, <100> Si, p-type, <100> 2. Field oxidation 2. Field oxidation Wet oxidation, 1000°C Wet oxidation, 1000°C 95 min 95 min 5598 Å 5598 Å Wet oxidation furnace Wet oxidation furnace 3. Well creation 3. Well creation Well Mask, positive photoresist Well Mask, positive photoresist Resist development: 30s Resist development: 30s Oxide etch: 30 min Oxide etch: 30 min 22
- 23. Process Flow of ISFET Fabrication 4. Well phosphorus diffusion 4. Well phosphorus diffusion Spin-on dopant phosphorus Spin-on dopant phosphorus Diffusion drive-in: 6 hours Diffusion drive-in: 6 hours N-diffusion furnace N-diffusion furnace 5. Phosphorus source drain formation 5. Phosphorus source drain formation Source Drain Mask, Positive photoresist Source Drain Mask, Positive photoresist Spin on dopant --phosphorus Spin on dopant phosphorus N-Diffusion furnace: 850°C, 25 min N-Diffusion furnace: 850°C, 25 min 6. Boron source drain formation 6. Boron source drain formation Source Drain Mask, positive photoresist Source Drain Mask, positive photoresist Spin on dopant --boron Spin on dopant boron P-Diffusion furnace: 900°C, 30 min P-Diffusion furnace: 900°C, 30 min 23
- 24. Process Flow of ISFET Fabrication 7. Gate oxide formation 7. Gate oxide formation Gate Mask photolithography Gate Mask photolithography Gate oxidation Gate oxidation Dry oxidation furnace Dry oxidation furnace 1000°C 60 min 1000°C 60 min 556 Å556 Å 8. Silicon nitride PECVD deposition 8. Silicon nitride PECVD deposition Deposition rate: 24.34nm/min Deposition rate: 24.34nm/min Deposited thickness: 486.7 Å Deposited thickness: 486.7 Å 9. Contact BOE etch formation 9. Contact BOE etch formation Oxide & nitride etch with BOE Oxide & nitride etch with BOE Etch time:30 min Etch time:30 min 24
- 25. Process Flow of ISFET Fabrication 10. PVD contact metallization 10. PVD contact metallization PVD module PVD module Aluminum thickness: 1541 Å Aluminum thickness: 1541 Å Annealing 450 °C, 45 min, N2 gas Annealing 450 °C, 45 min, N2 gas Metal Mask, positive photoresist Metal Mask, positive photoresist Etch rate Al: 308.2 Å/min Etch rate Al: 308.2 Å/min Etch time: 5 min approx. Etch time: 5 min approx. ISFET die with metal ISFET die with metal gate for functionality gate for functionality evaluation evaluation ISFET die with Si3N4 ISFET die with Si3N4 gate will be packaged gate will be packaged and tested in pH and tested in pH solutions solutions Photography of Photography of the completed ISFET wafer the completed ISFET wafer 25
- 26. Packaging of ISFET The packaging process of ISFET: wafer dicing, die mounting, wire bonding and encapsulation. The ISFET die is separated from the wafer and mounted on a PCB as a platform and contacts are wired from die to the PCB. Since the ISFET will work in electrolyte solution, an epoxy is used to encapsulate the edge of the ISFET die, the wire bonding and the PCB. The sensing gate is the only area which is exposed to the solution will not be covered. The type of epoxy used is silicone rubber. 26
- 27. Packaging Flow of ISFET 1. Diced ISFET from wafer 1. Diced ISFET from wafer 2. Mounting ISFET on PCB 2. Mounting ISFET on PCB 3. Wire bonding 3. Wire bonding 4. ISFET encapsulation 4. ISFET encapsulation 27
- 28. Characterization of ISFET The operation of ISFET is analyzed from IdVd and IdVg curves. IdVd and IdVg measurements are done using Keithley 4200 Semiconductor Parameter Analyzer. Two tests are performed on ISFET: functionality test at wafer level and pH test. In functionality test, the ISFET with metal gate is under probes connected to the analyzer. In pH test, the ISFET is immersed in acidic, neutral and base solutions (pH 4, pH 7, pH 10). All solutions obtained from Orion. All measurements were done using Ag/AgCl reference electrode from Hanna Instruments. 28
- 29. Functionality Test Setup Schematic setup Schematic setup (a) (a) Dark shielded box– wafer probe station (b) (b) Keithley 4200 Semiconductor Parameter Analyzer 29
- 30. pH Test Setup (a) (b) (c) (d) (a) Keithley 4200 Semiconductor Parameter Analyzer (b) ISFET (c) Reference Electrode (d) pH buffer solutions 30
- 31. Output characteristics of ISFET I-V measurements of ISFET performed using Keithley 4200 SPA through wafer probe station I-V measurements of ISFET performed using Keithley 4200 SPA through wafer probe station 31
- 32. pH Response of n-ISFET IdVd curves at Vg=5.0V for n-ISFET when IdVd curves at Vg=5.0V for n-ISFET when Sensitivity, S = Δ Vth / /Δ pH Sensitivity, S = Δ Vth Δ pH measured in three levels of pH buffer measured in three levels of pH buffer = Δ Vg / /Δ pH = Δ Vg Δ pH solution solution = 40.34 mV/pH = 40.34 mV/pH 32
- 33. pH Response of p-ISFET IdVd curves at Vg=-5.0V for p-ISFET when IdVd curves at Vg=-5.0V for p-ISFET when Sensitivity, S = Δ Vth / /Δ pH Sensitivity, S = Δ Vth Δ pH measured in three levels of pH buffer measured in three levels of pH buffer = Δ Vg / /Δ pH = Δ Vg Δ pH solution solution = 34.83 mV/pH = 34.83 mV/pH 33
- 34. Discussions ISFET operates by accumulating H+ from solution at gate. The positive charge on gate is mirrored on the inner side of semiconductor where a channel of negative charge occurs. This makes ISFET conductive. The lower pH, more H+ accumulates, more current flow between source and drain. Image Source: http://www.my.endress.com/ 34
- 35. Conclusions A CMOS ISFET pH sensor has been successfully designed, fabricated and characterized. Simulation on ISFET is successfully achieved using TCAD. Mask layout successfully designed using AutoCAD and fabricated on transparency masks. Fabrication of ISFET using all in-house CMOS technology required no extra masking or post processing step. The ISFET successfully detected buffer solutions of different pH. Based on the results obtained, the CMOS ISFET showed a fairly good response as a pH sensor and has potential for commercialization. 35
- 36. Research Achievements Research Publications Award Medals International Journal 1 Gold Medal 1 International Conference 4 Silver Medal 3 Regional Conference 3 Bronze Medal 2 Local Conference 5 36
- 37. Recommendation SPICE simulation Simulation of pH response of ISFET Miniaturization of ISFET Sub-micron size device, chrome masks Lower cost of fabrication, mass production Packaging of the ISFET Precise wafer dicing by automation Proper encapsulation material and technique Sampling Experiments Larger samples of pH on both acidic and basic tests 37
- 38. Acknowledgement The financial support from UniMAP and Malaysian Ministry of Science, Technology and Innovation (MOSTI). Guidance and advices from supervisors Motivational supports from families, researchers, friends. 38