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MODULE- 2
DATA REPRESENTATION AND
COMPUTER ARITHMETIC

FIXED POINT REPRESENTATION
• In a fixed-point representation, all numbers are represented as integers or fractions.
• The fixed-point method assumes that the radix (binary) point is always fixed in one
position
• The two widely used positions in register are
(1) a binary point in the extreme left of the register to make the stored number a fraction
Ex: 0.1011
(1) a binary point in the extreme right of the register to make the stored number an
integer
Ex: 1011.0

POSITIVE FIXED POINT REPRESENTATION
• The positive fixed-point (integer) number is represented by 0 in sign bit position
and the magnitude by a positive binary number.
• For example, +12 is to be stored in an 8-bit register. +12 is represented by a sign bit
of 0 in the leftmost position followed by the binary equivalent of 12, i.e. 0 0001100.
• There is only one way to represent a positive number Sign bit

NEGATIVE FIXED POINT REPRESENTATION
• There are three representations for a negative integer number.
• The negative number is represented by 1 in the sign bit position and the magnitude
of the number is represented in one of three possible ways:
(a) signed-magnitude representation
(b) signed-1’s complement representation
(c) signed-2’s complement representation
• There are three different methods to represent - 12 with 8-bit registers.
 In signed-magnitude representation: 1 0001100
 In signed-1’s complement representation: 1 1110011
 In signed-2’s complement representation: 1 1110100

 In all three systems,
*Left most bit is 0 for positive and 1 for negative numbers
 Positive values are same for all systems
 In sign magnitude, negative values represent by changing
MSB b3 from 0 to 1
1’s complement, negative values represent by complement
each bit of corresponding positive number
2’s complement obtain by adding 1 to 1’s complement of
number.
 drawback: +0 and -0 has distinct representation in sign and
magnitude and 1’s complement
2’s complement system leads to most efficient way to carry
out addition and subtraction

Characteristics of 2’s complement representation and arithmetic

ARITHMETIC OPERATION ON FIXED POINT
NUMBERS

Addition and subtraction of signed integer
The rules governing addition and subtraction of n-bit signed numbers using the 2’scomplement
representation system may be stated as follows:
To add two numbers, add their n-bit representations, ignoring the carry-out bit from the most significant
bit (MSB) position. The sum will be the algebraically correct value in 2’s-complement representation if the
actual result is in the range -2n-1 through +2n-1-1
To subtract two numbers X and Y , to perform X − Y , form the 2’s-complement of Y , then add it to X
using the add rule. Again, the result will be the algebraically correct value in 2’s-complement representation
if the actual result is in the range -2n-1 through +2n-1-1

Addition and subtraction using 2’s complement

Overflow in fixed point representation
 When the actual result of an arithmetic operation is outside the representable
range, an arithmetic overflow has occurred.
If two numbers are added, and they are both positive or both negative, then
overflow occurs if and only if the result has the opposite sign.

MULTIPLICATION- UNSIGNED
 Multiplication is a complex operation as compared to addition and
subtraction
 It can perform in hardware or software.
 Several algorithms are used in various computers.
 First we see the simpler problem of multiplying two unsigned integers,
Process involves generation of partial products, one for each digit in the
Multiplier and each successive partial product is shifted one position to the
left.
 When the multiplier bit is 0, the partial product is 0. When the multiplier is 1,
the partial product is the multiplicand
 Final product is produced by summing the partial products.
 The multiplication of two n-bit binary integers results in a product of upto 2n
bits in length.

MULTIPLIER ARCHITECTURE-UNSIGNED
 we can perform a running addition on the
partial products rather than waiting until the
end.
 Eliminates the need for storage of all the
partial products; fewer registers are needed.
Save some time on the generation of partial
products
 For each 1 on the multiplier, an add and a shift
operation are required; but for each 0, only a
shift is required

MULTILPLICATION OPERATION STEPS
 The multiplier and multiplicand are loaded into two registers
(Q and M).
 A register, is also needed and is initially set to 0.
 1-bit C register, initialized to 0, holds a potential carry bit
resulting from addition.
 Bit 0 of multiplier operand (Q0 of Q register is checked)
 If bit Q0 is 1, then multiplicand are added to A register and
results are stored here.
 All bits of C, A,and Q registers are shifted to right one bit, so
that C bit goes into An-1, A0 goes into Qn-1 and Q0 is lost
 If bit 0, no addition operation only shift operations is carried
out.
This process is repeated for each bit of the original multiplier.
Resulting 2n-bit product is contained in the A and Q registers
Multiplicand
Multiplier

FLOWCHART FOR UNSIGNED MULTIPLICATION

MODULE- 2
SIGNED MULTIPLICATION

BOOTH’S ALGORITHM
 Algorithm used for signed number multiplication is called Booth’s algorithm
which generates 2n-bit product .
 Treats both positive and negative numbers uniformly.

Initially set A and Q-1 = 0
 N bit adder
-N bit adder add two inputs, A register and M(multiplicand)
-For addition, A= A+M
Add’/sub =0,Cin=0,multiplicand directly applied as input to n bit adder and add with A register
-For subtraction, A= A-M
Add’/sub =1,Cin=1, multiplicand is complemented and applied as input to n bit adder and finally 2’s
complement of multiplicand is added to A register
 Shift, add and subtract control logic : scans Q0 and Q-1 bits one at a time
-If (Q0 and Q-1 =1-1 or 0-0 ), shift operations occur from (A to Q-1) registers, no add/subtract(Enable=0)
-If (Q0 and Q-1 =0-1),addition operation , A=A+M (Add/subtract enable=1)
-If (Q0 and Q-1 =1-0),subtraction operation , A=A-M (Add/subtract enable=1)
-After addtion and subtraction, right shift occurs from Left most bit of A(An-1) and also it keeps An-1 bit
in A register.
- It is also known as arithmetic shift, since it preserves the sign bit.
SIGNED MULTILPLICATION OPERATION STEPS

Booth’s algorithm (7X3)=21
Multiplicand=7
Multiplier=3
QO Q-1 Add’/sub Add/sub
enable
shift
0 0 X 0 1
0 1 0 1 (A+M) 1
1 0 1 1 (A-M) 1
1 1 X 0 1
EXAMPLES FOR BOOTH’S ALGORITHM
Booth’s algorithm (5X-4)=-20
Both Positive

FLOWCHART FOR SIGNED MULTIPLICATION

BOOTH’S ALGORITHM USING RECODED
MULTIPLIER

MODIFIED BOOTH’S ALGORITHM
• To speed up the multiplication process in Booth’s algorithm, bit pair
recoding is used.
• It halves the maximum number of summands
• In this techniques, booth recoded multiplier bits are grouped in pairs.
• Each pair is represented by its equivalent single bit multiplier reducing
total number of multiplier bits to half.

BIT PAIR RECODING OF Q USING TABLE

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RESTORING AND NON-RESTORING DIVISION
MODULE- 2

DIVISION
1 0 0 1 0 0 1 1
1011
1 0 1 1
0 0 1 1 1 0
1 0 1 1
0 0 1 1 1 1
1 0 1 1
1 0 0
Divisor Dividend
Quotient
00001101
Remainder
Partial Remainder1
Partial Remainder 2
11
143
4
13
Examine bits of dividend from left to right,
until set of bits represents number >=
divisor, referred to as divisor able divide the
number.
Until this condition occurs 0’s placed in
quotient from left to right. When condition
satisfied place 1’s in quotient and divisor
subtract from dividend
Result is reffered to as partial remainder
Repeat the steps until all bits of dividend
are brought down and result is less than
divisor.
Each repetiton cycle, additional bits from
dividend are brought down to partial
remainder

HARDWARE TO IMPLEMENT BINARY DIVISION
Hardware consists of n+1 binary adder, shift,
add and control logic and registers A,Q and M.
Divisior and dividend are loaded into register M
and Q.
Register A initially set to Zero
Division operation is carried out
After division operation is complete, n bit
quotient stored in register Q and remainder in
Register A

RESTORING DIVISION
Q (Dividend)=0111; M(Divisor)=0011
 Shift A and Q left one binary position
 Subtract M(divisor) from A and place
result back in A (A=A- M= A+(-M))
 If sign bit of A is 1, Set Q0 =0 and
restore A.
If sign bit A is 0, set Q0=1
 Repeat the steps n times
-M=11101
M= 00011
n= 4
A=00000
Count =n =n-1
Decimal 7 Decimal 3

FLOWCHART FOR RESTORING DIVISION OPERATION

NON RESTORING DIVISION
After subtraction operation in restoring algorithm,
- If sign bit of A is 1, Set Q0 =0 and restore A.
- If sign bit A is 0, set Q0=1
After subtraction operation in Non restoring algorithm,
-If sign bit of A is 1, shift A and Q left one position and add divisor to A,
Set Q0 =0.
-If sign bit of A is 0, shift A and Q left one position and subtract divisor from A, Set Q0 =1
Repeat steps 1 and 2 for n times

Q (Dividend)=0111 M(Divisor)=0011 M= 00011 -M=11101

Q=7 M=3 => Q=2, R=1
Q=7 M=-3 => Q=-2, R=1
Q=-7 M=3 => Q=-2, R=-1
Q=-7 M=-3 => Q=2, R=-1
Examples of integer division with all possible
combinations of signs of Q(dividend) and M(divisor)

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