Nanometer layout handbook at high speed design

Nano meter layout handbook
@ high-speed design
2016.1.20.
Advanced Integrated Systems Lab.
Minho Park

References
2
1. Vishant Gotra, Rishabh Agarwal, Gurinder Singh Baghria - Freescale Semiconductor, Advanced yield enhancement technique: Lithography friendly
design, http://www.eetimes.com/document.asp?doc_id=1280536
2. Matt Malloy ; Lloyd C. Litt - Technology review and assessment of nanoimprint lithography for semiconductor and patterned media manufacturing
3. Plasma Damage, http://www.enigmatic-consulting.com/semiconductor_processing/CVD_Fundamentals/plasmas/plasma_damage.html
4. Chris Schuermyer, Jan 17, 2013, Gate Oxide Defects Caused by Antenna Effects, http://siliconyield.com/gate-oxide-defects-caused-by-antenna-effects/
5. Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices @ Journal of Micro/Nanolithography, MEMS, and MOEMS
6. Keiji Kishine et al, Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control
7. Sam Palermo, Lecture 5: Layout Techniques
8. Franco Maloberti, Layout of Analog CMOS IC
9. Dan Clein, CMOS IC LAYOUT
 I referenced above papers, books, and class materials to make this contents. All
used images (except originals) are belong to own’s copyrights.
 I made this contents for students self motivated seminar. For who is about to
layout own’s chip design along schematics.
 Definitely not commercially used.

Contents
3
Part I : Lithography
- lithography defects and its preventions
Part II : Layout techniques
- Layout techniques about high speed Tx,Rx
Part III : High speed layout guide
- Checklist of high speed layout
- Matching, Offset, Loading, Reliability

5
 non ideal phenomenon in patterning  DFM (OPC, DRC)
 Tilt problem (shadow effect, gradient)
 Shadow : beam (wet) energy remains  antenna effect
 Cross chip gradient : doping implemented irregularly (gradient) along wafer zone while causing dose, focus problem
 matching solution
 VOID
- layer inter connection (contact, via) resistance up
 Antenna effect
- ebeam energy(etching) charged along long line and it crosses gate oxide.
 Etching problem (Critical Dimension, pinching/bridging)
 CD : mainly gate poly pattern collapse due to several reason (focus)
 dummy pattern(pattern dummy, etch dummy), simple pitch
 pinching / bridging
- Patterns conflict each other  thickening, thinning happens  dummy, OPC (DRC)
- corner round effect
Summary of defects in patterning

6
Figure 2: pinching and bridging during manufactureFigure 1: Process variation band.
Figure 4: Bridging failure.Figure 3: pinching failure.
 process variability bands / bridging, pinching
 hotspot (Critical Dimension) Error (next page)
pattern defect examples [1]

7
 gate-poly defect (Critical Dimension) example
thickening, thinning, pinching and ... all GP defects
closely related with circuit performance degradation.
thickening, thinning, pinching and ... all GP defects
closely related with circuit performance degradation.
gate-poly pattern defects (CD) [2]

8
 Metal1 – VIA – Metal2
inter layer contact / via defect
 line resistance up / irregular, yields down
via ok via defect
lithograph defects : VOID & VIA

9
charge dissipation
@active on the bulk
charge dissipation
@active on the bulk
++++
++++
++++
Plasma damage - Antenna effect [4]
 e-beam energy charged by plasma
along antennas (long metal lines)
 at high resistance / capacitance burst out.
 e-beam energy charged by plasma
along antennas (long metal lines)
 at high resistance / capacitance burst out.
+++
+
++
e-beam
(by plasma)
energy charged along
surface of shadow region

10
. charging
. damage
Qbd : 1~100 coulomb/cm2
(breakdown chage )
MOS transistor with positive bias on the gate
electrons that can hop over or tunnel through the oxide-
semiconductor barrier can travel through the oxide.
Electric fields are high, and the electrons can gather
energy and do damage (break bonds) as they proceed.
plasma damage [3]

11
From Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices
@ Journal of Micro/Nanolithography, MEMS, and MOEMS
Defect correction method [5]

12
 DRC : Design Rule Checks
 LFD : Lithography Friendly Design
 RET : Resolution Enhancement Techniques
 OPC : Optical Proximity Correction
hot spot fixinghot spot fixing
Defect correction techniques

13
 pinching / bridging  OPC, LCC, DRC
- Patterns conflict each other  thickening, thinning happens  dummy, OPC (DRC)
- corner round effect
 tilt related problem (process variation)  Matching layout
 VOID  more than double contact/VIA
- contact certainly. make contact several times
- sometimes contact area causes parasitic cap  BW degradation
 antenna effect  antenna diode contact (junction)
- no open lines to gate poly  antenna diode connection on P substrate
 Critical Dimension problem  GP dummy / simple pitch placement
- CD : GP pattern collapse  dummy GP for protection
- simple pitch : using regular GP pitch (TR length regulation)
DFM layout method for defects
**DFM : design for manufacture

14
Below items are major lithography failures (DFM method needs)
Depth of focus
while separated masks are aligned to each other accurately, the actual thickness of the layer be reflected while printing the pattern on the silicon.
Depth of focus is the parameter which defines how accurately the thickness of the layers. The greater the depth of focus, the better will be the alignme
between the masks.
Dose
During lithography, the error(printing imperfections and therefore poor yield and circuit performance ) comes from removing the photoresist and varyin
in the intensity of light in various regions of the wafer
Process variation and process variability bands
As technology smaller more sensitive about small changes in the lithography process parameters change (dose, focus, mask bias...)
 the delay and leakage change affecting design performance.
CD(Critical Dimension) Errors
gate CD error in the active region and gate poly. (cross-chip linewidth variation)
Internal checks can be performed in the active region to measure CD and quantify variation across the gate.
process variability bands can be used to locate the regions of low contrast and high MEEF that are most affected by process variability
most effective lithography failures on circuit performance
bridging, pinching, CD errors, edge error, extra printing/nonprinting features
Bridging / pinching : edge placement error (EPE, contour separation failure) due to focus and dose setting in outer/inner tolerance zone
OPC goal : OPC compensates for process transformations and to ensure adequate patterning margin
grossary

15
Part II : Layout techniques

16
dummy gate
etch dummy
uniform pitch (simple pitch)
Gate poly dummy
 gate poly : most finest pattern.  require complicated pattern method

17
 single contact / via
Can makes contact at less area. good for Auto routing. but not suggest custom layout of analog unit.
 double contact / via
Resistance becomes less than single contact / via.
Suggest to make contact/via double while considering node capacitance. (without contact area stretching)
In case of MOS junction contact, care of node signal degradation. must consider between resistance and capacitance
Single / Double contact (DC, VIA)
W W W
area area x 2
 width double = area double
- R  ½R (resistance half)
- C  2 C (capacitance double)
R ½R
C 2C
• Many contacts placed close to one another  1. reduces series resistance
2. the surface of metal connection smoother than use only one contact
3. this prevents micro cracks in metal

Parasitic loading effects [6]
18
 phase delay θd and gain |G|
3) Capacitance Cp in Fig. 3(b) represents the parasitic capacitance Cpw with a wire line in Fig 3(a),
and also includes the input parasitic capacitances of the following stage in Fig. 2.
4) Furthermore, the parasitic resistance Rp with the wireline is connected to the output node.
 Gain degraded by α (Cp, Rp)

19
Why matching? : cross-chip gradient
doping
concentration
4I3I2II
S D
G
S D
G
S D
G
S D
G
 One of main cause of process variation
 Same width / length TR  Doping differently  Generate current differently
 Matching : Inter digitized? / Common centroid ?

5
5
20
doping
concentration
ex: cross-chip gradient cancellation
. Junction matched
. Junction Match failed?
5
5
6
4
 one of main causes of process variation
 same width / length TR , but doped differently  generate current differently

21
• shift placed (differential pair shifted)
• Process variations are averaged among transistors (good dc condition)
• good matching technique for dc condition
• total drain area uneven between M1 and M2.  drain capacitance uneven
(not desirable ac conditions: capacitance, other parameters may not be equal)
• A more robust approach is needed (Use dummies if needed !!)
Inter-digitized Layout [7]
M1:KP1+KP4+KP5+KP8 (Avg=4.5)
M2:KP2+KP3+KP6+KP7 (Avg=4.5)
Samuel Palermo
 concept and example of inter-digitized layout
 good for DC conditioned schematic

22
• Each transistor is split in four equal parts interleaved in two by two’s.
So that for one pair of pieces of the same transistor we have currents flowing in opposite direction.
• Transistors have the same source and drain area and perimeters, but this topology is more susceptible
to gradients (not common centroid)
Inter-digitized Layout (2) [7]
 improved Inter-digitized Layout – capacitive matched !
 shift placed (not mirrored)  gradient not cancelled, but good for DC/AC conditions
Samuel Palermo

23
Common Centroid Layout [7]
• split in even for parallel connection  mirror placed (differential pair mirrored)
• good for RF application
(less effective of crosstalk mismatch, junction capacitance mismatch)
M1M2M2M1M1M2M2M1
M1M2M2M1M1M2M2M1
M2M1M1M2M2M1M1M2
Samuel Palermo
 Common Centroid Layout
 Inter-digitized Layout

24
Common Centroid Layout
 example Layout : cap

25
Part III : High speed layout guide

Introduction
26
• Suggested reference of using this Layout handbook and checklist
- layout 사항에 대한 self checkout idea of layout about High speed CMOS IC
- Gives common sense of Idea  schematic  layout  mask  lithography
- DFM based insight of schematic  layout
• Major Category
1. Offset - matching
common centroid : process variation (crosschip gradient)
dummy : mis-pattern prevent
2. crosstalk
shield
space
3. Loading – noise, delay, skew
substrate guard-ring
dnwell
4. Reliability

27
Category Item Comment etc
matching
differential matching Differential pair symmetry : AABB(inter digitized) ABAB (common centroid)
GP CD Dummy place, GP pitch (incl length)
buf matching
Differential node (gate, drn,src node)
Drain node : mainly output node, makes capacitive load low while resistance low as well.
Trade off capacitive load and resistance. Normally a high speed output node need to reduce capacitive load for
speed limit (bandwidth limit)
Source node : connect to source (vdd/vss) or path itself to vdd/vss.
Decoupling cap : Capacitive up cap’s active junction, and resistive down for ESR effects low
gradient Cross chip gradient (process variation) – Vt variation as temperature
inter‐digitized Juction connection not matched so good for DC source  modified inter‐digitized also good for high speed
common centroid Good for offset layout. Area increased due to
input node make input capacitance low for high speed input.
output node
small swing node : makes metal line thinner to less node loading (but resistive)
large swing node : makes metal line thicker to less node resistor (but capacitive)
source make contact alot (usually source node connects to power/ground  capacitive up, resistive down)
offset
amp offset amp offset from various
DQ/ZQ mismatch DQDRV RON matches ZQCAL RON within spec‐in
clock tree H tree has same capacitance and resistance from same length
vref VREF, sub unit identify each other. (sub unit shape, length, width all identity) minimize sub unit pieces
loading
line shield Line Shield – coupling for different layer (3D)
repeating repeating every 1500um with repeater unit.
parasitic capacitance
enough space at same layer (fringe cap coupling)
avoid upper/lower layer pattern (coupling to upper/lower layer)
reliability
antenna effect shadow effect, wet etch, dry etch
VOID double contact
ESD
 Check List of high speed IO layout

28
Contents
 Matching
 Offset
 Loading
 Reliability

capacitance – loading [9]
29
Dan Clein
 Fringe cap : self loading cap
 Process gets narrow, metal stacks
higher  Fringe cap higher
 Fringe cap : self loading cap
 Process gets narrow, metal stacks
higher  Fringe cap higher  Coupling cap : planar, 3D Coupling cap : planar, 3D
 Coupling cap with
Coupled with metals every
where with substrate coupling
effects
 Coupling cap with
Coupled with metals every
where with substrate coupling
effects
 Coupling cases

30
capacitance – coupling (Crosstalk) [9]
Bottom capacitance Cb
mutual capacitances Cm
Top capacitances Ct added
Dan Clein
 Coupling loading through parasitic capacitance of long running metal lines affects seriously on
signal  normally tR, tF
 It happens not only planar but also 3D. The Tops and Bottoms
M1

capacitance – signal line shield [9]
31
< Differential pair twisting to reduce signal coupling (PCB technique) >
 effect of coupling - DC signal shield effect of coupling - DC signal shield
aggressor
victim
aggressor
victim
tPD (delayed)
tPD (normal)
XX : aggressor
. twisted line : coupling noise canceled with differential pair common mode
. shield with vss line.
XX : aggressor
. twisted line : coupling noise canceled with differential pair common mode
. shield with vss line.
 Coupling effects : aggressor affects on victim.
 Critical signal line could be shielded with static
level signal. This technique will eliminate the
worse-case coupling scenario
 Coupling effects : aggressor affects on victim.
 Critical signal line could be shielded with static
level signal. This technique will eliminate the
worse-case coupling scenario
 effect of coupling - diff pair twist shield effect of coupling - diff pair twist shield
case 1 case 2
. twisted line
. differential pair
. twisted line
. differential pair
XX : aggressor
1
2
1
2
. twisted line, differential pair
. vss shield
. twisted line, differential pair
. vss shield
Dan Clein
 Coupling : Victim and Aggressor cases

Capacitance – deterministic jitter
32
 Capacitance coupling also causes a Deterministic Jitter.
 FEXT-induced jitter : Far-end crosstalk on parallel microstrip line in single-ended signaling
 Capacitive coupling : as voltage feedback, even mode case
 Inductive coupling : as current feedback, odd mode case
먼저 발생 늦게 발생
From Prof. Shim of Postech

capacitance – Vref line shield [9]
33
< Shielding option examples in two-metal process >
 shield form all way if it needs shield form all way if it needs
Cc_lower
Cc_upper
Vref line
VSS
VSS
• case : isolating the signal from influences on the same layer both sides
• case : isolating the signal from influences on the same layer and upper/lower layers
• case : isolating the signal from influences on the same layer both sides
• case : isolating the signal from influences on the same layer and upper/lower layers
• Voltage reference level is critical to comparator and buffer.
• Reference level could be corrupted by signal line toggling.
• So keep reference line safe as isolate it from signal lines everywhere
• Voltage reference level is critical to comparator and buffer.
• Reference level could be corrupted by signal line toggling.
• So keep reference line safe as isolate it from signal lines everywhere
Dan Clein
 Shield : important signal / reference line shielding cases

34
capacitance – Vref line shield [9]
< Shielding option examples in three-metal process >
Dan Clein

35
Resistor – (symmetry) [9]
< resistor shielding >< interlaced resistor shielding >
Dan Clein
 Shield : line resistor shielding cases
 Line resistor is used for small and simple resistor
 Line resistor is also used for skew (tPD) matching. This technique is good for multi bit skew aligning.
 Line resistor is used for small and simple resistor
 Line resistor is also used for skew (tPD) matching. This technique is good for multi bit skew aligning.
A2
A1
A1 A2
A2 is delayed to A1  RC delay added to A1

36
Balanced NAND – input unbalanced [9]Dan Clein
in2
in1
out
 Balanced NAND
 One of inputs must be closer (or faster) to output than the other.
 To prevent unbalanced path, split NMOS fingers and attach all input TRs to output.
In1 is faster than in2
< Conventional NAND > < Balanced NAND >
in2
in1
out
In1 is slower as in2 is

Balanced layout [9]
37
The schematic shown on the right side of Figure 7.20 shows exactly how the schematic is defined for Example 3. Many LVS
layout verification tools have algorithms to recognize NAND gates within the layout. The layout NAND shown in Example 3 is
not often recognized as a NAND and creates discrepancies when compared to a regular schematic NAND. The reason is
that the order of the series connections within the NAND is reversed. Functionally, they are equivalent and in fact balanced.
In this case the schematic must be altered to reflect the correct connectivity in order for the LVS to pass.
Balancing circuits is not always as straightforward. Balancing series devices is more difficult when dealing with more than
two transistors connected in series. Figure 7.21 shows an example of three series gates to illustrate this concept further.
In order to balance the series connections, each input is connected to a transistor in each of the three positions: close to
out, center, and close to power. This is only possible if there are three parallel series chains; therefore, introducing
balancing to a layout may incur significant overhead.
Dan Clein

HCI (Hot carrier injection)
38
High voltage between src / drn  high E field causes hot carrier
 Ease down voltage between src / drn
 HCI (Hot carrier injection)
 High field between drain and source causes hot electrons that strikes out from semicon (mainly pinch off
condition).
 One of Vth variation causes to trap hot electrons inside of oxide.
 Ease down electric field
 LDD (lightly doped drain)

NBTI (Negative bias temperature
instability)
39
 NBTI (Negative bias temperature instability) : Vth varies on PMOS device
–Vth increase with negative bias, Vgs=-Vdd
–But recover with zero bias , Vgs=0
•NBTI degradation is front-loaded
•Frequency dependent or independent ?
•Vgs dependence
•Vth variation reduction due to NBTI
Vth increased

Nanometer layout handbook at high speed design

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