Novel fpga design and implementation of digital up
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The document describes the design and implementation of a digital up converter (DUC) on a field programmable gate array (FPGA). A DUC converts a low sampled digital baseband signal to a higher sampled passband signal. The proposed DUC system consists of a cascaded integrator comb (CIC) interpolation filter, CIC compensation filter, multiplier, and direct digital synthesizer. The CIC filter upsamples the input signal and the compensation filter compensates for losses in the CIC filter. Two DUCs are connected with an adder to produce a low noise output signal. The DUC is implemented on a Virtex 5 FPGA using VHDL. Simulation and synthesis are performed using Xilinx I
![IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
NOVEL FPGA DESIGN AND IMPLEMENTATION OF DIGITAL UP
CONVERTER
Vipin George1, C.Senthil Singh2
1M.TecH Student, Dept. of ECE, 2Associate Professor, Toc H Institute of Science and Technology, Kerala, India
Abstract
In our world, communication systems play an important role in day to day life. In wireless and wired communication systems, signals
are to be upsampled at the transmitter. Digital up converter (DUC) is a sample rate conversion technique which is widely used to
increase the sampling rate of an input signal. The digital up converter converts low sampled digital baseband signal to a pass band
signal. In this paper, we are going to design and implement a low noise digital up converter on a FPGA (Field Programmable Gate
Array). In digital up converter, the input signal is filtered and converted to higher sampling rate and then it is modulated with the
carrier signal generated from the direct digital synthesizer (DDS). This system consists of a cascaded integrator comb (CIC)
interpolation filter, cascaded integrator comb compensation filter, multiplier and a direct digital synthesizer. The cascaded integrator
comb interpolation filter performs upsampling of the input signal and the cascaded integrator comb compensation filter is used to
compensate the losses of CIC filter by filtering the input signal. The multiplier is used for multiplying the upsampled signal from CIC
filter with the carrier signal generated from DDS and gives the DUC output. In this DUC, the input signal is upsampled at the rate of
eight. Here, two digital up converters are used and connected with an adder in order to obtain a low noise output signal. The coding
of this work is done in VHDL. The simulation and functional verification is carried out using Xilinx ISE and FPGA implementation is
carried out using Virtex 5.
Keywords: Digital Up Converter, Cascade Integrator Comb Filter, Field Programmable Gate Array, Direct Digital
Synthesizer.
----------------------------------------------------------------------***------------------------------------------------------------------------
1. INTRODUCTION
The digital up converter (DUC) is a device which converts
digital baseband signal to a pass band signal [8]. The input
signal is sampled at a relatively low sampling rate. This
baseband signal is filtered and converted to a higher sampling
rate and then modulated with a carrier signal generated from
the direct digitally synthesizer (DDS) [9]. The DUC can be
extensively used in wireless and wire line communication
systems. A DUC system consists of a Cascaded Integrator
Comb (CIC) interpolation filter, CIC compensation filter,
multiplier and a direct digital synthesizer. The input signal is
first fed to CIC compensation filter for filtering input signal,
then it is given to CIC filter for upsampling the filtered signal
and finally it is multiplied with the carrier signal generated by
DDS [8].
In the CIC compensation filter, the programmable finite
impulse response (PFIR) filter and the compensation filter is
present. The PFIR filter is used for pulse shaping the input
signal and upsample the input signal by factor two [9].
Compensation filter is also type of finite impulse response
(FIR) filter used to compensate for loses in cascaded integrator
comb (CIC) filter [7]. A CIC compensation filter is used to
provide ideal pass band and narrow transition region for the
input signal and upsample the input signal by factor two [7].
After filtering, signal is fed to CIC interpolation filter for
larger upsampling. Here, CIC interpolation filter will
upsamples the signal by factor four. The DDS is used for
generating carrier signal and the multiplier is used for
multiplying upsampled signal with carrier signal [9]. The
upsampled signal is given to multiplier. The multiplier
multiplies upsampled signal with carrier signal generated from
DDS and gives DUC output. In this paper, two digital up
converters are used and they are connected with an adder. This
is performed in order to produce a low noise output signal.
Then this system is implemented on Virtex 5.
2. METHODOLOGY
The block diagram of digital up converter (DUC) is shown in
the figure1. A DUC system consists of a Cascaded Integrator
Comb (CIC) interpolation filter, CIC compensation filter,
multiplier and a direct digital synthesizer. These blocks are
described as following.
_______________________________________________________________________________________
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Novel fpga design and implementation of digital up
- 1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 NOVEL FPGA DESIGN AND IMPLEMENTATION OF DIGITAL UP CONVERTER Vipin George1, C.Senthil Singh2 1M.TecH Student, Dept. of ECE, 2Associate Professor, Toc H Institute of Science and Technology, Kerala, India Abstract In our world, communication systems play an important role in day to day life. In wireless and wired communication systems, signals are to be upsampled at the transmitter. Digital up converter (DUC) is a sample rate conversion technique which is widely used to increase the sampling rate of an input signal. The digital up converter converts low sampled digital baseband signal to a pass band signal. In this paper, we are going to design and implement a low noise digital up converter on a FPGA (Field Programmable Gate Array). In digital up converter, the input signal is filtered and converted to higher sampling rate and then it is modulated with the carrier signal generated from the direct digital synthesizer (DDS). This system consists of a cascaded integrator comb (CIC) interpolation filter, cascaded integrator comb compensation filter, multiplier and a direct digital synthesizer. The cascaded integrator comb interpolation filter performs upsampling of the input signal and the cascaded integrator comb compensation filter is used to compensate the losses of CIC filter by filtering the input signal. The multiplier is used for multiplying the upsampled signal from CIC filter with the carrier signal generated from DDS and gives the DUC output. In this DUC, the input signal is upsampled at the rate of eight. Here, two digital up converters are used and connected with an adder in order to obtain a low noise output signal. The coding of this work is done in VHDL. The simulation and functional verification is carried out using Xilinx ISE and FPGA implementation is carried out using Virtex 5. Keywords: Digital Up Converter, Cascade Integrator Comb Filter, Field Programmable Gate Array, Direct Digital Synthesizer. ----------------------------------------------------------------------***------------------------------------------------------------------------ 1. INTRODUCTION The digital up converter (DUC) is a device which converts digital baseband signal to a pass band signal [8]. The input signal is sampled at a relatively low sampling rate. This baseband signal is filtered and converted to a higher sampling rate and then modulated with a carrier signal generated from the direct digitally synthesizer (DDS) [9]. The DUC can be extensively used in wireless and wire line communication systems. A DUC system consists of a Cascaded Integrator Comb (CIC) interpolation filter, CIC compensation filter, multiplier and a direct digital synthesizer. The input signal is first fed to CIC compensation filter for filtering input signal, then it is given to CIC filter for upsampling the filtered signal and finally it is multiplied with the carrier signal generated by DDS [8]. In the CIC compensation filter, the programmable finite impulse response (PFIR) filter and the compensation filter is present. The PFIR filter is used for pulse shaping the input signal and upsample the input signal by factor two [9]. Compensation filter is also type of finite impulse response (FIR) filter used to compensate for loses in cascaded integrator comb (CIC) filter [7]. A CIC compensation filter is used to provide ideal pass band and narrow transition region for the input signal and upsample the input signal by factor two [7]. After filtering, signal is fed to CIC interpolation filter for larger upsampling. Here, CIC interpolation filter will upsamples the signal by factor four. The DDS is used for generating carrier signal and the multiplier is used for multiplying upsampled signal with carrier signal [9]. The upsampled signal is given to multiplier. The multiplier multiplies upsampled signal with carrier signal generated from DDS and gives DUC output. In this paper, two digital up converters are used and they are connected with an adder. This is performed in order to produce a low noise output signal. Then this system is implemented on Virtex 5. 2. METHODOLOGY The block diagram of digital up converter (DUC) is shown in the figure1. A DUC system consists of a Cascaded Integrator Comb (CIC) interpolation filter, CIC compensation filter, multiplier and a direct digital synthesizer. These blocks are described as following. _______________________________________________________________________________________ Volume: 03 Special Issue: 01 | NC-WiCOMET-2014 | Mar-2014, Available @ http://www.ijret.org 124
- 2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 Fig-1: Block Diagram of Digital Up Converter 2.1 CIC Compensation Filter The CIC compensation filter consists of programmable finite impulse response (PFIR) filter and the compensation filter. The PFIR filter provides pulse shaping the input signal and upsample the input signal by factor two. The pulse shaped input signal will given to compensation filter. Compensation filter is just a FIR filter which is used to in order compensate the losses of CIC filter. A CIC compensation filter provides ideal pass band and narrow transition region for the input signal. These properties are not provided by the CIC filters. After filtering, compensation filter upsample the input signal by factor two. 2.2 CIC Interpolation Filter Cascaded Integrator Comb (CIC) filter is first introduced by Eugene Hogenauer. Hence these filters are also called Hogenauer filters. CIC filter consists of N number of cascaded combs and integrator sections. The main advantage of this filter is it does not use any multipliers. This filter consists of only adders, subtractors and registers. Hence they are typically employed in applications that have a large excess sample rate. The CIC filter consists of two types. They are interpolating CIC filter and decimating CIC filer. The interpolating CIC filter is used for upsampling the input signal and the decimating CIC filter is used for down-sampling the input signal. Unlike FIR filters, the decimator or interpolator can be built into the CIC filter architecture. Cascaded Integrator Comb (CIC) interpolating filter can be widely used for up-sampling the input signal in digital up converter. In the case of interpolating CIC filter, cascaded comb sections comes first, then an up-sampler and followed by integrator sections. The detailed structure of a CIC interpolator filter is shown on figure 2. In this work, the CIC filter upsamples the filtered signal at the rate of four. Fig- 2: Structure of CIC Interpolator Filter 2.2.1 Comb The each comb filter consists of a delay element and a subtractor. The detailed structure of a comb filter is shown on figure 3. Fig-3: Structure of a comb filter A comb filters with a sampling rate fs/R and has a rate change of R can be described by yn xn xn RM Where M is the differential delay After taking z transform yz xz z
- 3. xz yz xz1 z
- 4. Then transfer function for comb filter at fs is given by HCz yz xz 1 z
- 5. 2.2.2 Integrator The each integrator filter consists of a delay element and an adder. The detailed structure of a integrator filter is shown on figure 4 _______________________________________________________________________________________ Volume: 03 Special Issue: 01 | NC-WiCOMET-2014 | Mar-2014, Available @ http://www.ijret.org 125
- 6. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 Fig- 4: Structure of an Integrator Filter Here, yn yn 1 xn After taking z transform yz zyz xz xz yz1 z The corresponding transfer function for integrator is given by HIz yz xz 1 1 z Then transfer function for a CIC filter at fs is given by Hz 1 z
- 7. 1 z 2.3 DDS and Multiplier Direct digital synthesizer (DDS) is used to generate a carrier signal in order to modulate with the upsampled signal. Here, multiplier is used for modulating upsampled signal with the carrier signal and gives the DUC output. Then two digital up converters are connected with a ripple carry adder in order to obtain a low noise output signal. 3. RESULTS The simulation and functional verification of this work is done in Xilinx ISE and the FPGA implementation is carried on virtex 5. The figure 5 shows the design summary of this work. For this design, number of slice registers used is 23%, number of slice look up tables used is 21%, number of flip flops used is 11% and number of input output bounds used is 11%. Fig- 5: Design summary Fig- 6: RTL schematic view of this work The figure 6 shows the RTL schematic view of this work. Here in this design in order to obtain a low noise output signal, two digital up converters are connected with a ripple carry adder. The figure 7 shows the output of the low noise digital up converter. Fig- 7: Output of DUC 4. CONCLUSIONS This paper deals with novel FPGA design and implementation of digital up converter. By this design, we successfully designed a digital up converter and then it is implemented on a FPGA. The coding of each block is done in VHDL. The outputs of each blocks is simulated and synthesized in Xilinx ISE. The FPGA implementation of this design is done in virtex 5. REFERENCES [1]. Charanjit Singh, Manjeet Singh Patterh, Sanjay Sharma, “Digital Up Converter for WIMAX System”, International Journal of Engineering Science and Technology 2010. [2] Cummings M, S. Haruyama, “FPGA in the Software Radio”. IEEE Communications Magazine, v37, Feb. 1999. [3]. D.B.Chester, “Digital IF Up Conversion for Economical Wireless Implementations”, Southcon/96Conference Record, June 1996. [4]. Guoying Sun, Yunjie Li, MeiguoGao, Guangli Hu, “Realization of High Data Rate DUC Based on FPGA”, 2010 IEEE. _______________________________________________________________________________________ Volume: 03 Special Issue: 01 | NC-WiCOMET-2014 | Mar-2014, Available @ http://www.ijret.org 126
- 8. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308 [5]. Kharchenko H.V., Tkalich I.O., Vdovychenko Y.I. ASIC-based frequency synthesizer. Proceedings of 10-th IEEE CADSM Conference. [6]. LIN Fei-yu, QIAO Wei-ming, JIAO Xi-xiang, JING Lan, MA Yun-hai “Efficient Design of Digital Up Converter for WCDMA In FPGA Using System Generator”, 2009 IEEE. [7]. Naagesh S. Bhat “Design and ASIC Implementation OF DUC/DDC for Communication Systems”, 2010.IEEE. [8]. Santhosh Y N, NamitaPalacha, Cyril Prasanna Raj “Design and VLSI Implementation of interpolators/decimators for DUC/DDC”, 3rd International Conference on Emerging Trends in Engineering and Technology. [9]. Shilpa. P. Biradar, R. A.Vasmatkar, Shivshanker.P.B and LataTalwar “Design and implementation of low power digital up converter for power line communication systems”, World Journal of Science and Technology 2012. [10]. Wajih A. Abu-Al-Saudand Gordon L. Stüber “Modified CIC Filter for Sample Rate Conversion in Software Radio Systems” ,IEEE signal processing letters, vol. 10, no. 5, may 2003. [11]. X.Xu, X.Xie, and F.Wang, “Digital Up and Down Converter in IEEE 802.16d”, the 8th International Conference on Signal Processing, vol. 1, pp. 16-20, 2006 [12]. Yegor I. Vdovychenko “CPLD-based System for the Quadrature Digital Up converter”, 2010 IEEE. [13]. Yih-Min Chen Computationally Efficient Multichannel Digital Up Converter, 2000 IEEE. [14]. ZawawiN.M, M.F.Ain, S.I.S.Hassan, M.A.Zakariya, C.Y.Hui and R.Hussin“Implementing WCDMA Digital up Converter in FPGA”, 2008 IEEE international RF and microwave conference proceeding. BIOGRAPHIES Vipin George received BE degree in Electronics and Communications from Anna University Of Technology, Coimbatore and currently he is doing M.Tech degree in VLSI and Embedded systems at TocH Institute of Science and Technology under CUSAT university. C. Senthilsingh received the B.E. degree in electrical and electronics engineering from the MS University, India, M.Tech in VLSI design and Currently doing Ph.D. in Information and Comm. in Anna university, Chennai, India. His research interest includes VLSI, Image processing. _______________________________________________________________________________________ Volume: 03 Special Issue: 01 | NC-WiCOMET-2014 | Mar-2014, Available @ http://www.ijret.org 127